JP2000207886A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the chip size to be reduced without increasing the manufacturing cost by arranging common bit lines in the same direction as divided pairs of bit line, wiring one common bit line per divided one pair of bit line, and connecting plural sub-read circuits and plural sub-write circuits to the common bit lines. SOLUTION: A memory cell array 1 consisting of plural memory cells MC11- MC1m is connected to divided pairs of bit line BL1, XBL1. A sub-read circuit 3 and a sub-write circuit 4 are arranged adjacently to the memory cell array 1. A common bit line gBL is arranged in the same direction as the pairs of bit line BL1, XBL1. Plural output of the sub-read circuit 3 and plural input of the sub-write circuit 4 are connected commonly to the common bit line gBL. Thereby, a circuit receiving the common bit line gBL at the time of read-out can be made a logic gate discriminating H or L, and a sense amplifier is made unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a technology effective for increasing the speed, reducing current consumption, and reducing the cost of a hierarchical structure of bit lines to which memory cells are connected.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 59-165292 (hereinafter referred to as "Japanese Patent Laid-Open No. 59-165292")
There is one disclosed in prior art 1). The gist is to form a row-divided memory cell group, a common bit line of the cell group,
By providing a selection circuit for connecting any of the divided bit lines of the cell group to a common bit line by a selection signal based on a row address, a signal delay in a bit line driven by a memory cell is reduced. It is.

[0003] As an example of applying this hierarchical bit line structure to a static random access memory (hereinafter, SRAM), see page 187 of "Low power consumption, high speed LSI technology" published by Realize Inc. on January 31, 1998. (Hereinafter referred to as prior art 2). The point is that a memory cell block is divided into several banks, and a common bit line (referred to as a global bit line in the prior art 2) straddles the banks in parallel with the divided bit lines to which the memory cells are connected. The divided bit line and the common bit line are electrically connected by the bank selection signal, and the data signal of the common bit line is amplified by the sense amplifier, thereby reducing the driving capacity of the memory cell. It achieves high-speed operation and low power consumption.

Further, as an example of another hierarchical bit line structure, Japanese Patent Laid-Open No. 59-165292 (hereinafter referred to as prior art 3) is disclosed.
Are disclosed. The point is that the memory cell data appearing on the divided bit lines is amplified by a sense amplifier,
The complementary output of the sense amplifier is connected to a pair of common bit lines (described as a sub-bit line in Prior Art 2) via a read transistor, and the data of the sub-bit line is amplified by the sense amplifier. This is to reduce the number of memory cells connected to the divided bit lines to increase the speed of the read operation and reduce the power consumption.

[0005] Among the above prior arts, the prior arts 1 and 2 both have a feature that a select gate composed of a MOS transistor is arranged between a divided bit line pair and a common bit line pair. Is a signal line pair where complementary data appears, the common bit line pair uses metal wiring above the divided bit line pair, and the data of the common bit line pair is input to the sense amplifier. It is a feature.

As an example, FIG. 7 is a diagram showing a circuit configuration of the prior art 2, in which memory cells MC11, MC12,.
The divided bit line pair BL1, X to which MC1m is connected
BL1, a selection circuit 7 including Pch transistors 71 and 72, a common bit line pair gBL and XgBL, a sense amplifier 8 and a write amplifier 9 connected to the common bit line pair.
It consists of. Here, BL1 and gBL are data lines to which positive data is output to the memory cell, and XBL1 and XgBL are data lines to which complementary data is output. For example, the memory cell MC
11 is selected, the selection circuit 7 is turned on by the bank selection signal BS, and the divided bit line pair BL1, XBL
1 and the common bit line pair gBL, XgBLg are electrically connected. The memory cell MC11 drives the divided bit line pair and the common bit line pair, and the data signal of the memory cell is finally amplified by the sense amplifier 8 and output.

The prior art 3 particularly relates to a hierarchical bit line structure of a dynamic random access memory (DRAM), in which a sense amplifier is arranged between a divided bit line pair and a select gate. Is different from the prior arts 1 and 2. This is because, as described in Prior Art 3, since the potential difference between bit lines in a DRAM is very small, the memory cells are not directly driven to the common bit lines but are connected to the divided bit line pairs. After amplification by a sense amplifier, the signal is propagated to a common bit line pair via a selection gate, thereby realizing high speed operation. Here, since the sense amplifier connected to the divided bit lines of the DRAM needs rewriting to the memory cell as described in the related art 3, generally, the positive feedback of the CMOS is used. Type latch type sense amplifier is used. This type of sense amplifier amplifies the input of a minute potential difference almost to the power supply voltage, and latches the input in that state.

[0008]

Since the conventional semiconductor memory device is configured as described above, it has the following problems.

The common bit lines of the prior art are all two signal line pairs, and together with the divided bit line pairs, which are also two signal line pairs, two for DRAM cells and four for SRAM cells. Wiring needs to be arranged on one memory cell. Since these bit line wirings are usually formed of a metal such as AL, the metal pitch becomes severe and cannot be arranged in the same wiring layer. For this reason, in the prior art, two wiring layers are required to form a divided bit line and a common bit line, and compared to a semiconductor memory device that does not employ a hierarchical bit line structure, an insulating film is formed and connection holes are opened. , A wafer manufacturing process such as formation of an upper metal layer is added,
There is a problem that the manufacturing cost increases.

Further, since the common bit line pair has a structure to be input to the sense amplifier, an area for arranging the sense amplifier is required below the common bit line group, which is an obstacle to chip size reduction. . Particularly, in the prior arts 1 and 2, the selected memory cell is configured to directly drive the common bit line pair via the bit pair and the selection circuit, and the load capacity driven by the memory cell is reduced by the hierarchical bit line structure. However, the potential difference appearing on the common bit line is very small. In general, in order to amplify the input of the minute potential difference to a high level (hereinafter abbreviated as H) or a low level (hereinafter abbreviated as L) logic signal level at a high speed, for example, a large number of elements such as a double-ended current mirror type sense amplifier are used. It is necessary to use circuits and sense amplifiers connected in multiple stages. In this case, the sense amplifier area is further increased, and there is a problem that the chip size cannot be reduced.

In addition, a CMO similar to the prior art 3 is added to the SRAM.
In the case of using a latch type sense amplifier of the positive feedback type of S, the above-described cell is rewritten. Therefore, it is necessary to start the sense amplifier after data from the memory cell sufficiently appears on the bit line. Timing design is an obstacle to speeding up. In addition, in an asynchronous SRAM having no external clock, it is necessary to operate normally even if skew or off-noise enters the address input. When cell data other than the cell is temporarily output to the bit line, the sense amplifier latches the erroneous data, causing a serious failure that destroys the data of the normal memory cell selected thereafter. I do. Therefore, the prior art 3 has a problem that it cannot be used for an asynchronous memory.

An object of the present invention is to provide a semiconductor memory device having a hierarchical bit line structure capable of reducing the chip size without increasing the manufacturing cost. I do. It is another object of the present invention to apply a hierarchical bit line structure to an asynchronous memory.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device including, as means 1, a bit line pair to which a memory cell is connected is divided into a plurality of bit line pairs in the same column direction. A sub-read circuit that receives at least one bit line of the divided bit line pair, a sub-write circuit that outputs write data to the divided bit line pair, an output of the sub-read circuit, and the sub-write circuit A common bit line to which the input of the common bit line is connected, the common bit line is arranged in the same direction as the divided bit line pair, and one common bit line is wired for each of the divided bit line pair, A plurality of sub-read circuits and a plurality of sub-write circuits connected to the common bit line; The memory cell connected to the divided memory cell is an SRAM cell, wherein the common bit line is a divided bit line pair. 3. The semiconductor memory device according to claim 1 or 2, wherein the SRAM is formed in the same wiring layer as
The cell is a full CMOS cell in which six bulk transistors are arranged per cell, and a power supply wiring and a ground wiring in the cell are wiring layers different from the divided bit pairs, and are orthogonal to the divided bit line pairs. 3. The semiconductor memory device according to claim 3, wherein the sub-read circuit and the sub-write circuit are arranged at the same pitch as the pitch of the memory cells in the word line direction. The semiconductor memory device according to claim 1, 2, 3, or 4, wherein the sub read circuit is a differential sense amplifier having the divided bit line pair as an input. And a driving circuit for driving the common bit line. The semiconductor memory device according to claim 1, 2, 3, 4, 5 or 5, As the differential sense amplifier is a semiconductor memory device means 6, wherein the relative said divided bit line does not have a positive feedback feedback loop.

[0014]

In the semiconductor memory device of the present invention, at the time of reading, the memory cell drives only the divided bit line pair. A sub-read circuit connected to the divided bit line pair performs a read operation by amplifying read data of the divided bit line pair and outputting the data to a common bit line, which is one signal line. At the time of writing, a write operation is performed by converting write data of a common bit line into complementary data by a sub-write circuit and outputting the data to a divided bit line pair.

[0015]

FIG. 1 shows a schematic circuit configuration of a semiconductor memory device showing an example of an embodiment according to means 1 and 2 of the present invention. In FIG. 1, BL1, XBL1
Is a divided bit line pair similar to that of FIG.
A plurality of memory cells MC11, MC12,... MC1m
Memory cell array 1 is connected to a word line sW
The memory cell connected to the word line selected by the word line selection circuit 11 among L1, sWL2,... SWLm outputs data to the bit line pair BL1, XBL1. 3
Is a sub-read circuit that receives at least one of the divided bit line pairs BL1 and XBL1, and 4 is a sub-write circuit that outputs write data to the divided bit line pairs BL1 and XBL1. This sub lead circuit 3
And sub write circuit 4 are both arranged adjacent to memory cell array 1 and read control signal sR output from sub R / W control circuit 12 adjacent to word line selection circuit 11.
D, each of which is controlled by the write control signal sWT.
gBL is the output of the sub read circuit 3 and the sub write circuit 4
Are arranged in the same direction as the divided bit line pair BL1, XBL1, and one common bit line is arranged for each divided bit line pair. A plurality of outputs of the sub-read circuit and a plurality of inputs of the sub-write circuit are commonly connected to the common bit line gBL. Although not particularly limited, for example, a predetermined sub-read circuit or a sub-write circuit is decoded by a decode signal of a row upper address. Selected.

FIG. 2 shows a detailed circuit of FIG.
The memory cell MC11 uses an SRAM cell as an example. The sub read circuit 3 includes an inverter 1 receiving one of the divided bit line pairs BL1 as an input, a Pch transistor 32 and an Nch transistor 35 receiving the output thereof, and a Pch transistor 33 and an Nch transistor receiving the read control signals XsRD and sRD, respectively. 34, and the output of the drive circuit is connected to the common bit line gBL. The sub-write circuit 4 receives the common bit line gBL as an input and the write control signals sWT and XsW
NAND44 and NOR45 each controlled by T,
An inverter 43 and Nch transistors 41 and 42 are provided. The drains of the Nch transistors 41 and 42 output from the sub-write circuit 4 are divided into bit lines BL1 and BL1.
XBL1. The Pch transistors 61 and 62 are connected to the divided bit lines BL1 and XBL1.
And is controlled by a precharge control signal XsEQ to reset the divided bit lines BL1 and XBL1 to a power supply voltage. Here, as shown in FIG. 2, the divided bit line pair BL1 and XBL1 are not electrically connected to the common bit line gBL during any of the read and write operations.
The load capacity of the divided bit line to which the memory cell is connected is not added to BL, and the load capacity of gBL is mainly the wiring capacity. The drain capacitance and the gate capacitance of the plurality of sub-read circuits 3 and the plurality of sub-write circuits 4 are added to gBL, but are negligibly small.

The operation of the semiconductor memory device relating to the means 1 and 2 of the present invention will be described with reference to FIG. Prior to selecting the word line sWL1 at the time of reading, the precharge control signal X
sEQ becomes L, and the divided bit line pair BL1, XB
Both L1 are reset to the power supply voltage. Thereafter, when the selected memory cell MC11 stores, for example, L data, the memory cell MC11 pulls BL1 out of the divided bit line pair to L, and eventually the Pch transistors 63 and 64 whose gates are cross-coupled. Coupled with
The L level of BL1 stabilizes substantially at the ground line potential, and the H level of XBL1 stabilizes substantially at the power supply potential. Here, as an example of the present invention, taking a configuration in which 256 cells are connected to a bit line pair in which the parasitic capacitance per memory cell is divided by 2fF, the capacitance of the divided bit lines BL1 and XBL is taken as an example. Is about 0.5 pF. Generally, in a SRAM cell, a cell current at the time of reading flows about 100 uA. Therefore, if the power supply voltage is 3 V, the bit line BL1 is set to Ｖ VDD (potential of half the power supply voltage =
1.5V) is about 8 ns. Therefore, in FIG. 2 of the means 1 and means 2 of the present invention, the logic level of the bit line is determined by the memory cell within 10 ns after the rise of the word line, and the input level of the inverter 31 is determined. Signal sRD, Xs
If RD is set to H and L respectively, the read data of full swing is output to the common bit line gBL by the sub read circuit 4. The above-mentioned value is a value sufficient for practical use in a product having an access specification of about 70 ns.
During the read operation, the write control signal sWT is fixed at L, and the NAND 44 and the NOR 4 in the sub-write circuit 4
The output of 5 is fixed at H and L, respectively, regardless of the potential of the common bit line gBL, and the Nch transistors 41 and 42 do not conduct.

Next, in a write operation, write control signals sWT and XsWT are set to H and L, respectively, and NA
ND44 and NOR45 are activated. For example, when H write data is output to the common bit line gBL, N
The output of the AND 44 becomes L, the Nch transistor 42 becomes conductive, and the bit line XBL1 becomes L. On the other hand, bit line B
L1 is the output of the NAND 45 is L and the Nch transistor 4
Since 1 does not conduct, the power supply potential at reset remains H, and when the word line sWL1 is selected, H data is written to the memory cell MC11. During the write operation, the read control signals sRD and XsRD are L and H, respectively.
Since it is fixed and the driving circuit in the sub-read circuit 4 has a high impedance, it does not affect the above-mentioned writing operation. Here, in FIG. 2 according to the means 1 of the present invention, an SRAM cell is described as a memory cell. However, a memory cell that outputs complementary data to one word line is not limited to the SRAM cell, and for example, has a 2T2C structure. FRA
M cells may be used.

As described above, in the semiconductor memory device according to the first aspect of the present invention, the common bit line is a single signal line, and the sub read circuit is provided between the divided bit line pair and the common bit line. A feature is that a sub-write circuit is arranged and a divided bit line pair and a common bit line are completely insulated (not connected by a transistor, a transfer gate, or the like). Therefore, since the memory cell only drives the completely divided bit lines, a large amplitude can be obtained in a short time at the time of reading, and the bit line precharge time and precharge current can be greatly reduced. The operation time division bit line is not electrically connected to the common bit line and the wiring capacity is mainly used.Also, the common bit line is driven by a driving circuit having a high driving capability, so that the delay time in the common bit line can be greatly reduced and the access time can be reduced. Can be shortened. Also, since the common bit line is a signal that swings almost full with one wiring, a circuit receiving the common bit line at the time of reading can be a logic gate for determining H or L, and a sense amplifier unlike the conventional device is unnecessary. The size of the device can be reduced by reducing the peripheral circuit area.

Further, since the memory cell is an SRAM cell as in the means 2 of the present invention, the amplitude of the bit line can be increased, so that the read operation by the common bit line, which is one signal wiring, is performed. Can be performed stably. Further, the size of the sub-read circuit can be reduced, and the size of the device can be further reduced.
The SRAM cell is a full CMOS type SR shown in FIG.
In addition to the AM cell, the same effect is obtained in an HR load type SRAM cell in which a high resistance load is stacked on an Nch bulk transistor, and in a TFT load type SRAM cell in which a thin film transistor is stacked on an Nch bulk transistor.

In the semiconductor memory device according to the third aspect of the present invention, the common bit line gBL in FIGS. 1 and 2 is formed by the same wiring layer as the divided bit line pair BL1, XBL1. In the prior art 2 in which the hierarchical bit line structure is applied to the SRAM cell, four bit line wirings per cell are required and cannot be formed in the same wiring layer. It was formed using: On the other hand, according to the means 3 of the present invention, since the number of bit line wirings per cell is three, formation using the same wiring layer is possible. Therefore, it can be realized in a wafer manufacturing process equivalent to that of a semiconductor memory device that does not employ the hierarchical bit line structure, and the hierarchical bit line structure can be realized without increasing the manufacturing cost.

FIGS. 3 and 4 show a memory cell layout of a semiconductor memory device showing an example of an embodiment according to the means 4 of the present invention. FIG. 3 shows a bulk transistor and a first-layer metal wiring, and FIG. Shows the layout of the second and third metal wiring layers. The memory cells shown in FIGS. 3 and 4 are examples of a full CMOS type memory cell,
Driver transistors D1 and D2 and Nch transfer transistors T1 and T2 and Pch load transistors P1 and P2 are integrated in one cell. Poly wirings Pla and Pl in FIG.
b, metal 1 wirings M1a and M1b, contact holes C1 to
Due to C6, two sets of inverters P1 and D1 and P2 and D2 have a flip-flop structure in which the input and output of each other are cross-coupled.
Although not shown, T2 is commonly connected to a plurality of memory cells in the same row of the same memory cell array 1 by a word line Plc. Further, in combination with the wiring layer of FIG. 4, the drain electrodes of T1 and T2 are connected to the contact holes C9 and C9.
10, metal 1 wiring M1e, M1f, hole 1 hole HL1
c, HL1d, and metal 3 wirings M3a and M3b via the metal 2 wirings M2c and M2d. Here, M3a and M3b are the divided bit line pairs BL1 and XBL1 shown in FIGS. 1 and 2, respectively.
Although not shown in FIGS. 3 and 4, the same memory cell array 1
Are connected in the same column. M2a is a ground wiring formed by a metal 2 wiring, and is a hole 1 hole HL1.
a, a metal 1 wiring M1c, connected to the source electrodes of the driver transistors D1, D2 via a contact hole C7, M2b is a power wiring formed of a metal 2 wiring, and is a hole 1 hole HL1b, a metal 1 wiring M1d, a contact hole It is connected to the source electrodes of the load transistors P1 and P2 via C8. The metal 3 wiring M3c is a common bit line, and is not limited to this.
a and M3b.

As described above, the means 4 uses a full CMOS type memory cell, the common bit line is formed of the same metal wiring layer as the divided bit line, and the power supply wiring and the ground wiring in the cell are different from the bit line. It is characterized by being arranged in a direction perpendicular to the bit lines in different metal wiring layers. Full CM
By using the OS memory cell, the amplitude at the time of reading of the bit line divided more stably can be increased, and the low voltage operation can be improved and the high speed operation can be performed in combination with the bit line whose load capacity is reduced by the division. Can be realized. Also,
When combined with a cross-coupled element of a Pch transistor such as 63 and 64 in FIG. 2, the potential of the divided bit line at the time of reading becomes almost full swing, and the steady DC current in the divided bit line becomes zero, Significant reduction in current consumption can be realized. At the same time, a steady DC current does not flow through the sub-read circuit 3 and the sub-write circuit 4 in FIG. 2, so that an auto power-down method represented by word line pulse driving becomes unnecessary, and peripheral circuits related to the auto power-down can be reduced. . Here, similarly to the means 3, an additional wafer manufacturing process for forming a common bit line is not required, so that a low-cost semiconductor memory device can be realized. In addition, since the common bit line, the power supply wiring in the cell, and the ground wiring can both be made of a metal material with low resistance, high-speed operation by reducing the time constant of the common bit line and stable operation by reducing the resistance of the power and ground lines are realized. it can. In the means 4 of the present invention, as shown in FIG. 4, it is desirable that the wiring layer of the divided bit line pair and the common bit line pair be formed above the power supply wiring and the ground wiring. This is because the power supply wiring and ground wiring of the cell are less affected by the parasitic capacitance, while the common bit line,
Since the parasitic capacitance of the divided bit line affects the read time and the precharge current, by using this as an upper layer, the capacitance between wirings can be reduced, and the access time can be further shortened and the current consumption can be further reduced. Here, the above-mentioned metal wiring means a wiring made of AL (aluminum),
Any wiring made of a high melting point metal represented by (titanium) or W (tungsten) may be used as long as the design is made in consideration of the resistivity, and the material is not limited to this.

In the semiconductor memory device according to the means 5 of the present invention, the sub read circuit 3 and the sub write circuit 4 have the same pitch in the word line direction of the memory cells.
As shown in FIG. 2, the sub read circuit 3 and the sub read circuit 4 use P-channel and N-channel bipolar transistors.
It is configured based on a MOS circuit, and in the example of FIG.
A total of eight transistors and ten Nch transistors are used. This number of elements is, for example, a full C using two Pch transistors and four Nch transistors shown in FIG.
This corresponds to four or less MOS type memory cells, and the layout of the sub read circuit 3 and the sub write circuit 4 is full CMOS.
By arranging using the process rule and layout of the S memory cells, the pitch in the word line direction can be arranged the same as that of the memory cells, and the size in the bit line direction can be reduced, so that the device can be significantly reduced in size.

FIG. 5 shows a circuit configuration of a semiconductor memory device showing an example of an embodiment according to the means 6 of the present invention.
Bit line pair BL1, X
It comprises a differential sense amplifier having BL1 as an input and a drive circuit for driving a common bit. In FIG. 7, the Nch transistors 36, 37, 38 and the Pch transistors 39, 310 constitute a differential sense amplifier using a Pch cross couple as a load element. The input divided bit line pair BL1, XBL1 is input to the gate electrodes of the Nch transistors 36, 37. When the read control signal sRD becomes H, the sense amplifier is activated to amplify the bit line potential difference and output the common bit. Send to the line drive circuit. Pch transistors 311 and 312 are sense amplifier output reset circuits, and read control signal sRD is low.
During the equalization or non-selection period,
Reset to. The Pch transistor 32 and the Nch transistors 34 and 35 are driving circuits for a common bit line,
Upon receiving the output of the sense amplifier circuit, the read control signal s
RD is activated during the period of H, and drives the common bit line gBL. Here, in the write period or in the unselected block, the input of the drive circuit becomes H by setting the read control signal sRD to L, and the output of the drive circuit becomes high impedance, so that the write operation is not affected. Also, it does not affect the operation of other selected sub-read circuits connected to the common bit line.

In the means 6 of the present invention, the differential sense amplifier connected to the divided bit line amplifies a small potential difference of the bit line at high speed and supplies an almost full-swing input to the drive circuit. Reading time can be greatly reduced,
A high-speed semiconductor memory device can be realized. Even when the number of memory cells connected to the divided bit lines is large and the load capacity is large, there is no delay in access time, so that the number of memory cells on the same common bit line can be greatly increased, and A large-capacity semiconductor memory device can be realized. In the Pch cross-coupled load sense amplifier as shown in FIG. 5, no DC current flows after amplification, so that a reduction in current consumption of the semiconductor memory device can be realized.

FIG. 6 shows a circuit configuration of a semiconductor memory device showing an example of another embodiment according to the means 6 of the present invention.
The difference from FIG. 5 is that the differential sense amplifier having the divided bit line pair BL1, XBL1 as an input is a current mirror type. By using the current mirror type sense amplifier of FIG. 6, the data of the divided bit lines can be amplified more reliably, and the margin for selecting the word line and the read control signal sRD is not required at all. Speed up.

In the semiconductor memory device according to the seventh aspect of the present invention, the sense amplifier is a CMO using the sense amplifier of the prior art 3.
It is characterized in that the output of the sense amplifier does not have a positive feedback loop with respect to the input as in the case of the positive feedback type latch type sense amplifier of S, and the sense amplifier shown in FIGS. 5 and 6 is one example. In the sense amplifier of FIGS. 5 and 6, the divided bit line which is the input and the output of the sense amplifier are insulated by the gate, and the amplification operation is performed following the data of the divided bit line. Even if erroneous data is output for a moment, the data can be reliably amplified if normal data appears thereafter. Therefore, a stable storage device can be realized without malfunction even if the off-noise as in the prior art 3 enters, and the present invention can be applied to an asynchronous memory. In particular, if the present invention is applied to an SRAM that does not require a refresh operation, the effect is large.

Here, the present invention is not limited to a column division method or a word line selection method, and it goes without saying that the present invention may be combined with the division word line method.

[0030]

As described above, the semiconductor memory device of the present invention has the following effects.

By means 1, the stable operation by increasing the read amplitude of the bit line, the bit line precharge time and the precharge current are greatly reduced, the access time is reduced by reducing the delay time of the common bit line, and the peripheral circuit area is reduced. Thus, a small-sized semiconductor memory device with high stability, high speed, low current consumption and high stability can be realized.

By means 3, a low-cost semiconductor memory device without adding a wafer manufacturing process can be realized.

By means 4, it is possible to realize a low voltage and a great reduction in power consumption. Further, high-speed operation can be realized by reducing the time constant of the common bit line, and stable operation can be realized by reducing the resistance of the power supply / ground line. The peripheral circuits can be reduced by omitting the auto power down control circuit, and the size of the device can be further reduced.

By means 6, the read time can be greatly reduced and a high-speed semiconductor memory device can be realized. Further, the present invention can be applied to a large-capacity semiconductor memory device.

By means 7, even if off noise enters, a malfunction occurs and a stable semiconductor memory device can be realized. Further, the present invention can be applied to an asynchronous semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a schematic circuit configuration diagram of a semiconductor memory device according to means 1 and 2 of the present invention.

FIG. 2 is a circuit diagram of the semiconductor memory device according to the means 2 of the present invention;

FIG. 3 is a memory cell layout diagram of the semiconductor memory device according to the means 4 of the present invention.

FIG. 4 is a memory cell layout diagram of the semiconductor memory device according to the means 4 of the present invention.

FIG. 5 is a circuit diagram of a semiconductor memory device according to means 6 and 7 of the present invention.

FIG. 6 is a circuit diagram of a semiconductor memory device according to means 6 and 7 of the present invention.

FIG. 7 is a circuit diagram of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 memory cell array 3 sub read circuit 4 sub write circuit 6 sub memory cell block 7 selection circuit 11 word line selection circuit 12 sub R / W control circuit MC11, MC12, MC1m memory cell BL1, XBL1 divided bit lines gBL, XgBL common bit Line sWL1, sWL2, sWLm Word line sRD, XsRD Read control signal sWT, XsWT Write control signal D1, D2 Memory cell driver transistor (Nch) T1, T2 Memory cell transfer transistor (Nch) P1, P2 Memory cell load transistor (Pc)
h)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 H01L 27/10 681B 21/8242

Claims (7)

[Claims] 1. A semiconductor memory device comprising a plurality of bit line pairs to which a memory cell is connected divided into a plurality of bit lines in the same column direction, wherein at least one of the divided bit line pairs is inputted. A sub-read circuit, a sub-write circuit that outputs write data to the divided bit line pair, and a common bit line to which an output of the sub-read circuit and an input of the sub-write circuit are connected. The lines are arranged in the same direction as the divided bit line pairs, and one common bit line is wired per pair of the divided bit lines, and the common bit line has a plurality of the sub read circuits and a plurality of the sub read circuits. A semiconductor memory device to which a write circuit is connected. 2. The semiconductor memory device according to claim 1, wherein the memory cells connected to said divided memory cells are SRAM cells. 3. The semiconductor memory device according to claim 1, wherein said common bit line is formed in the same wiring layer as said divided bit line pair. 4. The SRAM cell is a full CMOS cell in which six bulk transistors are arranged per cell, and a power supply wiring and a ground wiring in the cell are formed in a wiring layer different from the divided bit pair. 4. The semiconductor memory device according to claim 3, wherein said semiconductor memory device is arranged in a direction orthogonal to said bit line pair. 5. The semiconductor memory device according to claim 1, wherein said sub read circuit and said sub write circuit are arranged at the same pitch as a pitch of said memory cells in a word line direction.
The semiconductor memory device according to claim 3. 6. The sub-read circuit according to claim 1, wherein said sub-read circuit comprises a differential sense amplifier having said divided bit line pair as an input and a drive circuit for driving said common bit line. 6. The semiconductor memory device according to claim 2, 3, 4, or 5. 7. The semiconductor memory device according to claim 6, wherein said differential sense amplifier does not have a positive feedback loop for said divided bit lines.