JPH0359884A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To use dummy RAM cells for the operation timing of a sense amplifier at the same condition as RAM cells by providing a dummy decoder whose output always becomes active in a sampling period, a dummy word line and the dummy RAM cells. CONSTITUTION:Dummy memory cell 107 rows which are detached from digit lines Qi and Qi+1 are provided, and the dummy decoder 106 to which the signal is inputted by the dummy word line Wj+1 and which makes the output active in the sampling period in spite of an input address is provided. Then, a sense amplifier enable signal is inputted from the terminal of the dummy word line Wj+1 to the sense amplifier 103. Thus, the sense amplifier 103 is speedily operated based on the output of the dummy decoder 106 without giving any influence on read data, and a high speed read operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices, and particularly to a technique for reading data from a high-speed static RAM.

[Prior Art] FIG. 4 shows a conventional example. RAM cell 301 is a general 6
It is a transistor static RAM cell. The sense amplifier 303 has a large current drive capability, and the digit line Q
The minute potential difference between the It groups is rapidly expanded to the ground level and the N source voltage level. However, n-channel type MO5
When FET 309 is off (non-conducting), its operation is stopped.

The read operation will be explained below.

First, when the clock CLK is at logic level "0", 304
Outputs W1 to Wj of all address decoders represented by
is set to "0" and protects the data in the RAM cell.
All digit lines c2 l-Q L by FET
Drunkenness ~ Precharge Drunkenness to "1". In addition, the signal line 31
1 is a p-channel type MOSFET for precharging.
One n-channel type MO5FET represented by T307 and T308 are connected in parallel, and the output of the signal line 311 becomes "1" when the clock CLK is "o". The signal line 311 becomes a sense amplifier enable signal line 310 via an inverter 312.
The level of 0 is changed to "o" by the inverter 312, and the operation of the sense amplifier 303 is stopped.

Next, when the clock CLK changes from "o" to "1", all the precharge p-channel type MO5FETs represented by 305, 306, and 307 turn off, and at the same time, one word selected by the address decoder The line changes from rOJ to "1". For example, word line Wj
is selected and data rOJ is stored in the RAM cell 301, rQJ is stored on the digit line Qi side.
rlJ will be output to the drunken side. Since both digit lines are already precharged to ``1'', there is almost no need for the inverter in the RAM cell to drive current for the Qi side, but for the Qi side, the output is ``0''. Therefore, it is necessary for the inverter in the RAM cell to drive a current to discharge the "1" charge on Qi. but,
The load capacity of the digit line is large, and the MOSFET that constitutes the RAM cell has a small gate channel width and low current driving ability, so the potential fluctuation of the digit line Q1 becomes extremely slow as shown in Figure 5. . During this potential fluctuation, the MO3FET 308 whose gate input is the terminal end of the word line Wj among the j n-channel MO3FETs connected in parallel to the signal line 311 is turned on, and the level of the signal line 311 becomes "0". ”. In response to this, the level of the sense amplifier enable signal line 3100 becomes "1", the sense amplifier 303 starts operating, and the potential of Qi falls sharply as shown in FIG. 5, resulting in a reduction in the data read time. has been realized.

[Problems to be Solved by the Invention] In the conventional example described above, since three n-channel MOS FETs for all word lines are connected in parallel to the signal line 311, the load capacitance of the signal line 311 becomes large. , there is a disadvantage that the level change of the sense amplifier enable signal line 310 from "O" to rlJ is delayed, and the start of operation of the sense amplifier 303 is delayed. This tendency becomes more pronounced as the storage capacity of the storage device increases and the number of word lines increases.
The proportional increase in area occupied by ET groups also poses a problem.

Note that in the method of independently setting the operation start timing of the sense amplifier without using a word line delay, it is difficult to set the delay, and if the sense amplifier starts operating before the word line is selected, the sense amplifier becomes unstable. R due to operation
There is a problem in that data in the AM cell is destroyed.

The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide a semiconductor memory device that avoids the delay in the operation of the sense amplifier and realizes a high-speed read operation.

[Means for Solving the Problems] A semiconductor memory device of the present invention has a memory cell array in which a plurality of memory cells are arranged in rows and columns. In a semiconductor memory device that precharges a digit line, a dummy memory cell row is provided that is separated from the digit line, and a dummy word line supplies power to the dummy memory cell row, and output is not output during a sampling period regardless of the manual address. The present invention is characterized in that a dummy decoder to be activated is provided, and a sense amplifier enable signal is manually applied to the sense amplifier from the terminal end of the dummy word line.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

The RAM cell array 102 has iXj (7) RAM cells 1
01 arranged in a matrix and a dummy memory cell row in which i dummy RAM cells 107 are arranged, iX
It has a storage capacity of (j+1) bits. The dummy RAM cell 107 of 1llllJ is connected to any of the digit lines Q1 to Qi.
, Q1 ~ is not connected to drunkenness. This is because the i dummy RAM cells 107 are always selected during sampling, so the undefined data in the dummy cells 107 and the data in the RAi'vI cell 101 that is originally read are transferred to the digit line Q.
1~Q++-~This is to prevent collisions.

The sense amplifier 103 has a larger current driving capability than the RAM cell 101, and rapidly expands the minute potential difference between the digit lines Q1 to Q1°■ to ■ based on the enable signal from the signal line 108. Further, the decoder 104, the dummy decoder 106, and the precharge circuit 105 are linked to the clock CLK, and during the period when the digit lines Ql-Qi and Q1 to PAGE are precharged by the precharge circuit 105, the output of all the decoders 104 is becomes inactive to prevent data destruction in RAM cell 101 due to precharging. When the precharge is completed and the sampling period begins, the decoder 104 activates only one of the word lines Wl-Wj based on the input address and starts reading data. dummy decoder 10
6 has the same structure as the decoder 104, but does not depend on manual addresses, and always activates the dummy word line Wj+l during the sampling period. Here, as mentioned above, the dummy RAM cell 107 is connected to the digit lines Q1 to Q++U to
Since it is separated from the intoxication, it has no effect on the original read data. And dummy word line W
A signal line 108 is drawn out from the terminal end of j+1, and is supplied to the sense amplifier 103 as an enable signal for the sense amplifier. Therefore, the sense amplifier 103 is quickly operated based on the output of the dummy decoder 106, and the sense amplifier 10
To avoid the delay in the operation start timing of No. 3 and realize a high-speed read operation.

FIG. 2 shows another embodiment of the present invention, in which a specific CMO
The present invention is applied to S static RAM.

The basic configuration and operation are the same as those of the embodiment described above. The dummy decoder 213 has the same structure as the normal decoder 204, and human power other than the clock CLK is fixed to "1". By doing so, it is possible to have almost the same current driving ability as any of the other decoders represented by 204.

Furthermore, the dummy RAM cell 214 constituting the dummy memory cell row has the same structure as the normal RAM cell 210 except that it is not connected to the digit lines Qi and Qi. This makes it easy to match the load capacitance and resistance, including the coupling capacitance between the dummy word line Wj+1 and other wiring constituting the RAM cell, with the load conditions of the original word line represented by Wj. is possible.

Such a dummy decoder 213 and a dummy word line Wj
+1. Due to the configuration of i dummy RAM cells 214, the delay at the end of the dummy word line Wj+1 is Wj
The delay matches the delay at the end of other original word lines, such as the example shown in FIG.

In this embodiment, the signal line 215 is further drawn out from the terminal end of the dummy word line 'vV j + 1 and is used as the sense amplifier enable signal line 210 via the buffer.
In reality, the load seen from the dummy decoder 213 is the signal line 2.
Although the delay is increased by 15, this is a necessary delay. This is because it takes a certain amount of time to generate a certain potential difference between the digit lines Qi and Qi that allows the sense amplifier 303 to operate.

Note that the signal line 215 and the sense amplifier enable signal line 21
The two-stage inverter 212 interposed between 0 and 0 is for dividing the load capacitance, shaping the waveform, and eliminating unnecessary delays.

[Effects of the Invention] As explained above, in the present invention, by providing a dummy decoder, a dummy word line, and a dummy RAM cell whose output is always active during the sampling period, other original RAM cells can be accessed. Under the same conditions as the case, a word-terminated output is always obtained, and this can be used for the sense amplifier operation timing. Therefore, it is possible to always obtain stable operation against variations in manufacturing conditions, operating temperature, and power supply voltage. Furthermore, there is no need for a circuit that performs OR logic for all word lines as shown in the conventional example, and the delay on the path leading to the sense amplifier enable signal 210 can be kept small as shown in the operating waveforms of FIG. This enables higher-speed operation compared to the conventional device shown in FIG. Further, even if the storage capacity of the RAM increases and the number of word lines increases, the present invention is not affected and the speed does not deteriorate as in the conventional example.

Also, when considering the occupied area, for example, RA
Assuming that the size of the M cell is aXa, in the conventional example, the width of the dynamic NOR circuit for all word lines in the word line direction is a/
4, the area will increase by about a2j/4 in an i×j RAM cell array. On the other hand, in the present invention, about a21
The area increases, and when the RAM cell arrangement is j==4i, the area becomes approximately the same. - In boat fishing, many RAM cells are arranged in the digit line direction (j), so the present invention is advantageous in terms of occupied area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, FIG. 3 is an operation waveform diagram of the embodiment of the present invention, and FIG. 4 is a circuit diagram showing another embodiment of the present invention. A circuit diagram showing a conventional example, and FIG. 5 is an operating waveform diagram of the conventional example. 101, 201. 301 102, 202. 302 103, 203 ・ ・ ◆ ・ 104, 204. 304 ・RAM cell, ・RAM cell array, ・Sense amplifier, ・Decoder, 105, 305° 306.307... Precharge circuit, 10
6゜107゜215 ・209 ・213 ・214 ◆ ・Dummy decoder, ・Dummy RAM cell, ・Signal line, ・Sense amplifier control transistor, 108゜0゜1 ・Sense amplifier enable signal line, 307゜308゜to dynamic NOR circuit.

Claims (1)

[Claims] In a semiconductor memory device that has a memory cell array in which a plurality of memory cells are arranged in rows and columns, and that precharges all digit lines of the memory cell array before reading information from the memory cell array by a sense amplifier, the digit lines are separated from each other. A dummy memory cell row is provided, and a dummy decoder is provided which receives input to the dummy memory cell row through a dummy word line and whose output is active during the sampling period regardless of the input address, and a sense amplifier is connected from the end of the dummy word line. A semiconductor memory device characterized in that an enable signal is input to the sense amplifier.