JPS62143289A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To form all the non-selection states of a word line by combining an output signal of an address input circuit bringing a specific internal complementary address signal to a non-selection level with an output signal of an address decoder circuit to form a selection signal. CONSTITUTION:A timing signal phi goes to an L level when a chip selection signal CE reaches the L level, an address decoder DCR brings all word lines to the non-selecting state to precharge complementary data lines D0, the inverse of D0. After the memory state for a long time, a dummy cycle control signal DUM is brought to the L level synchronously with the rising of the signal CE, then an output dum of an inverter circuit N1 goes to an H and when the address signal A0 is at H, a transfer (TR) Q15 is turned on via a TR Q13. When the signal A0 is at the L level, the TR Q15 is turned on via a TR Q12. As a result, the output signal of inverter circuits N2, N3, that is, internal complementary address signals a0, the inverse of a0 go to a non-selection level of L. Thus, all word lines W0-Wn go to the non-selecting state.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory circuit, such as a static RAM built into a digital integrated circuit.
(Random Access Memory).

[Background technology]

A memory cell in a MOS static RAM is, for example, a pair of drive MOs whose gates and drains are cross-coupled.
It is composed of a static flip-flop circuit consisting of a 3FET and its load element, and a pair of transmission gate MO3FETs. The memory array includes a plurality of memory cells arranged in a matrix and a plurality of pairs of complementary data lines, and each complementary data line is coupled to an input/output terminal of a corresponding memory cell.

By the way, static type RAM is used in digital integrated circuits.
It is being considered to have a built-in register and perform operations similar to registers. In order to speed up the operation of such a RAM, it is conceivable to precharge the complementary data lines connected to the input/output terminals of the memory cells using a single shot pulse generated at the end of a memory cycle. By adopting such a precharge method, reading/writing of the memory can be performed simultaneously with memory access.

However, in the above precharge method, the RA
If M is kept in the memory holding state for a relatively long period of time, the precharge potential of the complementary data line will be spontaneously discharged due to source and drain leakage currents of the MOSFETs connected thereto. Therefore, when accessing the memory after such a long memory retention state, a dummy cycle is required to perform the precharge operation. In this dummy cycle, if the word line is set to a selected state as in a normal memory cycle, there is a risk that the information stored in the memory cell will be destroyed by the low level caused by the natural discharge of the complementary data line.

Regarding the static type RAM, see, for example, Japanese Patent Laid-Open No. 198594/1983.

[Purpose of the invention]

One object of the present invention is to provide a semiconductor memory device that can create all non-selected states of word lines with a simple configuration.

Another object of the present invention is to provide a static RAM that realizes high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the combination of the output signal of the address input circuit which sets a specific one or more bits of internal complementary address signals to non-selection level by a predetermined control signal, and the output signal of the address decoder circuit which receives the remaining address signals shall form a selection signal for one word line,
All word lines are rendered unselected by the predetermined control signal.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applied.
A circuit diagram of one embodiment of M is shown.

Although not particularly limited, the RAM in the figure is a well-known 0MO3
(Complementary MO3) is formed on a single semiconductor substrate made of single crystal silicon using integrated circuit technology.

Each MOS FET is manufactured by the so-called self-line technology using a gate electrode made of polysilicon as a kind of impurity introduction mask.

The MOS FET constituting the memory cell is an N-channel type, and is formed on a P-type well region formed on an N-type semiconductor substrate. P channel MO3FET is N
type formed on a semiconductor substrate. N-channel MOS
The P-type well region as the substrate gate of the FET is coupled to the ground terminal of the circuit, and the N-type semiconductor substrate as the common substrate gate of the P-channel MO3FET is coupled to the power supply terminal of the circuit. Note that M constituting the memory cell
The configuration in which the OS FET is formed in the well region is 1. This is effective in preventing erroneous inversion of stored information in memory cells caused by α rays and the like.

The memory array M-ARY includes a plurality of memory cells M arranged in a matrix as a representative example.
The word lines wo, wi to Wn made of C and polysilicon layers, and complementary data lines Do and DO.

Each of the memory cells MC has the same configuration as each other,
One specific circuit is shown as a representative of a storage MO3FET QI, Q2 with its gate and drain cross-wired together and its source coupled to circuit ground.
and high resistance R1, R2 made of a polysilicon layer provided between the drains of the MO3FETs QI, Q2 and the power supply terminal Vcc. And the above MO3FETQ1. Transmission gate) MO3FETQ3, Q4 is connected between the common connection point of Q2 and the complementary data lines DO, Do.
is provided. Transmission gate MO3FETQ3 of memory cells arranged in the same row. Gates such as Q4 are connected to corresponding word lines WO1W1 and W
Input/output terminals of memory cells arranged in the same column and commonly connected to a pair of corresponding complementary data lines (bit lines or digit lines) DO, respectively, are exemplarily shown.

Connected to Do.

In the memory cell, MO3FETs QI and Q2 and resistors R1 and R2 constitute a kind of flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in the memory cell MC, in order to reduce power consumption, the resistor R1 maintains the gate voltage of MO3FETQ2 at a voltage slightly higher than its threshold voltage when MO3FETQI is turned off. The resistance value is set to a significantly high value to the extent that it can be used.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1R2 is MO3FETQI.

The resistance is made high enough to compensate for the drain leakage current of Q2. Resistors R'L and R2 are MOS FETQ2
It has a current supply capacity sufficient to prevent the charge charge accumulated on the gate capacitance (not shown) from being charged.

According to this embodiment, although the RAM is manufactured by CMO3-IC technology, the memory cell MC is composed of an N-channel MO3FET and a polysilicon resistance element as described above.

The memory cell and memory array of this embodiment are made of P-channel MOS FE instead of the polysilicon resistor element described above.
Compared to the case where T is used, the size can be made smaller.

In other words, if a polysilicon resistor is used, the drive MO9
It can be formed stacked with the gate electrode of FET QI or Q2, and its size can be reduced. Unlike when a P-channel MOSFET is used, there is no need to separate the drive MO3FET Q1, Q'l from a relatively large distance, so no wasted blank space is generated.

In the figure, the following address selection circuit is used for words IWO, Wl to Wn to create an all-unselected state. In this embodiment, in order to create a non-selected state for all two lines, the seven lines receive the address signal AO.
input circuit is utilized.

That is, )''dress signal AO is P channel MO3
FETQ12 and N-channel MO3FETQ13 ;',) 'It is supplied to the input terminal of the CMOS inverter circuit. This CMOS inverter circuit (Q12, Q1
The output signal of 3) is a CMOS signal consisting of a P-channel MO3FETQ14 and an N-channel MO3FETQ15.
Input to the inverter circuit.

The output signals of the two CMOS inverter circuits are supplied to cMos inverter circuits N3 and N2, respectively, and the non-5. The internal address signal aO of 1 and the inverted internal address 1 word aO are output.

The non-inverted address signal aO and the inverted address signal a
In order to make both the complementary address signals consisting of
Unlike the MOS inverter circuits N2, N3, etc., the output signal of the circuit N1 is supplied to the CMOS input 8°- which receives the dummy cycle control signal DUM. That is, the electrodes of the N-channel MO3FETs Q13 and Q15, which act as sources ti in the normal operating state, are supplied with a high level voltage such as the power supply voltage Vcc formed by the CMOS inverter circuit Nl receiving the dummy cycle control signal DUM or the circuit voltage. A low level signal dum, such as a ground potential, is supplied.

The inverted address obtained from the above inverter circuit N2 output (word 0 is the P-channel MO3FET Q16 and N
-7-Jannel MOS F E'r" Q17. The output terminal of this CMOS inverter circuit is coupled to the word line WO. The non-inverted address signal aO obtained from the output is connected to the P-channel MO3FET Q18 and the T-channel MOS F
It is supplied to the operating voltage terminal of a CMOS inverter circuit consisting of ETQ19. The output terminal of this CMOS impark circuit is coupled to word line Wl. At the input of these 0MO8 impark circuits, there is an address decoder circuit DC that receives the remaining address signals A1 to Am.
One selection signal di formed by H is supplied to the common source.

Also for other word lines, the inverter circuit N2. N
:Same as 1) Complementary atto L and Sgo numbers aQ and aQ formed by p impark circuit N4- etc. are used as operating voltages, and the inputs are address and output signal di of decoder circuit DCR.
A selection IR nine-way circuit is provided, which includes a P-channel MOSFETQ20, an N-channel MOSF2TQ21, etc.

A pair of complementary data lines Do, D in the memory array
Although not particularly limited, O is directly coupled to the input terminal of the differential sense amplifier. That is, the complementary data line DO
, Do is an N-channel differential amplifier MO3FETQ?
, QB, respectively. These differential M
The drains of the OS FETs Q7 and Q8 are connected to P-channel type MO3FETs Q9. QI
An active load circuit consisting of O is provided. The above differential amplification MO3FETQ7. QB is placed between its common source and the ground potential point of the circuit, and is activated by an N-channel power switch MO5FETQ11 that is turned on by a sense amplifier operation timing signal SaC. Sense amplifiers similar to those described above are also provided on other complementary data lines (not shown). The amplified output signal of the sense amplifier is transmitted by a control signal R to a readout circuit RAO which outputs the amplified output signal. This readout circuit 1? The AO puts its pair of output terminals into a high impedance state or a floating state when in a memory holding state or writing state.

Further, an output terminal of a write circuit WAO is coupled to the complementary data lines DO, Do. This write circuit WA
The operation of O is controlled by the control signal W, and when it is in the operating state, in other words, during a write operation, it outputs a complementary data signal corresponding to the write signal to the complementary data lines DO, DO. Write circuit WA
O puts its pair of output terminals in a high impedance state or floating state when it is in an inactive state, in other words, in a memory holding state or a reading state.

In this embodiment, the complementary data lines DO, DO include:
The following precharge circuit is provided. A pair of complementary data lines DO and 10,000, although not particularly limited, are N-channel MO3F controlled by a precharge signal φp.
Power supply voltage Vcc is supplied via ETQ5 and Q6, respectively. Other complementary data lines (not shown) are also provided with precharge MOSFETs similar to those described above. Note that the precharge MOS FET is the N-channel MO3 mentioned above.
FETQ5. P channel MO8FE instead of Q6 etc.
T may also be used. In this case, an inverted precharge 1 word φp may be supplied.

The control circuit C0NT receives the chip selection signal GE, the read/write Tj; control signal R/W, and the output signal dum of the inverter circuit Nl, and outputs the precharge false signal φp1 as the sense amplifier operation timing signal sa.
c, 'A write signal W, a read signal R, an operation timing signal φ of the address decoder DCR, etc. are formed.

Next, an example of the operation of the static RAM will be described with reference to the timing chart shown in FIG.

Although not shown in the figure, when the nap selection signal A (CB) is set to low level, the timing signal φ is set to low level, and the address decoder DCR sets all outputs to high level to unselect all word lines. .Synchronized with this, one shot of precharge IJ ψp force is generated, and P'J-1-
+-di MO3FETQ5. Q6 etc. are turned on, and the complementary data lines Do, D.

etc. are precharged to high level (Vcc - Vth). Here, vth is MO3FETQ5. This is the threshold voltage of Q6, etc.

If the chip selection signal CE is kept at a low level for a relatively long time, in other words, if the memory retention state continues for a relatively long time,
The complementary data lines DO, D.

The precharge potential of , etc. gradually decreases due to its natural discharge.

When accessing the memory after such a relatively long memory holding state, the dummy cycle control signal DUM is set to a low level in synchronization with the rise of the chip selection signal CE to a high level. by this,
Since the output signal dum of the inverter circuit N1 is set to high level, if the address signal AO is high level, the first stage circuit receiving it
The high level of the output signal dun of the inverter circuit N1 via the inverter circuit N1 is transmitted to its output node. The high level of this output node causes the N-channel MO3F of the next stage circuit to
When the ETQI 5 is turned on, the high level of the output signal dum causes its output/code to go high. Further, when address I δ is at a low level, its output node is set at a high level via the P-channel MO3FETQ12 of the first stage circuit. Due to the high level of this output node, the N-channel MO3 of the next stage circuit
Since FETQi5 is turned on, the above signal dum
A high level causes its output node to also go high/bell. As a result, the output of inverter circuits N2 and N3 is 8
In other words, internal complementary address signals aO and dO are both brought to a low non-selection level in accordance with the low level of the dummy cycle control signal DUM+7), regardless of the level of the address signal AO.

For this reason, 1. Since no operating voltage is supplied to the word line driving CMOS inverter circuit, all word lines WO to Wn are set to low level and non-selection level.

The control circuit C0NT forms a high level precharge signal φp in accordance with the high level of the internal dummy cycle control signal dum. As a result, the complementary data lines DO, DO, etc., which have been naturally discharged due to the leakage current, are precharged to the high level.

In parallel with the above precharge operation, in other words, the address decoder circuit DC is activated by the operation timing signal φ generated by the high level of the chip selection signal CE.
R is the address signal AI or Am input at that time.
is decoded, and after the operation time Td, one selection signal d1 is formed, for example. Before the operating time Td required for decoding these address signals AI to Am has elapsed, the dummy cycle control signal DUM is set to a high level.

As a result, two CMOs receiving the address signal AO
Since the S inverter circuit is given the low level of the internal signal dum, the internal complementary address signal aO9τO is
The level is set to high and low according to the level of the address signal A0. When the address signal AO is at a high level, the non-inverted internal address signal aO is set at a high level, and the P-channel MO is turned on by the low level of the output signal d1 of the address decoder circuit DCR.
The word line WO is set to a high selection level through the 3FET Q16. Note that the word line W1 is connected to the P channel MO by the low level of the decode output signal d1.
The 3FET Q1B is turned on, but is maintained at a low non-selection level by the low level of the inverted internal address signal aO.

In this embodiment, since the complementary data lines DO, DO, etc. are precharged before the word line selection operation,
Write/read operations can be performed immediately if necessary. Note that when this operation cycle is used as a dummy cycle, generation of the sense amplifier operation timing signal sac, etc. is stopped. In this case, the interval between dummy cycles n can be set short.

Then, when the chip selection signal CE is set to a low level, one shot of the precharge signal φp is generated in synchronization with this, and the precharge operation of the complementary data lines Do, DO, etc. is performed again.

After this, when the chip selection signal CE is set to high level after a short period of time, the memory cell selection operation is immediately started.
A write/read operation is performed.

〔effect〕

The effect that all the word lines can be brought into a non-selected state can be obtained by a simple configuration in which one or more bits of complementary address signals specified by fil are both set to a non-selected level.

(2) According to (1) above, the data line connected to the memory cell can be precharged using the decoding time of the address signal of the remaining bits.

This eliminates the need for a special precharge period (
Since the memory cells can be accessed, the memory cycle can be shortened, or in other words, the operation speed can be increased.

(3) In addition to precharging the data line at the end of memory access, when accessing the memory after a relatively long memory retention state, the data line can be easily precharged in a short time using (2) above. This provides the advantage of being able to insert a dummy cycle.

(4) Internal complementary address signals are made to have the same level by a simple configuration in which a voltage at a level according to a control signal is supplied to one operating voltage terminal of a cascade-type CMOS inverter circuit that receives an address signal. be able to. This provides the effect of creating a non-selected state for all memory cells.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, as shown in FIG. 3, a circuit that sets both internal complementary address signals to a non-select level includes two inverter circuits N5. NOR gate circuit G is connected to the output of N6.
1 and G2 may be provided, and the internal dummy cycle control m signal dum may be supplied to the control terminal thereof. Further, the word line drive circuit includes an AND gate circuit G3. G4 may be used.

In addition, the memory cell as a static type RAM is P
Channel MOS FET and N-channel MOS F
A static flip-flop circuit constructed by combining ET may also be used. Further, the complementary data lines may be provided with a column selection circuit to select a pair of complementary data lines from a plurality of complementary data lines and couple them to the sense amplifier or the write circuit.

A memory cell is a storage element that has a threshold voltage higher or lower than the selected level of a word line according to stored information, and is a so-called mask ROM (read-only memory) or EPROM (electronic memory). (program ROM). In such a ROM, when a data line is precharged to obtain a readout signal, a similar address selection circuit is used to achieve low power consumption and high-speed readout.

[Application field]

In the above explanation, the invention made by the inventor of the present application has mainly been explained using as an example the case where it is applied to a static RAM built into a digital integrated circuit, which is the technical field behind the invention, but the invention is not limited to this. It can also be used, for example, in a static RAM built into a one-chip microcomputer, a ROM read by precharge/discharge, or a similar semiconductor memory device as an external memory device.

[Brief explanation of drawings]

Figure 1 shows a static RAM to which this invention is applied.
FIG. 2 is a timing chart showing an example of its operation, and FIG. 3 is a circuit diagram showing a main part of another embodiment of the present invention. M-ARY...Memory array, DCR...Address decoder circuit, MC...Memory cell, WA...Write circuit,
RA...readout circuit, CONT...control circuit

Claims (1)

[Scope of Claims] 1. An address input circuit that sets internal complementary address signals of one or more specific bits to a non-select level by a predetermined control signal, an address decoder circuit that receives the remaining address signals, and this address decoder. A semiconductor memory device comprising: a word line selection circuit that forms a selection signal for one word line by a combination of an output signal of the circuit and one or more bits of complementary address signals formed by the address input circuit. 2. The predetermined control signal is a dummy cycle control signal, and at the end of the memory cycle and by the dummy cycle control signal, the precharge operation of the complementary data line connected to the pair of input/output terminals of the static memory cell is performed. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device forms a precharge signal for precharging. 3. The internal complementary address signals, which are both brought to a non-select level by the dummy cycle control signal, are applied to one voltage terminal of two CMOS inverter circuits in a cascade configuration that receive the address signals, and are set to a high level according to the control signal. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed by supplying level and low level signals.