JP3283672B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory using a ferroelectric.

[0002]

2. Description of the Related Art A ferroelectric random access memory (FERAM) using a ferroelectric material is:
This is a nonvolatile memory that stores data in the polarization direction of the ferroelectric.
An example of such a FERAM is disclosed in JP-A-2-110.
There is an array configuration shown in FIG. Conventional dynamic random access memory (DRAM)
Similarly to the above, the memory cell MC1 and the like include one transistor and one capacitor. However, the capacitor of the memory cell includes a storage electrode, a plate, and a ferroelectric film between the storage electrode and the plate. This memory cell stores information as the direction of polarization of the ferroelectric film. This polarization direction is not lost even when the power is turned off as a characteristic of the ferroelectric substance.

When reading nonvolatile information of a memory cell, all data lines (BL1, BL1 #, BL2, B
L2￣￣￣) is set to Vss, all data lines are set to a floating state, and then one word line (WL1) is set.
Activate. Then, the voltage appearing on each data line is amplified by the sense amplifiers (SA, SA ') connected to each data line of all the data lines, and then the data line is selected and output. Here, the sense amplifiers (SA, SA ') detect information of the memory cells as follows. First, since the plate of the capacitor of the memory cell is at the potential of VDD / 2, the voltage of (Vss-VDD / 2) is applied to the capacitor of the memory cell connected to the word line WL1. Depending on the nonvolatile information, this voltage may be maintained in the same direction as the polarization direction of the ferroelectric of the capacitor of the memory cell, or may be inverted. When the polarization is reversed, a large current flows out of the memory cell. If the polarization does not reverse, there is little current from the memory cell. By detecting this current, nonvolatile information can be read.

[0004]

However, the above F
ERAM has the following problems.

(1) When one memory cell information is read, an unselected data line is also temporarily set to Vss. As a result, the charging / discharging current of the unselected data line becomes unnecessarily large.

(2) When one piece of memory cell information is read, the non-selected data line is also temporarily set to Vss, so that the information of the memory cell connected to the non-selected data line is destroyed.

(3) Since information in a memory cell connected to an unselected data line is destroyed, a sense amplifier is required for each data line to rewrite information in a memory cell in which the polarization of the ferroelectric film is inverted. Becomes As a result, the chip area increases.

Accordingly, an object of the present invention is to reduce the power consumption of a nonvolatile memory using a ferroelectric.

[0009]

In order to achieve the above object, a semiconductor memory according to a representative embodiment of the present invention comprises:
A plurality of word lines (WLf1 to WLfm) and a plurality of data lines (DLf1, DBf1,..., DL
fn, DBfn) and a plurality of memory cells (MCf11, Mf) provided at desired intersections of the plurality of word lines and the plurality of data lines.
CBf11,..., MCfmn, MCfmn), word line selecting means for activating one of the plurality of word lines (WLfi), and data for selecting one of the plurality of data lines (DLfj). Line selection means, and precharge means (PCf1 to PCf1) for setting the potential of each data line of the plurality of data lines to a predetermined potential.
Cfn, PCf0) on a chip, wherein the word line selecting means, the data line selecting means, and the precharging means have a first potential (VDD) and a second potential (VDD).
(VSS), each memory cell of the plurality of memory cells has one field effect transistor and one capacitor, and the one field effect transistor is connected to one word of the plurality of word lines. A gate connected to a line, a source or a drain connected to one of the plurality of data lines, and a drain or a source connected to the one capacitor, wherein the one capacitor is the one A storage electrode connected to the drain or source of the field effect transistor, and a plate electrode (PLf)
And a ferroelectric film provided between the storage electrode and the plate electrode, and after the data line selecting means selects the one data line (DLfj) of the plurality of data lines, The precharge means (PCf0) sets the potential of the selected one data line (DLfj) to the first potential (VDD), and thereafter, the word line selection means sets the potential of the plurality of word lines. The method is characterized in that the one word line (WLfi) is activated (see FIGS. 1 and 2).

In the semiconductor memory according to a preferred embodiment of the present invention, the precharge means (PCf1 to PCfn) may be provided before the data line selection means selects the one data line (DLfj) of the plurality of data lines. Is the potential of the plurality of data lines,
The third potential (VPL) is set substantially equal to the potential of the plate electrode of the capacitor of the plurality of memory cells (see FIG. 2).

A semiconductor memory according to a more preferred embodiment of the present invention further includes one sense amplifier (SAf) provided commonly to the plurality of data lines, and the sense amplifier (SAf) is connected to the data line selection line. Means connected to the one data line (DLfj) of the plurality of data lines selected by the means, and after the word line selecting means activates the one word line (WLfi) of the plurality of word lines, The sense amplifier (SAf) is activated (see FIGS. 1 and 2).

[0012]

According to the semiconductor memory, it is not necessary to set the non-selected data line to the first potential, and the current consumption at that time can be reduced.

According to the semiconductor memory of the preferred embodiment of the present invention, when activating the word line, the potential of the unselected data line is substantially the same as the potential of the plate electrode of the capacitor of the plurality of memory cells. Since the voltage is set to the third potential (VPL), no voltage is applied to the ferroelectric film of the capacitor of the memory cell connected to the unselected data line, and the information of the memory cell is not destroyed.

According to the semiconductor memory of the preferred embodiment of the present invention, since the information of the memory cell connected to the non-selected data line is not destroyed, one sense amplifier commonly provided for the plurality of data lines is provided. (SAf) only, and the memory area can be reduced.

[0015]

FIG. 1 is an embodiment showing a circuit configuration of a memory according to the present invention. In the figure, a word line WLfx
(X = 1,..., M), the data line DLfy and the complementary data line DBfy (y = 1,..., N) are arranged in a matrix,
The memory cell MCfxy is located on the intersection of WLfx and DLfy.
Are connected, and the complementary memory cells MBfxy are connected on the intersections of WLfx and DBfy, thereby forming a memory cell array. DLfy and DBfy are connected to a precharge circuit PCfy and a data line pair selection switch SWfy, respectively. PCfy is a precharge circuit control line PCS.
fy, and supplies the potential of the precharge potential supply line VCSfy to DLfy and DBfy at the time of activation. SWfy is controlled by a column selection signal line YSfy, and connects the selected data line pair to the sense signal line pair DLf0,
Connect to DBf0. DLf0 and DBf0 are connected to a precharge circuit PCf0, a sense amplifier SAf, and an input / output switch SWf0. SAf is controlled by sense amplifier control lines PPf and PNf.
The potential difference between DLf0 and DBf0 is sensed and amplified. SW
f0 is controlled by a column selection signal line YSf0, and DLf
0, DBf0 are connected to the input / output signal line pair I / Of. Note that PCSf1 to PCSfn need not be all individual, and may be connected, for example. VCSf
The same applies to 1 to VCSfn. Also, PCf0
And the precharge operation of DLf0 and DBf0 is P
It may be performed by any of Cf1 to PCfn.

An example of the read operation of the circuit shown in this embodiment will be described with reference to FIG. In this example, the read operation is performed on the selected data line pair, but the unselected data line pair is not operated, and the potential at the standby time is maintained. In the figure, WLfi (i = 1,..., M) represents a selected word line, and DLfj, DBfj (j =
,..., N) represent the selected data line pair and DLf
Here, y and DBfy represent data line pairs not selected. During standby, the word line potential is VS
S, the plate potential of the memory cell capacitor and the data line potential are VPL, the sense amplifier is inactive, the precharge circuit is active, and the selection switch is non-conductive. Further, the potential of the precharge potential supply line VCSf0 is set to VDD, and VDD is supplied to the signal line pair DLf0 and DBf0. VPL is a voltage approximately intermediate between VDD and VSS. At time trf1, the precharge circuit PCfj connected to the selected data line pair is deactivated and Y
The switch SWfj is turned on by Sfj, and DLfj is connected to DLf0 (hereinafter referred to as DLfj-DLf0),
Connect DBfj to DBf0 (hereinafter DBfj-DBf
0). At this time, the potential VDD of VCSf0 becomes DLf
j-DLf0 and DBfj-DBf0. Here, when the potential of PCSf0 is raised to VCH, VDD is sufficiently charged. At this time, the precharge circuit PCfy connected to the unselected data line pair maintains the activated state as in the standby state, and may continue to supply VPL to DLfy and DBfy, or may be deactivated at the same time as PCfj. DLf
y and DBfy may be in a floating state.

As shown in FIG. 3, when precharge circuits are alternately connected to precharge circuit control lines PCSf1 and PCSf2, a precharge circuit adjacent to an inactive precharge circuit can be kept active. become. According to this configuration, the potential of the non-selected data line adjacent to the selected data line can be fixed, and the interference noise due to the capacitance between data lines, which is generated in the non-selected data line due to the potential change of the selected data line, is reduced it can. Note that, for example, three or more precharge circuit control lines may be provided.

Returning to FIG. 2, the description of the read operation will be continued. At time trf2, PCf0 is inactivated, and DLfj-DLf0 and DBfj-DBf0 are brought into a floating state. Next, at time trf3, WL
The potential of fi is raised from VSS to VCH, and the transistors of the memory cells MCfiy and MBfiy connected to WLfi are turned on. Then, the selected memory cell pair MC
The ferroelectric capacitors of fij and MBfij have almost V
The voltage of DD-VPL is applied, and DLfj-DLf0,
A signal potential appears at DBfj-DBf0. At this time, since the potential of the unselected data line pair is almost VPL, WLf
In the unselected cell connected to i, almost no voltage is applied to the ferroelectric capacitor even if the transistor is turned on by WLfi. Therefore, no signal is read from these memory cells, and no information is destroyed.
Here, at time trf4, the sense amplifier SAf is activated by PNf and PPf, and DLfj−DLf0, Dfj
The potential difference between Bfj-DBf0 is sensed and amplified. By this amplifying operation, rewriting is performed on the memory cells MCfij and MBfij whose information has been destroyed by the polarization inversion. At time trf5, the switch S is set by YSf0.
Wf0 is turned on, and DLfj-DLf0, DBfj-D
The signal read to Bf0 is output to I / Of. At this time, it is also possible to write information to the selected cell by giving a write signal from outside. At time trf6, SWfj and SWf0 are turned off and PCf
1 to PCfn to activate DLf1 to DLfn, DBf
The potentials of 1 to DBfn are charged to VPL. Time trf7
In this case, the memory cell array is returned to the standby state by setting the potential of WLfi to VSS to turn off the cell selection transistor. Further, SAf is deactivated, and at time trf8, PCf0 is activated to return the potentials of DLf0 and DBf0 to the standby state, and the read operation ends. In the above read operation, WL
Information is not read from memory cells other than those located at the intersections of fi with DLfj and DBfj. Therefore, unnecessary driving of the data line pair can be omitted, and a memory with low power consumption can be configured. In addition, it is possible to reduce the acceleration of the ferroelectric film fatigue due to unnecessary memory cell driving, and to obtain a highly reliable memory. Although an example in which information is read from a pair of memory cells has been described here, VDD precharge is performed on a plurality of data line pairs, WLfi is set to VCH, and then the data line pairs are sequentially set to DL.
The signal may be connected to f0 and DBf0 to amplify a signal and read out to an input / output line. Needless to say, the same read operation can be performed by using VSS precharge instead of VDD precharge.

As described above, according to the present embodiment described with reference to FIGS. 1 and 2, unnecessary driving of the data line pair can be omitted, so that current consumption during operation can be reduced. further,
The sense amplifier can be shared by a plurality of data lines, and the number of sense amplifiers can be greatly reduced. As a result, the effects of low power consumption and low noise can be obtained, and the area of the sense amplifier can be reduced and the layout margin can be reduced. Further, unnecessary polarization inversion of the unselected memory cell capacitor can be reduced, and fatigue of the ferroelectric can be reduced.

FIG. 4 is an embodiment showing a circuit configuration of a memory according to the present invention. The configuration and arrangement of a memory cell array are changed, dummy data is provided, and data lines and complementary data lines are not arranged. The embodiment differs from the embodiment shown in FIG. 1 in that a line is provided. In the figure, a word line WL
zx (x = 1,..., m) and the data line DLzy (y = 1,
.., N) are arranged in a matrix, and a memory cell MCzxy is connected to the intersection of WLzx and DLzy. Further, a dummy cell DMz1 is connected to an intersection of the dummy word line DWLz and the dummy data line DDLz. As the capacitor of the dummy cell, for example, a capacitor having a larger area than the capacitor of the memory cell is used. The polarization direction of the dummy cell capacitor immediately before the read operation is determined by applying the precharge potential of the selected data line, for example, VDD to the potential of the storage electrode, and the polarization written to the ferroelectric capacitor when VPL is applied to the plate. Set the same as the direction. Thereby, for example, during a read operation similar to that described with reference to FIG. 2, '1' and '
An intermediate voltage of the signal voltage of 0 'is generated in the dummy data line, and information stored in the memory cell is detected. This is because when the polarization of the memory cell capacitor is not inverted during the read operation, the potential of the dummy data line is lower than the data line potential because the effective capacity of the dummy cell capacitor is larger by the difference in capacitor area. On the other hand, when the polarization of the memory cell capacitor is inverted, the current flowing into the capacitor due to the inversion increases the effective capacitance of the memory cell capacitor, so that the potential of the dummy data line becomes higher than the data line potential. . The dummy cell capacitor must be designed so that the effect of increasing the effective capacitance due to the polarization inversion exceeds the effect of increasing the capacitance due to the area difference.
DLzy is connected to the precharge circuit PCzy and the data line selection switch SWzy, respectively. PCzy is
It is controlled by the precharge circuit control lines PCSzo and PCSze, and when activated, supplies the potential of the precharge potential supply line VCSz to DLzy. In the example shown, P
The precharge circuits controlled by CSzo and PCSze are alternately arranged, so that the potential of every other data line can be fixed. SWzy is controlled by a column selection signal line YSzy to sense and amplify the selected data line.
Connect to Lz0. The dummy data line DDLz is
The precharge circuit DPCz is connected to the switch DSWz. DPCz is a precharge circuit control line DPCSz
During activation, supplies the potential of the precharge potential supply line DVCSz to DDLz. DSW
z is controlled by the dummy data line selection signal line DYSz, and connects DDLz to the sensing / amplification signal line DDLz0. DLz0 and DDLz0 are precharge circuits PCz
0, the sense amplifier SAz, and the input / output switch SWz0. PCz0 charges DLz0 and DDLz0. SAz senses and amplifies the potential difference between DLz0 and DDLz0. SWz0 is controlled by a column selection signal line YSz0, and connects DLz0 and DDLz0 to the input / output signal line pair I.
/ Oz. The read operation and the write operation may be performed based on the same principle as in the above-described embodiment.

According to the present embodiment, a higher density memory can be obtained as compared with the array configuration based on the data line pairs as described above. Further, since the potential of the non-selected data line adjacent to the selected data line can be fixed, the influence of interference noise between the data lines can be sufficiently reduced even in such a configuration. Note that a change may be made such as connecting a plurality of dummy cells in an array. Further, in the drawing, another memory cell array may be connected to the dummy cell side with the sense circuit interposed, another dummy cell may be connected to the memory cell array side, and a dummy cell on the opposite side of the memory cell array including the selected cell may be used.

FIG. 5 shows an embodiment of the present invention showing a ferroelectric memory circuit. FIG. 2A shows a memory array configuration,
FIG. 2B shows an address input method for selecting a memory cell in FIG. FIG. 5A is different from FIG. 1 in that a switch SWP1 and the like for selectively driving the sense amplifier SAa1 and the like are provided. FIG. 1 in which a power supply line of a sense amplifier is provided for each sense amplifier
Since the sense amplifier power supply line is shared as compared with the example of the above, the memory array can be highly integrated. Where SWP
Although a selection line YSDa1 for driving 1 and the like is necessary, a wiring thinner than a power supply line may be used, so that high integration is not hindered. Therefore, the configuration is more suitable for highly integrating the memory array. FIG. 5A shows a case in which a read operation is performed by Vss (0 V) precharge, and a switch is provided only for the power supply line on the high potential side of the sense amplifier. V
In the case of DD precharge, it is needless to say that the concept of the embodiment of the present invention can be similarly applied by providing a switch only for the power supply line on the low potential side of the sense amplifier. FIG. 5B shows the memory cell MC in FIG.
It shows an address input method for selecting ai1 and the like. Although the address is input twice, it is characterized in that the second address includes the word line selection information. First, in response to the fall of the first address strobe signal / CS1, an address designating YSaj (selection information of a data line to be connected to a sense amplifier and performing VSS precharge) is fetched. This information is also used to selectively activate the connected sense amplifier, for example, SAai by YSDa1. Next, in response to the fall of the second address strobe signal / CS2, the address specifying the word line WLai and the address specifying the YSSAak (selection information of the sense amplifier connected to the input / output line I / Oa) are changed. It is captured. Here, when only one data line pair is selected by YSaj, and when connected to only one sense amplifier, YSaj
It is not necessary to input SAak in response to / CS2,
When a plurality of data line pairs are respectively connected to a plurality of sense amplifiers by YSaj, YSSAak is required. As a result of the address fetching twice, the information of the specified memory cell is read out, for example, Dout.
Is output as According to the embodiment of the present invention, a block including a selected data line to be VSS precharged and a sense amplifier to be activated is provided first, compared with the input method of inputting the address of the word line first, and the first address input is performed. Read operation immediately afterwards (selective precharge operation)
Can be started, so that a high-speed memory with low power consumption can be obtained. Further, as a result of inputting the address in a plurality of times, the number of address pins can be reduced, and there is an effect that a highly integrated semiconductor memory can be mounted with a small number of pins. By sharing the sense amplifier between a plurality of data line pairs, the area occupied by the sense amplifier can be reduced and the chip area can be reduced, so that there is also an effect that the chip price can be reduced. It is needless to say that the concept of the address input method shown in FIG. 5B can be applied to the memory arrays shown in FIGS. For example, in the case of the memory array of FIG. 1, information on YSfj, PPf, and PNf is fetched in response to a first address strobe signal / CS1, and information on WLfi and YSf0 is received in response to a second address strobe signal / CS2. Information is captured.

FIG. 6 shows an embodiment of the present invention showing a ferroelectric memory circuit. Two memory circuits similar to FIG. 5 are arranged in parallel and further described in detail including peripheral circuits. It was done. Control lines for controlling various switches in the memory array are provided crosswise.
First, the switch for connecting the selected data line to the sense amplifier is connected to the Y selection line YDb1 from the Y decoder YDECb.
2 or the like. Switching timing in a series of information reading and writing operations is controlled by a control line YEb0 crossing the data line. The sense amplifiers SAb1 and the like receive the Y signal from the Y decoder YDECb.
The selection is made by the selection line YDb12 or the like. The timing for activating the selected sense amplifier is controlled by a control line P1b crossing the data line. The timing of connecting the selected sense amplifier to the input / output line I / Ob is controlled by a control line YEb1 crossing the data line. A circuit PCb1 or the like for precharging the data line pair to the potential of the power supply line VCSb, for example, the potential of VDD / 2 is provided for each data line pair. On the other hand, a circuit PCSAb1 or the like for precharging the sense signal line of the sense amplifier to the potential of the power supply line VSAb, for example, the potential of 0 V, is provided for each sense amplifier. The memory cell array includes MCTLb, XABb, YAB
b, XDECb, and YDECb are controlled by peripheral circuits. The control circuit MCTLb receives the input signal / CS
1, input addresses A0 to AN according to the state of / CS2.
Decipher the meaning of. The peripheral circuit XABb is a circuit for generating an X address and finally selecting a word line, for example, WLbi. When the input addresses A0 to AN include the X address in at least a part thereof according to a signal R1b from the MCTLb. If specified, an X address AWb is generated based on the input address. This information is decoded by the X decoder XDECb, and finally the word driver,
For example, XDRVb is activated to select a word line. As described later, the signal XD from XDECb
0b is a signal line PCSbi, PCSSAb1, P1b,
It may be used to select YEb0, YEb1, etc. The peripheral circuit YABb is a circuit for generating a Y address and finally selecting a data line. The signal C1b from the MCTLb specifies that the input addresses A0 to AN include at least a part of the Y address. In this case, the Y address ADb is generated based on the input address. This information is decoded by the Y decoder YDECb, and finally selects a data line and a sense amplifier.

FIG. 7 shows the word driver XDRVb of FIG.
For example, only the driver in which the signal line XD0b is set to the high level and the signal line XEB0 is set to the low level,
Word line WLb is activated. The signal line WPHb is normally at a low level, and the word line potential is fixed at 0 V.
When operating the driver, the driver is set to a high level to operate the driver in accordance with the input of the signal lines XD0b and XEB0.

FIG. 8 is an embodiment of the present invention showing an information reading operation waveform of the memory circuit of FIG. The first address strobe signal / to the control circuit MCTLb
When CS1 goes low, the address signals A0-AN
Is taken in as the data line selection address, and the signal AD
b and YDb1, YDb12, etc. are generated. In parallel with this, the signal line, for example, PCSb1 is set to the low level, and the data line potential is set to the floating state of VDD / 2. Thereafter, when the signal line YEb0 is set to a high level,
For example, data line pair DLb selected by signal line YDb1
1, only DBb1 is connected to sense amplifier SAb1 by switch SWb1. Along with this, DLb1, DB
b1 is precharged to 0 V by the circuit PCSAb1. Other data lines remain at the potential of VDD / 2. Next, the signal line PCSSAb1 is set to low level,
DLb1 and DBb1 are set to the floating state. Further, when the second address strobe signal / CS2 to the control circuit MCTLb goes low, the address signals A0 to AN are taken in as word line selection addresses, and the signals AWb, XD0b, XEBb, etc. are generated. Further, the activation signal W of the word driver shown in FIG.
PHb is also set to a high level. As a result, XD0b, XE
A word line selected by Bb or the like, for example, WLbi is activated. Before the word line is activated, the node potential of the memory cell capacitor on the side facing the plate PLb is at VDD / 2, and DLb1 and DBb1 are in a floating state of 0 V.
The potentials of b1 and DBb1 slightly increase. This potential rise amount is determined by the parasitic capacitance of the data line and the effective capacitance of the ferroelectric capacitor. Here, the memory cell MCbi1
Since the polarization in the opposite direction is written in the ferroelectric capacitors of MBbi1 and MBbi1, a potential difference occurs between DLb1 and DBb1. This is because the potential of PLb is VDD /
2, since DLb1 and DBb1 are almost 0 V, the polarization of the two ferroelectric capacitors is aligned in one direction by activating WLb1. That is, one of the polarizations is inverted. When the polarization is reversed, an extra charge for compensating the polarization is required, and the capacitance of the capacitor is effectively increased.
As a result, the signal potential of the data line on the side where the polarization is inverted becomes closer to VDD / 2. The potential difference between DLb1 and DBb1 generated based on the above principle is determined by the sense amplifier SAb.
1, the signal line P1b is set to a high level. As a result, the sense amplifier S selected by YDb12
Only Ab1 is activated, and one of DLb1 and DBb1 is amplified to VDD and the other is amplified to 0V. At this stage, information is rewritten to the memory cells MCbi1 and MBbi1. When the signal line YEb1 is set to a high level, YDb1
2 is the only input / output line Ib
/ Ob to read information. Note that the activation of the word line WLbi does not destroy the information of the memory cell provided at the intersection between the WLbi and the unselected data line. This is because the potential of the plate PLb and the potential of the unselected data line are both VDD / 2, and no voltage is applied to the ferroelectric capacitors of the unselected memory cells. To end the read operation,
/ CS1 is returned to the high level, and in synchronization with this, the Y addresses ADb, YDb1, YDb12, etc. are returned. Also,
By setting YEb0 to low level, the data lines DLb1, DBb
1 is disconnected from the sense amplifier SAb1 and then PCSb
1 is returned to the high level to precharge the data line to VDD / 2. After the data line is precharged to VDD / 2, the word line WPHb is set to low level to deactivate the word line WLbi. Return to low level in advance. Finally, / CS2 is returned to the high level, and AW
b and XEBb are returned to a low level and a high level, respectively. According to the operation method of the present invention described above, / CS
Since the data line is selectively precharged to 0 V by the first address input information synchronized with one signal, the operation can be performed at a higher speed and with lower current consumption than when the same address information is used for selecting a word line. Become. This is because, when a word line is selected by the first address information, it is necessary to first provide a period for precharging the data line before selecting the word line. Therefore, after precharging the data line, the word line is selected, and the data line and the sense amplifier are selected by the second address information. Therefore, the access time is delayed only during the period for precharging the data lines. Moreover, in this case, it is necessary to precharge all data lines. Therefore, current consumption accompanying data line charging / discharging increases.

In order to carry out the information rewriting operation, YEb1 is set to the high level in FIG. 8 and when the sense amplifier is connected to the input / output line, the sense amplifier is forcibly inverted from the input / output line side. Just do it. Alternatively, for example, without performing the read operation as shown in FIG.
2. With the activation of YDb1 and WLbi, the node on the data line side of the capacitor may be connected to the input / output line for the memory cell whose information is to be rewritten, and the information may be immediately rewritten.

According to the embodiment of the present invention described above with reference to FIGS. 6 to 8, at the time of reading or writing information, only the data line connected to the selected memory cell needs to be charged and discharged. This has the effect of greatly reducing the current consumption. Further, since the address can be input twice, the memory storage capacity can be increased while keeping the number of pins of the package small. In addition, since the first address is used for the selective Vss (0 V) precharge information of the data line, the power consumption is reduced while suppressing the deterioration of the operation speed as compared with the case where the first address is used for the word line selection information. This has the effect of realizing power. Also, when activating the sense amplifier, by providing a switch only on the p-channel field-effect transistor side of the sense amplifier, the circuit is simplified as compared with a case where a switch is provided on the n-channel field-effect transistor side at the same time. This has the effect of reducing the area occupied by the switch circuit. Further, since a configuration in which the sense amplifier is shared between a plurality of data lines is possible, there is an effect that the area occupied by the sense amplifier can be reduced and the chip area can be reduced. In the embodiment of the present invention, the information reading method using the Vss precharge has been described, but it goes without saying that the same can be performed with the VDD precharge.

FIG. 9 is another embodiment of the present invention showing a ferroelectric memory circuit. As compared with FIG.
A feature is that a plurality of sense amplifiers are simultaneously selected by one signal line from DECc1, for example, YDc12, and a plurality of data line pairs are simultaneously selected by one signal line, for example, YDc1. The plurality of data line pairs are respectively connected to different sense amplifiers. FIG. 9 shows an example in which the signal line YDc12 selects two sense amplifiers, and the signal line YDc1 and the like select two data line pairs. The sense amplifiers SAc1 and SAc2 are simultaneously activated under the control of the signal line P1c. The sense amplifiers SAc1 and SAc2 are connected to the signal line YEc1.
Control of the other input / output lines I / Oc1 and I / Oc
2 respectively. For example, at the time of reading information, the output from the sense amplifier is stored in the register RSc, and is selected by the decoder circuit YDECc2.
It is output to the main input / output line I / OMc as appropriate. In this case, for example, the address may be input in the same manner as in FIG. 5B, but in FIG.
Instead of selecting ak, FIG. 9 controls a switch between the register RSc and the main input / output line I / OMc. Alternatively, the control circuit YDECc2 is a counter, and sequentially transfers the information of the register RSc to the main input / output line I / OMc based on the second address. The counter up operation may use an external signal, for example, a / CS2 signal or a system clock signal. According to the embodiment of the present invention, it is not necessary to arrange the signal lines YDc1 and the like and the AND circuit between the YDc1 and the signal lines YEc0 in accordance with the data line pitch.
The interval between c4 and YDc12 can be widened. Therefore, the layout becomes easy, and the chip area does not increase due to the AND circuit. In addition, the current consumption during operation can be reduced as compared with the case where all data lines crossing the word lines are charged and discharged. Further, there is an effect that a series of data can be read and rewritten at high speed while the data is latched in the sense amplifier. That is, FIG.
In a reading method similar to that described in (b), 3
The input addresses after the first time are also made to correspond to the / CS2 signal,
By using the selected word line for selecting the activated sense amplifier, the series of data can be read and rewritten at high speed. Alternatively, an internal address can be generated by a counter based on the second input address, and the information in the register RSc can be continuously read or rewritten.

FIG. 10 is another embodiment of the present invention showing a ferroelectric memory circuit. The point that a plurality of sense amplifiers are simultaneously activated by the control of the signal line YDd12 is shown in FIG.
Is the same as The difference from FIG. 9 is that the simultaneously activated sense amplifiers are selectively connected to the same input / output line I / Od by the control circuit YDECd2. The control circuit YDECd2 is, for example, a counter, which is activated by a sense amplifier group selection signal YDd12, and a series of sense amplifiers are sequentially connected to a common input / output line I / Od by a signal from a signal line YEd1. It goes without saying that the control circuit YDECd2 may be constituted by an address decoder. in this case,
For example, if an address is input in the same manner as in FIG. 5B, a high-speed and low-power-consumption ferroelectric memory can be realized. According to the embodiment of the present invention, the same effect as the embodiment of FIG. 9 is obtained. That is, YDd1 to YDd4, YDd12
Can be widely spaced. Further, current consumption during operation can be reduced as compared with the case where all data lines crossing the word lines are charged and discharged. Further, a series of data can be read and rewritten at high speed while the data is latched in the sense amplifier.

FIG. 11 is another embodiment of the present invention showing a ferroelectric memory circuit. One memory array block MA0-00 or the like has one sense amplifier and i + 1 data line pairs, and is configured, for example, in the same manner as FIG. However, memory arrays are arranged on both sides of the sense amplifier. k + 1 blocks MA0-00
Data line pairs at similar positions of .about.MAk-00 are simultaneously connected to sense amplifiers in each block as intersections of Y address lines, for example, YDM0-0 and signal lines YEU0-0 or YE0D-0 intersecting therewith. Is done. Also, M
K + 1 in each block of A0-00 to MAk-00
Sense amplifiers SA00 and the like are connected to the Y address line YDSA
It is activated as an intersection between −0 and a signal line P1-0 intersecting with −0. The connection of the (k + 1) sense amplifiers SA00 and the like activated at the same time to the input / output line IO00 is selectively performed as an intersection between the Y address lines YDSA00 to YDSAk0 and the signal line P1-0. In the case of FIG.
Units consisting of k + 1 blocks similar to 00 to MAk-00 are arranged in the horizontal direction and in the vertical direction. In this manner, by selecting two intersecting signal lines, information in a memory cell can be selectively read or rewritten.

FIG. 12 is an embodiment of the present invention showing an address input method in a memory circuit similar to FIG.
First, in response to the fall of the first address strobe signal / CS1, the Y address lines YDMs-t, YDSA
-T (0 ≦ s ≦ i, 0 ≦ t ≦ m) and the signal line YE0U
Selection information of -r or YE0D-r, P1-r (0 ≦ r ≦ n), that is, selection information of a data line pair to be precharged to 0V is taken in. Next, in response to the fall of the second address strobe signal / CS2, one of the word lines WL0 (i) and the like and the activated (k + 1) sense amplifiers in the block (t, r) is selected. The selection information of the Y address line YDSAp1t (0 ≦ p1 ≦ k) is fetched. As described above, one input address is appropriately branched as information of the X decoder XDEC and the Y decoder YDEC. According to the embodiment of the present invention described in FIGS. 11 and 12, for the same reason as in FIGS.
There is an effect that the layout of 0 to YDMi-0 or the like becomes easy and current consumption during operation can be reduced. In particular, two intersecting signal lines, eg, YDM0-0 and YE0U-0
And the data line is selected by the logical product of the memory array blocks MA0 passing through the same signal line YDM0-0.
Only MA0-00 can be selected from -00 to MA0-0n, and the above-mentioned effect, that is, the effect of simplifying the layout of signal lines and reducing the current consumption during operation becomes more remarkable. As another effect, there is an effect that a series of data can be read and rewritten at a high speed by connecting sense amplifiers that are simultaneously activated to an input / output line sequentially by a signal line YDSA00 or the like. Further, by increasing the number i + 1 of data line pairs sharing the same sense amplifier, the data line length can be shortened, so that the parasitic capacitance of the data line can be reduced, and as a result, the signal voltage can be increased. . When i is increased, if k is also increased (m is decreased), the signal line Y
DM0-0 to m, ... YDMi-0 to m, YDSA-0
The number of addresses such as m can be made constant. Therefore, the amount of address information for the first time does not increase when the parasitic capacitance of the data line is reduced.

FIG. 13 is another embodiment of the present invention showing a ferroelectric memory circuit. In the embodiment of the present invention shown in FIGS. 1 to 12, a plurality of data line pairs share one sense amplifier, whereas in the present embodiment, a plurality of data line pairs share a plurality of sense amplifiers. . In the previous embodiment, FIG. 11, one memory array block, eg, MA0-00
Are composed of a plurality of data line pairs and one sense amplifier, whereas in FIG. 13, MA0-00 and the like are composed of a plurality of data line pairs and two sense amplifiers.
These MA0-00 and the like are arranged in a matrix like FIG. In FIG. 13, for example, information is read out to one of the two sense amplifiers SA00U and the like, and then latched in the same manner as described with reference to FIG. Sense amplifier SA00U latching data,
By successively selecting SA10U or the like, a series of data can be read at high speed. This is shown in FIGS.
This is the same as the embodiment of the present invention. On the other hand, when information other than the data latched in the sense amplifier becomes necessary,
While accessing data latched in the sense amplifier SA00U or the like, desired information is sensed in the same manner as described with reference to FIG. 8 by using another one of the two sense amplifiers SA00D or the like. Can be read out. It should be noted that the data line and the sense amplifier are disconnected when data is latched in the sense amplifier SA00U or the like. According to the embodiment of the present invention, the information of the memory cells connected to the same word line as well as the information of the memory cells connected to another word line can be read continuously and at high speed. In the embodiment of the present invention, the sense amplifiers that are simultaneously activated are connected to different input / output lines as in FIG. 9, but the input / output lines have the same configuration as in FIGS. 10 and 11. Needless to say, it is good.

[0033]

According to the present invention, a low power consumption, high speed, highly integrated nonvolatile ferroelectric memory is provided.

[Brief description of the drawings]

FIG. 1 shows a configuration of a ferroelectric memory circuit according to the present invention.

FIG. 2 is a read operation waveform of FIG.

FIG. 3 is a configuration of a precharge circuit of FIG. 1;

FIG. 4 shows a memory circuit configuration of the present invention.

FIG. 5 shows a ferroelectric memory circuit (a) of the present invention and its address input method (b).

FIG. 6 is a ferroelectric memory circuit of the present invention.

FIG. 7 is an example of the word line drive circuit XDRVb of FIG. 6;

8 is an operation waveform of the memory circuit of FIG.

FIG. 9 is a ferroelectric memory circuit of the present invention.

FIG. 10 is a ferroelectric memory circuit of the present invention.

FIG. 11 is a ferroelectric memory circuit of the present invention.

FIG. 12 shows an address input method in the memory circuit of FIG. 11;

FIG. 13 is a ferroelectric memory circuit of the present invention.

[Explanation of symbols]

/ CS1, /CS2...address strobe signal, A0 to
AN: address signal, DOUT: output, PPa to PP
f, PNa to PNf: sense amplifier drive line, VSAa to
VSSd: ground line, VCSa to VCSd, VCSf1 to
VCSfn: VDD / 2 power supply line, A0 to AN: Address input signal, R1b: X address control signal, C1
b ... Y address control signal, AWb ... X address signal, ADb ... Y address signal, XD0b, XEBb ...
Word line selection line, PCSai to PCSdi, PCSf1
~ PCSfn: Data line precharge signal, PCSSA
a1 to PCSSAd1, PCSf0: sense precharge signals, P1b to P1d, P1-0 to n: sense amplifier drive signals, YEb1 to YEd1, YE1-0 to n ... sense amplifier / input / output line connection signals, YEb0 to YEd0,
YE0U-0 to n, YE0D-0 to n ... sense amplifiers
Data line connection signals, I / Oa to I / Of, IO00 ... I / O lines, PLa to PLb ... Plate, YDbi to YDd
i, YSai to YStijk, YDM0-0 to YDM0
-M, YDMi-0 to YDMi-m data line selection line,
YDb12 to YDd12, YSDa1, YDSA-0
YDSA-m: sense amplifier selection line, DLai to DLf
i, DBai to DBfi, D00, D00B ... data line, WLai to WLfi, WL0 ... word line, WPHb
... Word driver set signal, YSSAai, YSSA
di, YSf0, YDSA00: sense amplifier / input / output line connection selection line, MCTLb, XABb, YABb, XD
ECb, YDECb: peripheral circuit, XDRVb: word driver, MAb, M00U, M00D: memory cell array, MCaij to MCfij, MBaij to MCfij
... memory cells, PCai to PCfi ... data line precharge circuits, 513-i ... sense amplifier / data line switches, PCSAai to PCSAdi, PCf0 ... sense system precharge circuits, SAai to SAf, SA00, S
A00D, SA00U: sense amplifier, SWSAai ~
SWSAdi, SWf0: switch between sense amplifier and input / output line, MA0-00 to MA0-nm, MAk-00
MAk-nm: Memory array block.

Continuing on the front page (72) Inventor Masakazu Aoki 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Jun Eto 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Ken Sakata 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd.Central Research Laboratories (72) Inventor Masashi Horiguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd.Central Research Laboratories (56) Reference Document JP-A-64-49195 (JP, A) JP-A-63-201998 (JP, A) JP-A-2-110893 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/22

Claims (10)

(57) [Claims] An intersection of a plurality of word lines and a plurality of data lines.
And a storage capacitor connected to a field-effect transistor.
Including ferroelectric film provided between pole and plate electrode
For activating a plurality of memory cells each having a capacitor and one of the plurality of word lines
Word line selecting means for selecting one of the plurality of data lines
Data line selecting means; and information stored in the memory cell.Sensing to detect
A samp, The plate of the capacitor of the plurality of memory cells
Means for supplying a first potential to the electrode; Set the potential of each data line of the plurality of data lines to a predetermined potential
Precharge means for setting, The first data, which is one of the plurality of data lines,
One of the memory cells connected to the data line.
When reading a signal from a certain first memory cell,
Recharging means for connecting the first memory cell;
The potential of the first data line is changed to a second potential different from the first potential.
And among the above data lines
The potentials of the other data lines except the first data line are changed to the first data line.
Precharge to the potential, and then select the word line
A stage is connected to the first memory cell to be read;
A first word line that is one of the plurality of word lines
Activate Semiconductor memory characterized by the above-mentioned. 2. The semiconductor memory according to claim 1, wherein
During the period when the first word line is activated,
Charging means for precharging the first data line;
And stop the data line out of the plurality of data lines.
The potential of the other data lines except one data line is set to the first potential.
A semiconductor memory characterized by being precharged . 3. The semiconductor memory according to claim 2, wherein
The sense amplifier is read from the memory cell.
A semiconductor memory wherein information is amplified to the second potential or the third potential, and the first potential is a potential between the second potential and the third potential. 4. The semiconductor memory according to claim 1 or claim 3, the precharge means is the plurality
Desired data line among the data lines is set to the second potential.
And a plurality of the data lines
Of the data lines other than the desired data line
And a second precharge circuit for setting the first and second positions . 5. The semiconductor memory according to claim 1, wherein said sense amplifier is provided in common to said plurality of data lines, and said sense amplifier is read by said data line selecting means.
One data connected to the target memory cell
A semiconductor memory, which is connected to a line . 6. The semiconductor memory according to claim 4, wherein said sense amplifier and said first precharge circuit are provided in common for said plurality of data lines, and said sense amplifier and said first precharge circuit are provided for said data line. The first precharge circuit is connected to one data line connected to the memory cell to be read by the line selection means, and the second potential is read by the first precharge circuit.
One data line connected to the target memory cell
Semiconductor memory and outputs. 7. The semiconductor memory according to claim 6, wherein said second precharge circuit is a third precharge circuit group connected to each odd-numbered data line of said plurality of data lines, and said plurality of data lines. And a fourth precharge circuit group connected to each of the even-numbered data lines, and when the sense amplifier is activated, the plurality of data lines selected by the data line selecting means are provided. 1
When one of the plurality of data lines is odd, the fourth precharge circuit group is activated. When one of the plurality of data lines selected by the data line selecting means is even, the third precharge circuit group is activated. A semiconductor memory, wherein a group of precharge circuits is activated. 8. The semiconductor memory according to claim 7, wherein said semiconductor memory further comprises one dummy cell in common with said plurality of memory cells, said dummy cell having one transistor and one capacitor, By connecting a selected memory cell of the plurality of memory cells and the dummy cell to the sense amplifier, information recorded in the selected memory cell is amplified, and a capacitor of each memory cell of the plurality of memory cells is amplified. The ferroelectric has a first polarization state and a second polarization state, and the capacitance of the capacitor of the dummy cell is equal to the capacitance of the capacitor of each memory cell of the plurality of memory cells in the first polarization state. A semiconductor memory having a larger capacity than the capacity of the second polarization state. 9. The semiconductor memory according to claim 1, wherein a plurality of said sense amplifiers are provided in common to said plurality of data lines, and said first sense amplifier is inputted from outside of said semiconductor memory . According to the address signal, the data line selecting means is set as the read target.
The semiconductor memory according to claim and this <br/> to one data line connected to the memory cell to be connected to one sense amplifier of the plurality of sense amplifiers. 10. A half of any one of claims 1 to 4.
In the semiconductor memory, the sense amplifier is provided commonly to the plurality of data lines.
AndOf the above semiconductor memory First address signal input from outside
The data line selection meansThe above read target and
One data line connected to memory cells Above
Connected to the amplifier  After the first address signalOf the above semiconductor memoryExternal
The word line selection by the second address signal input from the
Selection means for the plurality of word lines.homethe aboveRead target and
The first memory cell connected to the memory cellActivate word line
A semiconductor memory characterized in that: