JPH036598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

FIG. 1 is a block diagram showing a conventional semiconductor memory device. In the figure, reference numeral 1 indicates memory cells arranged in a matrix, the detailed circuit of which is shown in FIG. A word line for activating the memory cell 1; 4 a row decoder for decoding row address information; 5 a row address signal line; 6a and 6b the bit lines 2a and 2;
Bit line loads are respectively connected to b, and 7 is a power supply terminal.

Note that in the memory cell 1 shown in FIG.
a and 8b are load elements composed of MOS transistors, resistors, etc.; 9a and 9b are inverter transistors; 10a and 10b are access transistors; 11a and 11b are memory cells 1
is a store node.

Next, the operation of the semiconductor memory device having the above configuration will be described, as an example, in the case where store nodes 11a and 11b are written to H level and L level, respectively. First, in the case of reading, when the address information of the cell to be read is input to the address signal line 5, the desired word line 3 is activated through the row decoder 4. When this word line 3 is activated, the access transistor 10b storing the L level
conducts. Therefore, a current flows from the power supply terminal 7 through the path of the bit line load 6b, the bit line 2b, the access transistor 10b, and the inverter transistor 9b, allowing reading.

In a semiconductor memory device with this configuration, all memory cells on the same row are activated, so current flows from the power supply to the memory cells in all columns, and when configuring a large capacity static RAM with many columns, current consumption is reduced. growing. Therefore, in order to reduce current consumption, a semiconductor memory device shown in FIG. 3 has been proposed. In this case, the row decoder 4 is arranged in the center of the memory cell plane, the word line is divided into the left word line 3a and the right word line 3b, and only the word line of the selected memory cell group of the left and right memory cell groups is used. By activating
Current paths are generated only in half of all the columns. Note that 12a and 12b are AND gates that select the left word line 3a or the right word line 3b, respectively, and 13a and 13b are gate signal lines that open the AND gates 12a and 12b, respectively.

Next, FIG. 4 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 3.
In this case, the row decoders 4a and 4b are arranged in a plurality of columns, and the word lines 3a to 3d are divided by a multiple thereof, thereby reducing the number of DC current paths.

However, conventional semiconductor memory devices require a large number of row decoders. For this reason,
There were drawbacks such as an increase in chip area and a loss in speed performance and yield.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-speed, low power consumption, large-capacity semiconductor memory device.

In order to achieve such an object, the present invention includes a plurality of memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided into blocks in the column direction, and a memory cell array corresponding to each of the plurality of memory cell groups. a memory cell group selection line for selecting a specific one of each memory cell group;
a row decoder for decoding row address information of a group of memory cells to be accessed, a preword line connected to an output terminal of the row decoder and arranged across the plurality of memory cell groups, and the plurality of memory cell groups. a divided word line provided corresponding to each of the memory cell group selection lines and activated based on a selection signal of the memory cell group selection line and an output signal of the prefix word line; They are arranged shorter than the word lines, and will be explained in detail below using examples.

FIG. 5 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention, and shows, as an example, a case in which three memory cell groups 1a, 1b and 1c' are arranged in the column direction. In the same figure, 1
4a, 14b and 14c are memory cell group 1
A memory cell group selection line for selecting a to 1c, 15 is a front word line arranged in parallel in the same direction as word lines 3a to 3c, and 16a, 16b and 16c have input terminals connected to front word line 15 and memory, respectively. These are AND gates connected to the cell group selection lines 14a to 14c, and whose output terminals are connected to the word lines 3a to 3c, respectively.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, for example, memory cell group 1a
When selecting a memory cell in the memory cell group 1a, the row address information of the memory cell group 1a to be accessed is decoded by the row decoder 4, and one of the front word lines 15 is activated. Then, when a selection signal is applied to the memory cell group selection line 14a, the AND gate 16a opens and the word line 3a is activated. Therefore, memory cell group 1 is connected from a power supply (not shown) to a bit line (not shown).
The column current flowing into the column a flows only in the column in the selected memory cell group 1a.

Note that although the selection of the memory cell 1 in the memory cell group 1a has been described above, it goes without saying that the same can be done for the other memory cell groups 1b and 1c. Furthermore, although the case where the memory cell group is divided into three has been described, it goes without saying that the same effect can be achieved even if the memory cell group is divided into N (N≧2).
Furthermore, if only the front word line 15 is made of a low-resistance material, the resistance of the word line is somewhat high but the length is short, so the capacitance is small and memory cells can be accessed at high speed. . Further, since the AND gates 16a to 16c have two input terminals and one output terminal, the circuit configuration is simple, so that an increase in chip area can be ignored. Also,
The row decoder 4 may be placed in the center of the chip,
Of course, it may be placed at the edge of the chip.

As described in detail above, according to the semiconductor memory device according to the present invention, row selection is performed hierarchically such that memory cell selection is performed in two stages: front word line and word line. By not only reducing the number of columns with DC current paths in the circuit, but also by making the word lines (divided word lines) shorter than the preceding word lines, high-speed, low-power, large-capacity semiconductors can be realized. This has the effect of configuring a memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional semiconductor memory device, FIG. 2 is a detailed circuit diagram of the memory cell in FIG. 1, FIG. 3 is a block diagram showing another conventional semiconductor memory device, and FIG. 4 is a block diagram showing a conventional semiconductor memory device. FIG. 5 is a layout diagram showing another conventional semiconductor memory device, and FIG. 5 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. 1...Memory cell, 1a and 1b...Memory cell group, 2a and 2b...Bit line, 3, 3a to 3d
...word line, 4, 4a and 4b...row decoder,
5... Row address signal line, 6a and 6b... Bit line load, 7... Power supply terminal, 8a and 8b... Load element, 9a and 9b... Inverter transistor,
10a and 10b...access transistor, 1
1... Store node, 12a and 12b... AND gate, 13a and 13b... Gate signal line, 1
4a-14c...Memory cell selection line, 15...Pre-word line, 16a-16c...AND gate. In addition,
The same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A memory cell array in which memory cells are arranged in a matrix is divided into blocks in the column direction, and a plurality of memory cell groups are provided corresponding to each of the plurality of memory cell groups. a memory cell group selection line for selecting a specific memory cell group; a row decoder for decoding the memory cell group to be accessed and row address information; a prefix word line, and a divided word provided corresponding to each of the plurality of memory cell groups and activated based on a selection signal of the memory cell group selection line and an output signal of the prefix word line. 1. A semiconductor memory device comprising: a semiconductor memory device, wherein the divided word line is arranged shorter than the preceding word line.