JPS6464192A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS6464192A
JPS6464192A JP63072361A JP7236188A JPS6464192A JP S6464192 A JPS6464192 A JP S6464192A JP 63072361 A JP63072361 A JP 63072361A JP 7236188 A JP7236188 A JP 7236188A JP S6464192 A JPS6464192 A JP S6464192A
Authority
JP
Japan
Prior art keywords
word line
memory cell
cell group
high speed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63072361A
Other languages
Japanese (ja)
Other versions
JPH036598B2 (en
Inventor
Kenji Anami
Masahiko Yoshimoto
Hiroshi Shinohara
Osamu Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63072361A priority Critical patent/JPS6464192A/en
Publication of JPS6464192A publication Critical patent/JPS6464192A/en
Publication of JPH036598B2 publication Critical patent/JPH036598B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To obtain a memory at high speed and with low energy consumption by dividing a memory cell into two steps of a pre-word line and a divided word line, selecting a row, decreasing the number of columns of a direct current path, and making the divided word line shorter than the pre-word line. CONSTITUTION:When the cell of a memory cell group la is selected, the row address information to be accessed is decoded by a row decoder 4 and one pre-word line 15 is activated. When a selecting signal is added to a memory cell group selecting line 14a, and AND gate 16a is opened and a divided word line 3a is activated. Consequently, the column in which a column current flows from a power source not shown in the figure through a bit line not shown in the figure into the memory cell group la, is only the column in the selected cell group la. When the divided word line 3a is made shorter than the pre-word line 15, a small capacity is obtained, and a memory cell can be accessed at high speed. By such constitution, the large capacity memory at the high speed and with low energy consumption can be formed.
JP63072361A 1988-03-26 1988-03-26 Semiconductor memory Granted JPS6464192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63072361A JPS6464192A (en) 1988-03-26 1988-03-26 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63072361A JPS6464192A (en) 1988-03-26 1988-03-26 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS6464192A true JPS6464192A (en) 1989-03-10
JPH036598B2 JPH036598B2 (en) 1991-01-30

Family

ID=13487100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63072361A Granted JPS6464192A (en) 1988-03-26 1988-03-26 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS6464192A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319605A (en) * 1991-02-05 1994-06-07 Samsung Electronics Co., Ltd. Arrangement of word line driver stage for semiconductor memory device
US6665228B2 (en) * 2001-06-11 2003-12-16 Infineon Technologies Ag Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319605A (en) * 1991-02-05 1994-06-07 Samsung Electronics Co., Ltd. Arrangement of word line driver stage for semiconductor memory device
US6665228B2 (en) * 2001-06-11 2003-12-16 Infineon Technologies Ag Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory

Also Published As

Publication number Publication date
JPH036598B2 (en) 1991-01-30

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