JPS57105892A - Rewritable non-volatile semiconductor storage device - Google Patents

Rewritable non-volatile semiconductor storage device

Info

Publication number
JPS57105892A
JPS57105892A JP55182294A JP18229480A JPS57105892A JP S57105892 A JPS57105892 A JP S57105892A JP 55182294 A JP55182294 A JP 55182294A JP 18229480 A JP18229480 A JP 18229480A JP S57105892 A JPS57105892 A JP S57105892A
Authority
JP
Japan
Prior art keywords
bit line
selection gates
storage device
semiconductor storage
volatile semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55182294A
Other languages
Japanese (ja)
Other versions
JPS6221200B2 (en
Inventor
Masanobu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55182294A priority Critical patent/JPS57105892A/en
Priority to EP81306062A priority patent/EP0055594B1/en
Priority to IE3036/81A priority patent/IE54406B1/en
Priority to DE8181306062T priority patent/DE3176810D1/en
Priority to US06/333,926 priority patent/US4543647A/en
Publication of JPS57105892A publication Critical patent/JPS57105892A/en
Publication of JPS6221200B2 publication Critical patent/JPS6221200B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30Accessing single arrays
    • G11C29/34Accessing multiple bits simultaneously

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce the write-in time of all zero at test, by providing selection gates and additional circuits, in a rewritable non-volatile semiconductor storage device. CONSTITUTION:Selected word lines WL0-WL255 and bit lines BL0-BL31 are made to high potential, and information 0 is written in a cell MCA at the cross point. All the bit lines are separated into bit line groups BLG0-BLG3, column selection gates G40-G43 are provided corresponding to each bit line group, column selection gates G0-G31 are provided corresponding to each bit line in each group, the selection gates are selectable individually or at the same time with the output of a column decoder CD1, the 2nd selection gate is made selectable in each bit line group with the output of a column decoder CD2, and an additional circuit Z which selects the selection gate at the same time with the column decoder at test when information 0 is written in all the cells, is provided.
JP55182294A 1980-12-23 1980-12-23 Rewritable non-volatile semiconductor storage device Granted JPS57105892A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55182294A JPS57105892A (en) 1980-12-23 1980-12-23 Rewritable non-volatile semiconductor storage device
EP81306062A EP0055594B1 (en) 1980-12-23 1981-12-22 Electrically programmable non-volatile semiconductor memory device
IE3036/81A IE54406B1 (en) 1980-12-23 1981-12-22 Electrically programmable non-colatile semiconductor memory device
DE8181306062T DE3176810D1 (en) 1980-12-23 1981-12-22 Electrically programmable non-volatile semiconductor memory device
US06/333,926 US4543647A (en) 1980-12-23 1981-12-23 Electrically programmable non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182294A JPS57105892A (en) 1980-12-23 1980-12-23 Rewritable non-volatile semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS57105892A true JPS57105892A (en) 1982-07-01
JPS6221200B2 JPS6221200B2 (en) 1987-05-11

Family

ID=16115763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182294A Granted JPS57105892A (en) 1980-12-23 1980-12-23 Rewritable non-volatile semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57105892A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107493A (en) * 1982-12-09 1984-06-21 Ricoh Co Ltd Eprom memory device with test circuit
US4841233A (en) * 1985-06-20 1989-06-20 Fujitsu Limited Semiconductor integrated circuit adapted to carry out operation test

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025500U (en) * 1988-06-17 1990-01-16

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107493A (en) * 1982-12-09 1984-06-21 Ricoh Co Ltd Eprom memory device with test circuit
US4841233A (en) * 1985-06-20 1989-06-20 Fujitsu Limited Semiconductor integrated circuit adapted to carry out operation test

Also Published As

Publication number Publication date
JPS6221200B2 (en) 1987-05-11

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