JPS54110742A - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS54110742A JPS54110742A JP1777378A JP1777378A JPS54110742A JP S54110742 A JPS54110742 A JP S54110742A JP 1777378 A JP1777378 A JP 1777378A JP 1777378 A JP1777378 A JP 1777378A JP S54110742 A JPS54110742 A JP S54110742A
- Authority
- JP
- Japan
- Prior art keywords
- line
- erasion
- level
- memory
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
Abstract
PURPOSE:To increase the degree of integration by collecting the memory cells in the word-based system and then providing a switch transistor to each word. CONSTITUTION:The 1st and 2nd memory cells 11a and 11b are composed of memory transistors Q11 and Q11' plus switch transistors S11 and S11', and the memory unit 11 is composed with every 2 bits with the above two memory cells. And memory unit selecting switch transistor T11 is provided to each memory unit. Line selection line L11 is set to L level, and the writing pulse is applied to writing line W11 to carry out writing into Q11 and Q11'. After this, the erasion pulse is applied to erasion line E11 or E11' to perform the erasion of Q11 or Q11'. For the reading. L11 is set to H level and the reading voltage is applied to W11 to check the level for row selection line R11 and R11'.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53017773A JPS582438B2 (en) | 1978-02-17 | 1978-02-17 | Non-volatile semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53017773A JPS582438B2 (en) | 1978-02-17 | 1978-02-17 | Non-volatile semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54110742A true JPS54110742A (en) | 1979-08-30 |
JPS582438B2 JPS582438B2 (en) | 1983-01-17 |
Family
ID=11953024
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53017773A Expired JPS582438B2 (en) | 1978-02-17 | 1978-02-17 | Non-volatile semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS582438B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5769584A (en) * | 1980-10-15 | 1982-04-28 | Toshiba Corp | Non-volatile semiconductor memory |
JPS5769583A (en) * | 1980-10-15 | 1982-04-28 | Toshiba Corp | Non_volatile semiconductor memory |
JPS6052999A (en) * | 1983-07-11 | 1985-03-26 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Memory device |
JPS60229300A (en) * | 1984-03-01 | 1985-11-14 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Eeprom type memory |
US9030877B2 (en) | 2007-08-30 | 2015-05-12 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105429094B (en) | 2015-12-16 | 2018-02-16 | 南京南瑞继保电气有限公司 | A kind of apparatus and method for ensureing intelligent substation trip protection reliability |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51147280A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Semiconductor device |
-
1978
- 1978-02-17 JP JP53017773A patent/JPS582438B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51147280A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Semiconductor device |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5769584A (en) * | 1980-10-15 | 1982-04-28 | Toshiba Corp | Non-volatile semiconductor memory |
JPS5769583A (en) * | 1980-10-15 | 1982-04-28 | Toshiba Corp | Non_volatile semiconductor memory |
JPS628877B2 (en) * | 1980-10-15 | 1987-02-25 | Tokyo Shibaura Electric Co | |
JPS628876B2 (en) * | 1980-10-15 | 1987-02-25 | Tokyo Shibaura Electric Co | |
JPS6052999A (en) * | 1983-07-11 | 1985-03-26 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Memory device |
JPS60229300A (en) * | 1984-03-01 | 1985-11-14 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Eeprom type memory |
US9030877B2 (en) | 2007-08-30 | 2015-05-12 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Also Published As
Publication number | Publication date |
---|---|
JPS582438B2 (en) | 1983-01-17 |
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