JPS582438B2 - Non-volatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a memory device using an MIS type nonvolatile semiconductor element having a floating gate as a memory element.

If the MIS type nonvolatile memory transistor with a floating gate is a P-channel type, when a negative pulse (hereinafter referred to as a write pulse) larger than a write critical voltage is applied to the control gate of this memory transistor,
The threshold voltage Vt of this memory transistor changes in a more negative direction, and even after the write pulse disappears, this value of Vt is maintained, and data is written. When a negative pulse greater than the erase threshold voltage (hereinafter referred to as erase pulse) is applied to the drain of a transistor, the threshold voltage Vt of this memory transistor changes in the positive direction, and the value of Vt remains unchanged even after the erase pulse disappears. This means that the data has been erased while maintaining the .

Therefore, the value of Vt after writing and erasing is set to the logic state "0", respectively.
By making it correspond to "1" and "1", information can be stored.

When constructing a memory array using a large number of memory transistors as described above, a circuit configuration as shown in FIG. 2, for example, has conventionally been used.

That is, FIG. 2 is a circuit diagram showing a part (4 bits) of a memory array constituting a memory device using this type of memory transistor as a memory element. is the memory transistor as mentioned above, and T211, T212, T
221, T222 and S211, S212, S221,
S222 indicates switch transistors, and these switch transistors are MIS-type enhancement transistors.

Then, one memory transistor Q211 etc. and two switch transistors T211 and S211 etc. total 3.
memory cells 211, 212,
222, and these memory cells are arranged in a matrix to form a memory array.

That is, memory cells 211, 212 (or 221, 22
2) switch transistors T211, S211, T2
12, T212 (or T221, S221, T222,
The row selection line L21 (or L22) is connected to the gate of S222).
are connected, and memory transistors Q211, Q2
21 (or Q212, Q222) source is column selection line R
2 (or R22).

Furthermore, switch transistors T211, T221 (or T
212, T222) is connected to the write line W21 (or W
22), and the switch transistor 821
1, the drain of S221 (or S212, s222) is connected to the erase line E21 (or E22).

and memory transistor Q211 (or Q212, Q
221, Q222) is a switch transistor T211 (or T212, T221, T22).
2), and its drain is connected to the source of the switch transistor S211 (or s212, S221, S222).

For example, the memory transistor Q of the memory cell 211
When writing to 211, the row selection line L21 is set to "L" level with a negative voltage larger than both the write critical voltage and the erase critical voltage, and a write pulse is applied to the write line W2. .

Then, due to the conduction of the switch transistor T211, a write pulse is applied only to the control gate of the memory transistor Q211, and writing as described above is performed, while other memory cells are not affected in any way.

Next, when erasing Q211, the column selection line L2
1 is set to the "L" level as before, and an erase pulse is applied to the erase line E21.

Then, the switch transistor S211 becomes conductive, so that an erase pulse is applied only to the drain of the memory transistor Q211, and while the above-described erasure is performed, other memory cells are not affected in any way.

Next, when reading the memory contents of the memory transistor Q2,1, the row selection line L21 is set to the "L" level as described above, a negative voltage smaller than the erase critical voltage is applied to the erase line E21, and the write line W21 A read voltage vR of an appropriate level smaller than the write critical voltage is applied to.

The level of this read voltage ■R is determined by each memory transistor Q2.
Since the value is selected to be intermediate between the Vt after writing and the Vt after erasing, such as 11, Q211 is turned off after writing and turned on after erasing.

Therefore, by checking the level of this time column selection line R21, it is possible to identify whether the memory transistor Q211 is on or off, that is, whether data is written or erased.

In this case, when the row selection line L22 is at "H" level (substrate level), the switch transistors T221 and S
221 are both off, so the memory transistor Q2
The state of R21 has no effect on the level of column selection line R21.

In this way, the memory array shown in Figure 2 allows writing, erasing, and reading from the memory transistor of any memory cell, and by adding a decoding circuit, the memory array can be converted to an appropriate bit width and number of words. It is possible to use it as

However, such a configuration requires three transistors for each memory cell, and for example, a contact hole is required in the integrated circuit to connect the source of the switch transistor T211 to the gate of the memory transistor Q211. There were limits to the improvement of the degree of integration.

The present invention has been made in view of the above circumstances, and provides a non-volatile semiconductor in which memory cells are grouped into words and one switch transistor is provided for each word, thereby improving the degree of integration. DESCRIPTION OF THE PREFERRED EMBODIMENTS For the purpose of providing a memory device, the present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a circuit diagram showing a part of a memory array which is a main part of a non-volatile semiconductor memory device according to the present invention, in which Qll, Q'll, Q12, Q'l2, Q21
, Q'21, Q22, Q'22 are MIS type nonvolatile memory transistors having floating gates, S1
1, S'11, S12, S'12, S21, S'21,
S22 and S'22 are MIS type enhancement type switch transistors, T11, T12, T21, T22
are memory unit selection switch transistors using the same<MIS type transistors.

Therefore, the memory device according to the present invention includes one memory transistor, for example, Qll, one switch transistor,
For example, S11 is used to configure a 1-bit memory cell, for example 11a, and a plurality of memory cells 11a, etc. (in the illustrated embodiment, two cells, that is, 11a and 11b) are arranged in parallel to correspond to one word. memory unit (in the illustrated embodiment, 2 bits = 1 word), for example, 11, and one memory unit selection switch transistor, for example T11, is provided for each memory unit. The unit selection switch transistor, for example, Tll, and the switch transistor SllyS'll that constitutes the associated memory cells l1a and 1lb are characterized in that they are configured to give a common signal.

That is, memory transistor Q1, (or Q12, Q
21tQ22) and the switch transistor S11 (or Sl2, S2, , S22) constitute a 1-bit first memory cell 11a (or 12a, 21a, 22a), and the memory transistor Q'11 (or Q'12, Q'2
1+Q'22) and the switch transistor S'11 (or S'12, S'21, S'22)
memory cells 11b (or 12b, 2lb, 22b) are configured, and these two memory cells constitute memory units 11 (or 12, 21, 22) of 2 bits each, and each memory unit has a A unit selection switch transistor T11 (or T12, T21, T22) is provided.

In the figure, Lll is a row selection line for selecting memory unit 11.12, L12 is a row selection line for selecting memory unit 21.22, and R11 is memory cell 11a, 21a.
Column selection line for selection, R'H is memory cell 1lb, 2
Column selection line for lb selection, R12 is memory cell 12a
, 22a, R'12 is a column selection line for selecting memory cells 12b and 22b, W1 is a write line for writing to memory unit IL21, and W12 is a column selection line for memory units 12 and 22. Writing line for writing, E
11 is an erase line for erasing memory cells 11a and 21a, E'11 is an erase line for erasing memory cells 1lb and 2lb, and E12 is an erase line for memory cells 12a and 22
E'12 is an erase line for erasing memory cells 12b and 22b.

Next, using the memory unit 11 as an example, the connection between each of the above lines and each transistor will be explained.
. connected to the source.

The drains of switch transistors S11 and S'11 are connected to erase lines Ell and E'll, respectively.

Further, the gates of the switch transistors S11, S/11 and the memory unit selection switch transistor T11 are all connected to the row selection line Lll, and the drain of the memory unit selection switch transistor Tll is connected to the write line W1.
,It is connected to the.

Such connections are the same for the other memory units 12, 21, and 22.

Next, write/write data to each memory transistor in the circuit described above.
Erasing and reading will be explained using the memory unit 11 as an example.

First, the row selection line Lll is set to "L" level, and the write line W1,
Apply a write pulse to.

Then, the memory unit selection switch transistor Tl
1 becomes conductive, a write pulse is applied to the control gates of memory transistors Qll and Q'll, and writing is performed to both memory transistors Qll and Q'11.

After that, when an erase pulse is applied to the erase line EH or E'11 while keeping the row selection line Lll at the "L" level, the memory transistor Qll or Q'11 is turned on because the switch transistors S and 11S'11 are conductive. An erase pulse is applied to the drain of the memory transistor Qll or Q depending on whether the erase pulse is applied to the erase line Ell or E.
'11 is erased.

During such writing/erasing, the row selection line L12 and the write line W
12. If the erase lines E12 and E'12 are kept at the "H" level, no change in state, ie, writing or erasing, will occur in the memory transistor Q12, etc. of other memory units.

Next, for reading, the row selection line Lll is set to the "L" level, a negative voltage smaller than the erase critical voltage is applied to the erase lines E11 and E'tt, and the read voltage 1 as described above is applied to the write line W11.
This is done by applying R and checking the levels of column selection lines R11 and R'11.

Since the memory transistor Q11+Q'tt is off after writing and on after erasing, its off/on state can be determined by checking the levels of column selection lines R, 1, and R'll, respectively. It is possible to identify whether data is written or erased.

In the memory device of the present invention as described above, if a memory unit in which writing and reading are performed simultaneously, that is, one word, has an n-bit configuration, 2n+1 transistors (if n=2 as in the embodiment) As shown in Figure 2, the number of transistors can be significantly reduced compared to the case where 3 transistors are required for each bit, which requires 3n transistors for each n bit, as shown in Figure 2. I can figure it out.

Also, focusing on one memory cell, since this memory cell connects the drain of the memory transistor Q1, etc. and the source of the switch transistor Sll, etc., a contact hole in the integrated circuit is unnecessary.

Of course, the memory unit selection switch transistor Tll
A contact hole is required to connect the sources of the memory transistors Q11, Q'11, etc. to the control gates of the memory transistors Q11, Q'11, etc., but the number of memory cells constituting the memory unit,
That is, regardless of the number of memory transistors, one contact hole is sufficient for each memory unit.

In this way, according to the present invention, it is possible to reduce the number of transistors used and the number of contact holes.
As a result, the degree of integration can be greatly improved.

In the above embodiment, one word has a 2-bit configuration, but
It is also easily possible to configure one word with three or more bits.

Furthermore, even when manufacturing memory transistors and switch transistors using N-channel type integrated circuit technology instead of the P-channel type as described above, the present invention can be applied as is, just by reversing the voltage polarity. Of course.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing a part of a memory array which is a main part of a non-volatile semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a part of a memory array of a known non-volatile semiconductor memory device. It is a circuit diagram showing a part. Q11, Q'11...Q'22...Memory transistor, Sll, S'll...S/
22...Switch transistor, T11, T'
t2, T21, T22...Switch transistor for memory unit selection, 11a, 11b...22
b...Memory cells 11, 12, 13, 14...
...Memory unit.

Claims (1)

[Claims] 1 using one switch transistor and one nonvolatile memory transistor with a floating gate.
A bit memory cell is configured, a plurality of the memory cells are arranged in parallel to configure a memory unit, one memory unit selection switch transistor is provided for each memory unit, and the memory unit selection switch 1. A nonvolatile semiconductor memory device characterized in that a common signal is applied to switch transistors constituting a transistor and a memory cell associated therewith.