JPH1186574A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which a noise can be prevented from being generated by flowing in a wiring and the like at the time of reading out data and from varying threshold voltage of a read-out cell apparently and highly accuracy read-out operation can be realized. SOLUTION: A bit line BL is kept in a floating state after it is charged to 0V at the time of read-out operation, strings are selected, while voltage VSL is applied to a source line SRL, higher voltage Vth (unsel) than voltage obtd. by adding threshold voltage Vth (0) when data is 0 to source line voltage VSL is applied to gates of unselected memory transistors MT10-MT12 and MT14-MT17, and the bit line BL is charged to difference voltage between gate voltage VCG (sel) of a selected memory cell transistor MT13 and threshold voltage Vth of the memory cell transistor MT13 or source line voltage VSL by charging operation of the bit line BL by string.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable nonvolatile memory, for example, a flash EEPROM.
M (Electrically Erasable Programmable Read Only Me
mory) and the like.

[0002]

2. Description of the Related Art FIG. 6 shows a NAND flash EEPROM.
FIG. 3 is a diagram illustrating a memory array structure of an OM. NAN of FIG.
The D-type flash EEPROM shows a memory array in which eight memory cell transistors MT0 to MT7 are connected to one NAND string connected to one bit line BL for convenience. FIG. 6 shows a bias for a selected string at the time of reading.

In a memory string, the control gate CG of each of the memory cell transistors MT0 to MT7 is
Are connected to word lines WL0 to WL7, respectively.
The drain of the memory cell transistor MT0 is connected to the bit line BL via a selection transistor DST1 composed of an NMOS transistor whose gate electrode is connected to the selection signal supply line DSG1, and the source of the memory cell transistor MT7 has a gate electrode connected to the selection signal supply line DSG1. Select transistor S composed of NMOS transistor connected to SSG1
It is connected to the source line SRL via ST1.

Incidentally, a NAND flash EEPROM is used.
In general, a first p-well for a cell array region and a second p-well for a peripheral circuit region are formed in an n-type semiconductor substrate, and a gate insulating film, a floating gate, A memory cell is formed by laminating an interlayer insulating film and a control gate. An NMOS transistor of a peripheral circuit is formed in a second p-well, and an n-well for a PMOS transistor is formed in the second p-well. You.

In the NAND flash EEPROM having such a structure, when performing an erasing operation,
When a high voltage of, for example, about 20 V is applied to the n-type substrate and the p well and 0 V is applied to the control gate, a tunnel current flows from the floating gate to the substrate, and electrons escape. As a result, the threshold voltage Vth of the memory cell shifts from positive to negative.

When performing a write operation, when writing data to the memory cell transistor MT3, 20 V is applied to the selected word line WL3, unselected word lines WL0 to WL2,
This is performed by applying an intermediate voltage of 10V to WL4 to WL7, applying 3V to the selection signal supply line DSG1, applying 0V to the selection signal supply line SSG1, and applying 0 to 3V to the bit line BL. As a result, a tunnel current flows through the memory cell transistor MT3, and electrons are injected into the floating gate. As a result, for example, the threshold voltage Vth of the memory cell is maintained as it is or shifts from negative to positive.

When performing a read operation, the bit line B
3V (Vb) is applied to L, 0V (Vs) is applied to the source line SRL, 0V (Vcg) is applied to the control gate of the selected memory transistor, the control gate of the unselected memory transistor, and the selection signal supply lines DSG1 and SSG1.
To 4.5V. When 0 V is applied to the control gate of the selected memory transistor, if the data is "1", the threshold voltage Vth is negative, so that the cell is turned on (depletion state) and the cell current I
read flows. On the other hand, if the data is "0", the threshold voltage Vth is positive, so that the cell is turned off (enhancement state) and the cell current Iread does not flow. As described above, whether data is "1" or "0" is determined by whether a cell current flows from a bit line to a source line through a plurality of cells.

As described above, in a semiconductor non-volatile memory device such as an EPROM or a flash memory, a binary type data recording two-valued data "0" and "1" in one memory cell transistor. The memory cell structure is usual. However, with the recent demand for large capacity nonvolatile semiconductor memory devices, a so-called multi-level nonvolatile semiconductor memory device that records at least three or more values of data in one memory cell transistor has been proposed. (For example, “A Multi-Level 32Mb Fla
sh Memory "'95 ISSCC p132 ~
reference).

FIG. 7 shows the relationship between the threshold voltage Vth level and the data contents (distribution) when two-bit data having four values are recorded in one memory transistor in a NAND flash memory. FIG.

In FIG. 7, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the threshold distribution frequency of the memory transistor. The contents of 2-bit data constituting data to be recorded in one memory transistor are represented by [D2, D1] and [D2, D1].
D1] = [1,1], [1,0], [0,1], [0,
0]. That is, there are four states: data “0”, data “1”, data “2”, and data “3”. In the case of four values, the threshold voltage distribution (multi-value data distribution) is three on the positive side and one on the negative side, as shown in FIG.

[0011]

However, as described above, in the read operation of the conventional NAND flash memory, the voltage generated by the cell current Iread flowing through the source line having the parasitic resistance R, etc.
Since the effect of apparently increasing the threshold voltage Vth of the cell is added as noise during data reading, there is a disadvantage that the reading accuracy is degraded.

Also, in the above-mentioned multi-level flash memory in which a plurality of data are stored in one cell, the accuracy of the so-called verify read operation at the time of the write operation is degraded due to noise due to the same cause. There are disadvantages, such as hindering the increase in capacity and a decrease in operation speed.

The present invention has been made in view of such circumstances, and a purpose of the present invention is to cause noise generated by flowing through a wiring or the like at the time of data reading, thereby apparently changing the threshold voltage of a read cell. It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device which can prevent the occurrence of an error and realize a highly accurate read operation.

[0014]

In order to achieve the above object, according to the present invention, the amount of electric charge accumulated in a charge accumulating portion changes according to a voltage applied to a connected word line and bit line, and the change is A memory string having at least one memory cell transistor whose threshold voltage changes in accordance with the following. One end of the memory string is connected to the bit line via the first selection transistor, and the other end of the memory string is connected to the other end of the memory string. A non-volatile semiconductor memory device connected to a source line via a second selection transistor and outputting data based on a word line voltage and an accumulated charge amount to a bit line at the time of a read operation. Of the selected memory cell transistor while applying a predetermined voltage to the source line while turning on the selected transistor. Having reading means for charging the voltage corresponding to the threshold voltage of the register.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage portion changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A memory string having at least one transistor, wherein one end of the memory string is connected to a bit line via a first selection transistor, and the other end of the memory string is connected to a source line via a second selection transistor The multi-value data of three or more values is recorded in one memory transistor according to the threshold voltage of the memory transistor, and at the time of reading, the word line voltage and the accumulated charge amount set according to the threshold voltage are stored. A non-volatile semiconductor memory device that outputs data based on a bit line, wherein the first and second selection transistors are operated during a read operation. Together to have a reading means for charging by applying a predetermined voltage to the source line, the bit line voltage corresponding to the threshold voltage of the memory cell transistors described above selected.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage section changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A memory string having at least one transistor, wherein one end of the memory string is connected to a bit line via a first selection transistor, and the other end of the memory string is connected to a source line via a second selection transistor A nonvolatile memory that records multi-valued data of three or more values in one memory transistor according to the threshold voltage of the memory transistor and outputs data based on the word line voltage and the accumulated charge amount to a bit line at the time of reading; A semiconductor memory device, wherein during a read operation, the first and second select transistors are turned on and the source line A predetermined voltage is applied, a voltage corresponding to the voltage applied to the source line is applied to the word line to which the selected memory cell transistor is connected, and the threshold voltage of the selected memory cell transistor is applied to the bit line. Reading means for charging to a voltage corresponding to.

In the present invention, the voltage applied to the source line is set based on a voltage applied to a selected word line and a threshold value according to data stored in a selected memory transistor. Have been.

Further, according to the present invention, there is provided a column circuit for determining read data from the charge level of the bit line, and a transfer gate for connecting the bit line to the column circuit after the potential of the charged bit line is determined. .

According to the present invention, for example, when data is read from a predetermined memory cell transistor, the first and second selection transistors of the selected string are kept conductive and a predetermined voltage is applied to the source line. Applied. Further, a predetermined word line voltage is applied to the gate of the selected memory cell transistor. This allows
The bit line is charged to a voltage according to the threshold voltage of the selected memory cell transistor. The data output from the bit line is input to the column circuit after the potential of the bit line is determined, for example, and the determination is performed.

[0020]

FIG. 1 is a system configuration diagram of a flash memory to which a nonvolatile semiconductor memory device according to the present invention is applied. This flash memory includes a memory array MA, a row circuit (Row Circuit) RC, and a column circuit (Colum Circuit).
n Circuit) CC and a well voltage control circuit WVC.

The memory cell array MA has n × m cells (not shown) connected by n word lines WL and m bit lines BL, and has word lines corresponding to NAND type memory strings. Each block has k blocks BLK1 to BLKk. Each word line WL and bit line BL are connected to a row circuit RC and a column circuit CC for controlling data writing / reading / erasing to a cell, and access to a cell at a desired address is controlled.

FIG. 2 is a diagram showing a memory cell array structure of a flash memory according to the present invention. FIG. 2 shows, for convenience, eight memory cell transistors MT10 to MT10 in one NAND string connected to one bit line BL.
17 shows a NAND-type flash memory array when connected.

In the memory string MSTR, for example, n-type memory cell transistors MT10 to MT17 capable of writing and erasing data by accumulating and releasing charges at a floating gate are connected in series, and the respective memory cell transistors MT10 to MT17 are connected. Are connected to the word lines WL10 to WL17, respectively. The drain of the memory cell transistor MT10 is connected to the bit line BL via a selection transistor DST10 composed of an NMOS transistor whose gate electrode is connected to a selection signal supply line DSG10. The source of the memory cell transistor MT17 has a gate electrode connected to the selection signal supply line DSG10. It is connected to the source line SRL via a selection transistor SST10 composed of an NMOS transistor connected to SSG10.

A precharge NMOS transistor NT11 is connected between the bit line BL and ground GND, and the bit line BL is connected to the column circuit CC via an NMOS transistor NT12 as a transfer gate. The gate of the NMOS transistor NT11 receives the signal PR.
C supply line, and the NMOS transistor NT
Twelve gates are connected to the signal CTL supply line.

Then, each memory cell transistor MT1
The threshold voltage Vth of 0 to MT17 is a value corresponding to the data written in the cell. For example, when 1-bit data is written in one cell, the threshold voltage Vth for data 1 is = -3V, and a threshold voltage Vth = 1V with respect to data 0.

The memory cell transistors MT10 to MT17 and the select transistors DST10 and SST10 of the memory string MSTR are formed in a p-well, and the p-well is connected to a well voltage control circuit WVC. The well voltage control circuit WVC outputs n
A high voltage of, for example, about 20 V is applied to the mold substrate and the p well, and 0 V is applied at the time of another read operation or the like.

The selection signal supply line DSG10 is connected to a supply line (not shown) for the drive voltage VDSG, and the selection signal supply line SSG10 is connected to a supply line (not shown) for the drive voltage VSSG. The selection signal supply line D
SG10 and SSG10 are, for example, a high withstand voltage N (not shown).
Drive voltages VDSG, VSS via MOS transistors
Connect to G supply line.

Next, the read operation of the above configuration will be described with reference to FIG. Here, a case where the read operation is performed on the memory cell transistor MT13 in FIG. 2 will be described as an example.

First, prior to the data read operation,
When the signal PRC is at a high level, the NMOS transistor NT1
1 gate. As a result, the NMOS transistor NT11 becomes conductive, and the bit line BL becomes 0V.
Is charged. Then, the signal PRC is switched to a low level, the NMOS transistor NT11 is switched to a non-conductive state, and the bit line BL is held in a floating state.

Next, select signal supply lines DSG10 and S
A voltage of 4.5 V is supplied to SG10 to select a string, a voltage VSL is applied to the source line SRL, and a voltage VCG (s) is applied to the gate of the selected memory cell transistor.
el), unselected memory cell transistors MT10 to MT
12, the gates of MT14 to MT17, that is, word lines WL10 to WL12 and WL14 to WL17 have data 0
In this case, the voltage VCG (unsel) (> Vth (0) + VS) is larger than the sum of the threshold voltage Vth (0) and the source line voltage VSL.
L) is applied. At this time, the bit line BL is charged with the gate voltage VCG (sel) of the selected memory cell transistor MT13 and the threshold voltage Vth (MT1
3: data) = VCG (sel) −Vth (MT13: data) or the source line voltage VSL.

For example, when associating the data with the threshold voltage Vth as described above, the source line voltage VSL is set to 3V,
3 is applied to the gate of the selected memory cell transistor MT13.
V, unselected memory cell transistors MT10 to MT1
2. If 4V is applied to the gates of MT14 to MT17, the bit line BL is charged to 3V (VSL) in the case of data 1, and the bit line BL is charged to 2V [V
CG (sel) -Vth (MT13: data)].

After the potential of the bit line BL is determined, the signal C
TL is supplied to the gate of the NMOS transistor NT12 at a high level. As a result, the bit line BL is electrically connected to the column circuit CC including the sense circuit and the decode circuit. As a result, the threshold voltage Vth of the selected memory cell transistor MT13, that is, the voltage of the bit line BL corresponding to the data written in the memory cell transistor MT13 is detected by the column circuit CC, and decoding of the written data is performed. Done.

At this time, if the first stage of the input circuit of the column circuit CC is set to have a high input impedance, noise caused by a current flowing through the string and the wiring at the time of reading data may cause an apparent threshold voltage of the selected memory cell transistor MT13. Vth can be prevented from being changed, and a highly accurate read operation can be performed.

The same read operation can be applied to a verify read operation in a bit-by-bit verify operation at the time of a write operation, and high-accuracy write control can be realized as compared with the case where a conventional read operation is used. It becomes possible.

As described above, according to the present embodiment, NA
In the ND type flash EEPROM, during the read operation, the bit line BL is charged to 0 V, and then left in a floating state to select a string.
The voltage VSL is applied to the source line SRL, and the unselected memory cell transistors MT10 to MT12, MT14 to MT1
7 has a threshold voltage Vth (0) for data 0
Voltage VCG (uns
el) (> Vth (0) + VSL) to apply the bit line BL
The difference between the gate voltage VCG (sel) of the selected memory cell transistor MT13 and the threshold voltage Vth (MT13: data) of the memory cell transistor MT13 = VCG (sel) −Vth ( MT13:
data) or the source line voltage VSL, and data is detected from the potential of the bit line BL. Therefore, noise caused by flowing through the wiring or the like at the time of reading data is apparently the threshold value of the read cell. There is an advantage that the voltage can be prevented from being changed, and a highly accurate read operation can be realized.

In the above description, a memory cell transistor for storing binary data has been described as an example. However, a so-called multi-valued type in which at least three or more values of data are recorded in one memory cell transistor. Needless to say, the present invention can be applied to a nonvolatile semiconductor memory device. In this case, in addition to the feature of high accuracy, a high-speed read operation can be performed by the two methods described below.

For example, when writing 2-bit data to one cell, threshold voltage Vth = −3 V for data 11, Vth = 0.5 V for data 10,
It is assumed that Vth = 1.5 V for data 01 and Vth = 2.5 V for data 00.

First, the first reading method will be described with reference to FIG. In this case, the source line voltage VSL is set to 3
V, unselected memory cell transistors MT10 to MT1
2. The gate of MT14 to MT17 has VCG (unsel) =
5.5 V is applied to the selected memory cell transistor MT1.
In each of the first to third read operations, VCG (sel, 1st) = 0 V and VCG (sel, 2nd) =
1V, VCG (sel, 3rd) = 2V is applied.

In the first read operation, when the data written in the cell is data 11, the bit line BL is set to 3
It is charged to V (VSL) and remains at 0 V in the case of data 10, 01, 00. Therefore, when the data 11 is read, it is determined that both the upper bit and the lower bit of the data are 1, and the read data after the second read operation can be ignored. In the first read operation, when data 11 is not read, in the next read operation, when the data written in the cell is 10, the bit line BL is charged to 0.5 V, and when the data is 01, 00, Remains at 0V. Therefore, it is determined that the upper bit of the data is 1.
Similarly, by the third read operation, it is possible to determine 1 or the upper bit of the data.

As described above, data of a plurality of bits written in one cell can be read.

Next, the second reading method will be described with reference to FIG. In this case, the source line voltage VSL is set to 3
V, 3 V is applied to the gate of the selected memory cell transistor MT13, and unselected memory cell transistors MT10 to MT
12, VCG (unsel) = is applied to the gates of MT14 to MT17.
Apply 5.5V. As a result, the bit line BL is charged to 3 V (VSL) in the case of data 11, the bit line BL is 2.5 V in the case of data 10, the bit line BL is 1.5 V in the case of data 01, and the data 00 is in the case of data 00. Bit line B
L is charged to 0.5V.

When the threshold voltage of the selected memory cell transistor MT13 and the bit line BL voltage corresponding to the data written in the selected memory cell transistor MT13 are detected by the column circuit CC in accordance with the string, the detection of the written data is performed. It can be carried out. The column circuit CC has a function of decoding a voltage value appearing on the bit line BL into a 2-bit data series. With these operations, it is possible to read a plurality of bits of data by a single read operation. As a result, a higher-speed operation can be performed as compared with the method of reading data by performing a plurality of read operations as described above.

In the above-described embodiment, a NAND type string has been described as an example. However, the present invention uses another flash EEPROM, such as a D / E, for exchanging data between a bit line BL and a memory string via a selection transistor.
Needless to say, the present invention can be applied to a flash EEPROM of an INOR type, an AND type, and the like.

[0044]

As described above, according to the present invention,
Noise caused by current flowing through the string and the wiring at the time of data reading can be prevented from apparently changing the threshold voltage of the reading cell, and a highly accurate reading operation can be performed.

Further, a plurality of data written in the same cell can be read out to the column circuit by one read operation, and a higher speed can be obtained as compared with a method of performing a plurality of read operations and reading data of the cell. Operation becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a flash memory according to the present invention.

FIG. 2 is a diagram showing a memory cell array structure of a NAND flash memory according to the present invention.

FIG. 3 is a diagram for explaining a read operation of the NAND flash memory according to the present invention.

FIG. 4 is a diagram for explaining a reading method in a flash memory employing a multi-level writing method according to the present invention.

FIG. 5 is a diagram for explaining another reading method in the flash memory adopting the multi-level writing method according to the present invention.

FIG. 6 is a diagram showing a memory array structure of a NAND flash memory.

FIG. 7 is a diagram showing the relationship between the threshold voltage Vth level and the distribution of data when data of two bits and having four values is recorded in one memory transistor in a NAND flash memory.

[Explanation of symbols]

MT10 to MT17: memory cell transistor, DST
10, SST: selection transistor, WL10 to WL17
... word line, BL ... bit line, DSG10, SSG10
... Selection signal supply line, RC ... Row circuit, CC ... Column circuit, WVC ... Well voltage control circuit, NT11, NT12
... NMOS transistor.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (13)

[Claims] An at least one memory cell transistor in which the amount of charge stored in a charge storage unit changes according to a voltage applied to a connected word line and bit line, and a threshold voltage changes according to the change. One memory string, one end of the memory string is connected to a bit line via a first selection transistor, and the other end of the memory string is connected to a source line via a second selection transistor. A non-volatile semiconductor memory device that outputs data based on a word line voltage and a stored charge amount to a bit line, wherein during a read operation, the first and second selection transistors are turned on and a predetermined voltage is applied to the source line. To charge the bit line to a voltage corresponding to the threshold voltage of the selected memory cell transistor. Nonvolatile semiconductor memory device having means out. 2. The voltage applied to the source line is set based on a voltage applied to a selected word line and a threshold value according to data stored in a selected memory transistor. 2. The nonvolatile semiconductor memory device according to claim 1, comprising: 3. A column circuit for determining read data from a charge level of the bit line, and a transfer gate for connecting the bit line to the column circuit after the potential of the charged bit line is determined. Nonvolatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the first stage of the input circuit of the column circuit is held at a high input impedance. 5. The non-volatile semiconductor memory device according to claim 1, wherein said read means has means for charging said bit line to a reference potential before starting to read, and thereafter holding said bit line in an electrically floating state. 6. The non-volatile semiconductor memory device according to claim 3, wherein said read means has means for charging said bit line to a reference potential before starting to read and then holding said bit line in an electrically floating state. 7. The nonvolatile semiconductor memory device according to claim 1, wherein said memory string has a NAND structure. 8. A memory transistor in which the amount of charge stored in the charge storage unit changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. One end of the memory string is connected to a bit line via a first select transistor, and the other end of the memory string is connected to a source line via a second select transistor. The multi-valued data of three or more values is recorded in one memory transistor according to the threshold voltage of the memory cell, and at the time of reading, the data based on the word line voltage and the accumulated charge amount set according to the threshold voltage is bit-wise. A non-volatile semiconductor memory device that outputs data to a first line and a second line when a read operation is performed. , By applying a predetermined voltage to the source line, the nonvolatile semiconductor memory device having a readout means for charging said bit line to a voltage corresponding to the threshold voltage of the memory cell transistors described above selected. 9. A voltage applied to the source line is set based on a voltage applied to a selected word line and a threshold value according to data stored in a selected memory transistor. 9. The nonvolatile semiconductor memory device according to claim 8, comprising: 10. A column circuit for judging read data from the charge level of the bit line, and a transfer gate for connecting the bit line to the column circuit after determining the potential of the charged bit line. Nonvolatile semiconductor memory device. 11. A memory transistor in which an amount of charge stored in a charge storage unit changes according to a voltage applied to a connected word line and bit line, and a threshold voltage changes according to the change. One end of the memory string is connected to a bit line via a first select transistor, and the other end of the memory string is connected to a source line via a second select transistor. Is a non-volatile semiconductor memory device that records multi-valued data of three or more values in one memory transistor in accordance with the threshold voltage of data and outputs data based on the word line voltage and the accumulated charge amount to the bit line at the time of reading. During a read operation, the first and second selection transistors are turned on, and a predetermined voltage is applied to the source line. In addition, a voltage corresponding to the voltage applied to the source line is applied to the word line to which the selected memory cell transistor is connected, and the bit line is set according to the threshold voltage of the selected memory cell transistor. A nonvolatile semiconductor memory device having a reading means for charging to a voltage. 12. The voltage applied to the source line is set based on a voltage applied to a selected word line and a threshold value according to data stored in a selected memory transistor. The nonvolatile semiconductor memory device according to claim 11, comprising: 13. A column circuit for determining read data from the charge level of the bit line, and a transfer gate for connecting the bit line to the column circuit after determining the potential of the charged bit line. Nonvolatile semiconductor memory device.