JPH1186571A - Nonvolatile semiconductor storage device and its data writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve writing inhibiting operation controllability and characteristic into a memory cell by providing a memory cell transistor wherein a stored electric charge quantity in an electric charge storage part is varied in accordance with an applied voltage to connected word lines and bit lines and a threshold voltage is varied in accordance with it. SOLUTION: (n) type memory cell transistors MT10-MT17 capable of writing and erasing data by the storage and discharge of electric charges in a floating gate are connected in series with a memory string MSTR, and its control gate CG is connected to word lines WL10-WL17. A drain of the memory cell transistor MT10 is connected to the bit line via a selection transistor DST10 wherein a gate electrode is connected to a selection signal feeding line DSG10. The selection transistor DST10 is composed of a stack gate type transistor whose threshold Vths10 is variable, and the threshold Vths10 is varied to the value of e.g. nearly 0-1 V. Whereby, the applying voltage to the selection signal feeding line DSG10 is controlled so as to take a required threshold in accordance with operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically rewritable nonvolatile memory, for example, a flash EEPROM.
M (Electrically Erasable Programmable Read Only Me
mory) and a data writing method thereof.

[0002]

2. Description of the Related Art FIG. 8 shows a NAND flash EEPROM.
FIG. 3 is a diagram illustrating a memory array structure of an OM. NAN of FIG. 8
The D-type flash EEPROM shows a memory array in which eight memory cell transistors MT0 to MT7 are connected to one NAND string connected to one bit line BL for convenience. FIG. 8A shows a write bias for a selected string at the time of writing, and FIG. 8B shows a write bias for an unselected string at the time of writing.

In a memory string, the control gate CG of each of the memory cell transistors MT0 to MT7 is
Are connected to word lines WL0 to WL7, respectively.
The drain of the memory cell transistor MT0 is connected to the bit line BL via a selection transistor DST1 composed of an NMOS transistor whose gate electrode is connected to the selection signal supply line DSG1, and the source of the memory cell transistor MT7 has a gate electrode connected to the selection signal supply line DSG1. Select transistor S composed of NMOS transistor connected to SSG1
It is connected to the source line SRL via ST1.

Incidentally, a NAND flash EEPROM is used.
In general, a first p-well for a cell array region and a second p-well for a peripheral circuit region are formed in an n-type semiconductor substrate, and a gate insulating film, a floating gate, A memory cell is formed by laminating an interlayer insulating film and a control gate. An NMOS transistor of a peripheral circuit is formed in a second p-well, and an n-well for a PMOS transistor is formed in the second p-well. You.

In the NAND flash EEPROM having such a structure, when performing an erasing operation,
When a high voltage of, for example, about 20 V is applied to the n-type substrate and the p well and 0 V is applied to the control gate, a tunnel current flows from the floating gate to the substrate, and electrons escape. As a result, the threshold voltage Vth of the memory cell shifts from positive to negative.

When a write operation is performed, for example, FIG.
As shown in (a), when writing data to the memory cell transistor MT3, 20 bits are applied to the selected word line WL3.
V, unselected word lines WL0-WL2, WL4-WL7
By applying an intermediate voltage of 10 V, 3 V to the selection signal supply line DSG1, 0 V to the selection signal supply line SSG1, and 0 to 3 V to the bit line BL. As a result, a tunnel current flows through the memory cell transistor MT3, and electrons are injected into the floating gate. As a result, for example, the threshold voltage Vth of the memory cell is maintained as it is or shifts from negative to positive.

When performing a read operation, the bit line B
Apply 3 V to L and 0 V to the source line SRL, and apply 0 V to the control gate of the selected memory transistor and 5 V to the control gate of the unselected memory transistor. Unselected memory transistors need to be on regardless of data. Therefore, the threshold voltage Vth of the memory cell is controlled to a predetermined voltage, for example, 3.5 V or less. When 0 V is applied to the control gate of the selected memory transistor, if the data is "1", the threshold voltage Vth is negative, so that the cell is turned on (depletion state) and a cell current flows. On the other hand, if the data is "0", the threshold voltage Vth is positive, so that the cell is turned off (enhancement state) and no cell current flows. As described above, whether data is "1" or "0" is determined by whether a cell current flows from a bit line to a source line through a plurality of cells.

As described above, in a semiconductor non-volatile memory device such as an EPROM or a flash memory, a binary type data recording two-valued data "0" and "1" in one memory cell transistor. The memory cell structure is usual. However, with the recent demand for large capacity nonvolatile semiconductor memory devices, a so-called multi-level nonvolatile semiconductor memory device that records at least three or more values of data in one memory cell transistor has been proposed. (For example, “A Multi-Level 32Mb Fla
sh Memory "'95 ISSCC p132 ~
reference).

FIG. 9 shows the relationship between the threshold voltage Vth level and the data content (distribution) when two-bit quaternary data is recorded in one memory transistor in a NAND flash memory. FIG.

In FIG. 9, the vertical axis represents the threshold voltage Vth of the memory transistor, and the horizontal axis represents the threshold distribution frequency of the memory transistor. The contents of 2-bit data constituting data to be recorded in one memory transistor are represented by [D2, D1] and [D2, D1].
D1] = [1,1], [1,0], [0,1], [0,
0]. That is, there are four states: data “0”, data “1”, data “2”, and data “3”. When the threshold voltage distribution (multi-value data distribution) is quaternary, as shown in FIG. 9, three distributions are provided on the positive side and one distribution is provided on the negative side.

For example, as shown in FIG. 10, when writing data to memory cell transistor MT3, 20 V is applied to selected word line WL3 and unselected word lines WL0 to WL
2. Apply an intermediate voltage of 10 V to WL4 to WL7, 3 V to the selection signal supply line DSG1, and 0 to the selection signal supply line SSG1.
When V is applied and data “00” is written, 0 V is applied to the bit line BL. When writing data “01”, 0.7 V is applied to the bit line BL, and data “0” is applied.
To write “2”, apply 1.4 V and set the data “1”.
When writing "1", 3 V is applied to the bit line BL.

[0012]

As described above, in the conventional NAND flash memory, a write operation to a memory cell is performed by applying a voltage of about 0 to 3 V to the bit line BL and applying a voltage to the select transistor DST1 of the selected string. This is performed by applying a voltage Vsg of about 3 V to the gate electrode. Here, the voltage applied to the bit line BL controls the channel voltage of the memory cell transistor via the selection transistor DST1, and together with the voltage applied to the word line, an important value as means for controlling data writing to the memory cell. Become.

However, even when a voltage of 0 to 3 V is applied to the bit line BL, it is limited by the gate voltage Vsg of the selection transistor DST1 of the selected string and its threshold voltage Vthsg, When the maximum voltage is higher than (Vsg-Vthsg), the range that can be controlled as the channel voltage of the memory cell is 0 to (Vsg-Vthsg).
sg) Limited to V. Thus, it is desired to lower the threshold voltage Vthsg in order to limit the controllability and characteristics of the write-inhibit operation to the memory cell.

In a flash memory employing a multi-level write method, the channel voltage of a memory cell corresponding to write data must be set at a sufficient voltage interval in order to prevent erroneous writing. Therefore, it is desired to lower the threshold voltage Vthsg so as to widen the control range of the channel voltage.

On the other hand, a voltage Vsg of 0 V is applied to the gate electrode of the selection transistor of the string in the non-selected state by the above-described write operation or the like, and the voltage of ~ 3 V applied to the bit line BL causes the non-selected string to pass through the unselected string. It is necessary to prevent the leaked current from flowing. That is, in order to prevent a leak current of an unselected string, it is desired to increase the threshold voltage Vthsg of the selection transistor.

As described above, in setting the threshold voltage of the select transistor in the string, it is necessary to satisfy conflicting conditions for satisfying some characteristics.
There is a disadvantage that only low characteristics can be realized as a whole.

The present invention has been made in view of such circumstances, and has as its object to improve the controllability and characteristics of a write-inhibit operation to a memory cell and to widen a set interval of a channel voltage. An object of the present invention is to provide a nonvolatile semiconductor memory device and a data writing method thereof.

[0018]

In order to achieve the above object, according to the present invention, the amount of electric charge accumulated in a charge accumulating portion changes according to a voltage applied to a connected word line and bit line, and the change is A non-volatile semiconductor memory device having a memory cell transistor whose threshold voltage changes according to the potential of the bit line, and writing data according to the potential of the bit line. And a selection transistor whose threshold voltage is variable according to the input level of the selection signal to the gate electrode.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage portion changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A non-volatile semiconductor memory device having a cell transistor and writing data according to the potential of the bit line after performing an erasing operation, comprising a gate connected between the memory cell transistor and the bit line, If the threshold voltage of the selection transistor is variable according to the input level of the selection signal to the electrode, and the threshold voltage of the selection transistor is set low during the erase operation before writing, and the writing is completed, Means for setting the threshold voltage of the selection transistor higher than the threshold voltage set at the time of writing.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage section changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. What is claimed is: 1. A nonvolatile semiconductor memory device having a NAND structure, comprising: a transistor; and, at the time of reading, outputting a word line voltage set according to a threshold voltage and data based on an accumulated charge amount to a bit line. And a selection transistor connected between the bit line and the bit line, the threshold voltage of which is variable according to the input level of the selection signal to the gate electrode.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage portion changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A multi-level data having three or more values recorded in one memory transistor according to the threshold voltage of the memory transistor, and a word line voltage set according to the threshold voltage at the time of reading. What is claimed is: 1. A non-volatile semiconductor memory device having a NAND structure for outputting data based on an accumulated charge amount to a bit line, wherein the nonvolatile semiconductor memory device is connected between the memory cell transistor and the bit line, and responds to an input level of a selection signal to a gate electrode. And a selection transistor having a variable threshold voltage.

Further, in the present invention, there is provided a means for setting the threshold voltage of the selection transistor low when performing a write operation. Further, the present invention has means for setting the threshold voltage of the selection transistor to be higher than the threshold voltage set at the time of writing after the end of the writing operation.

In the present invention, the selection transistor is constituted by a transistor having a structure equivalent to that of the memory cell transistor.

Further, according to the present invention, there is provided a memory in which the amount of charge stored in a charge storage section changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A data writing method for a nonvolatile semiconductor memory device having a cell transistor and performing data writing according to a potential of the bit line via a selection transistor having a variable threshold voltage after performing an erasing operation. At the time of the pre-erase operation, the threshold voltage of the selection transistor is set low, data is written in a state where the threshold voltage of the selection transistor is low. Is set higher than the set threshold voltage.

According to the present invention, for example, when writing to a predetermined memory cell transistor, the threshold voltage of the selection transistor to which the memory cell transistor is connected is set low. Then, data is written while the threshold voltage of the selection transistor is low. When the writing is completed, the threshold voltage of the selection transistor is set higher than the threshold voltage set at the time of writing. That is, the threshold voltage is returned to the value before the start of the write operation (the erase operation before write). Note that the threshold voltage of the selection transistor to which the unselected memory cell transistor is connected is kept at a high value, thereby preventing generation of a leak current.

[0026]

FIG. 1 is a system configuration diagram of a flash memory to which a nonvolatile semiconductor memory device according to the present invention is applied. This flash memory includes a memory array MA, a row circuit (Row Circuit) RC, and a column circuit (Colum Circuit).
n Circuit) CC and a well voltage control circuit WVC.

The memory cell array MA has n × m cells (not shown) connected by n word lines WL and m bit lines BL, and has word lines corresponding to NAND type memory strings. Each block has k blocks BLK1 to BLKk. Each word line WL and bit line BL are connected to a row circuit RC and a column circuit CC for controlling data writing / reading / erasing to a cell, and access to a cell at a desired address is controlled.

FIG. 2 is a diagram showing a memory cell array structure of a flash memory according to the present invention. FIG. 2 shows, for convenience, eight memory cell transistors MT10 to MT10 in one NAND string connected to one bit line BL.
17 shows a NAND-type flash memory array when connected.

In the memory string MSTR, for example, n-type memory cell transistors MT10 to MT17 capable of writing and erasing data by accumulating and releasing charges at a floating gate are connected in series, and the respective memory cell transistors MT10 to MT17 are connected. Are connected to the word lines WL10 to WL17, respectively. The drain of the memory cell transistor MT10 is connected to a bit line B via a selection transistor DST10 whose gate electrode is connected to a selection signal supply line DSG10.
L, and the source of the memory cell transistor MT17 is a selection transistor SS composed of an NMOS transistor whose gate electrode is connected to the selection signal supply line SSG10.
It is connected to the source line SRL via T10.

The selection transistor DST10 in the memory string MSTR according to the present embodiment is constituted by a transistor having a variable threshold value Vths10, for example, a stack gate type transistor similar to a memory cell transistor. Select transistor DST1
The threshold voltage ths10 of 0 can be varied to a value of, for example, about 0 V to 1 V. As will be described later, the selection signal supply is performed so as to take a necessary threshold value according to an operation (particularly, a write operation). The voltage applied to the line DSG10 is controlled.

The memory cell transistors MT10 to MT17 and the select transistors DST10 and SST10 of the memory string MSTR are formed in a p-well, and the p-well is connected to a well voltage control circuit WVC. The selection signal supply line DSG10 is connected to a supply line (not shown) for the drive voltage VDSG, and the selection signal supply line SSG10 is connected to a supply line (not shown) for the drive voltage VSSG. The selection signal supply line D
SG10 and SSG10 are, for example, a high withstand voltage N (not shown).
Drive voltages VDSG, VSS via MOS transistors
Connect to G supply line.

Next, a write operation with an erase operation according to the above configuration will be described with reference to FIGS. 3, 4, 5 and 6. FIG. Here, a case where the write operation is performed on the memory cell transistor MT13 in FIG. 2 will be described as an example. FIG. 3 is a flowchart for explaining a write operation, FIG. 4 is a diagram showing bias conditions of a selected string and an unselected string during an erase operation before writing, and FIG. FIG. 6 is a diagram illustrating a bias condition, and FIG. 6 is a diagram illustrating a bias condition of a selected string and a non-selected string when the threshold voltage of a selection transistor is increased after a write operation.

First, prior to the data write operation,
Erase operation for the selected block to be written and threshold voltage Vths1 of the select transistor in the selected string
The threshold voltage of 0 is lowered (S1, S2). Specifically, the n-type substrate and the p-type substrate are controlled by the well voltage control circuit WVC.
A high voltage of, for example, about 20 V is applied to the well. Then, as shown in FIG. 4A, the memory cell transistor MT10 of the string selected by the row circuit RC
0V is applied to the word lines WL10 to WL17 to which the control gates of the control transistor DST10 to WL17 are connected, the selection signal supply line DSG10 to which the gate electrode (corresponding to the control gate) of the selection transistor DST10 is connected, and the source line SRL side. Selection transistor SST10
20V is applied to the selection signal supply line SSG10 to which the gate electrode is connected. At this time, the bit line BL and the source line SRL are held in a floating state by the column circuit CC and the like. As a result, a tunnel current flows from the floating gates of the memory cell transistors MT10 to WL17 to the substrate, and electrons escape. That is, data is erased, and the threshold voltage Vth of the memory cell shifts from positive to negative. At this time, the threshold voltage Vths10 of the select transistor DST10 on the bit line BL side becomes 1
Transition from V to 0V. That is, the threshold voltage is lowered.

In the erase operation, as shown in FIG. 4B, for the unselected strings, the word lines WL10 to WL17 to which the control gates of the memory cell transistors MT10 to WL17 are connected, and the select transistor DST10 , SST10 are connected to the selection signal supply lines DSG10, SSG10 to which 20V is applied. As a result, erasure of data in the unselected string is suppressed, and the threshold voltage Vths10 of the selection transistor DST10 on the bit line BL side is maintained at 1V. That is, lowering of the threshold voltage is suppressed.

When the above erasing operation is completed, a writing operation is performed (S3, S4). More specifically, for example, as shown in FIG.
3 when writing data to the selected word line WL13
20V, unselected word lines WL10 to WL12, WL1
4 to WL17, an intermediate voltage of 10V is applied, a selection signal supply line DSG1 is applied with 3V, a selection signal supply line SSG1 is applied with 0V, and a bit line BL is supplied with 0V according to write data.
Alternatively, 3 V is applied. At this time, the source line SRL is held at the ground level (0 V), and the well voltage control circuit 2
With 0, 0V is applied to the p-well 12, and the substrate is also maintained at 0V. As a result, desired data is written to the memory cell transistor MT13, and the other memory cell transistors MT10 to MT12 and MT14 to MT1 are written.
No writing to 7 is performed. As a result, for example, the threshold voltage Vth of the memory cell is maintained as it is or shifts from negative to positive.

In the write operation, as shown in FIG. 5B, for the unselected strings, the word lines WL0 to WL7 to which the control gates of the memory cell transistors MT10 to WL17 are connected, and the select transistor DST10 , SST10 are connected to the selection signal supply lines DSG10, SSG10 to which 0V is applied. Then, the bit line BL is supplied by the column circuit CC or the like.
And 0V is applied to the source line SRL. Therefore, since the threshold voltage Vths10 of the select transistor DST10 on the bit line BL side is kept at 1 V, the occurrence of a leak current through the unselected string is prevented. On the other hand, the channel voltage of the selected string is such that the threshold voltage Vths10 of the selection transistor DST10 is 0V.
Therefore, control can be performed in the range of 0 to 3 V, and controllability and characteristics of the write-inhibiting operation for the memory cell can be improved.

When the write operation is completed, the threshold voltage Vths10 of the select transistor DST10 on the bit line BL side of the selected string, which has been lowered in threshold voltage, is set to 0.
The threshold voltage is raised from V to 1 V (S
5). Specifically, as shown in FIG. 6A, 0 V is applied to the word lines WL0 to WL7, and the select signal supply line DSG10 to which the gate electrode (corresponding to a control gate) of the select transistor DST10 is connected. 20
V, 0 is applied to the selection signal supply line SSG10 connected to the gate electrode of the selection transistor SST10 on the source line SRL side.
V is applied. At this time, the bit line BL and the source line SRL are held at 0 V by the column circuit CC and the like.
Thereby, the select transistor DST on the bit line BL side
The threshold voltage Vths10 of 10 changes from 0V to 1V.

At this time, for an unselected string,
As shown in FIG. 6B, the memory cell transistor MT
Word lines WL0 to WL7 to which control gates of 10 to WL17 are connected, and select transistors DST10 and S
Select signal supply line DS to which gate electrode of ST10 is connected
0 V is applied to G10 and SSG10. Further, 0 V is applied to the bit line BL and the source line SRL by the column circuit CC or the like.

Then, by returning the threshold voltage Vths10 of the select transistor DST10 on the bit line BL side from 0V to 1V, the write operation is completed (S6).

As described above, according to the present embodiment, the NA
In an ND type flash EEPROM, a selection transistor DST10 for connecting each string to a bit line BL
Is constituted by a transistor whose threshold value is variable, and the threshold value of the selection transistor of the string to be written is lowered (change from 1 V to 0 V) at the time of writing,
The threshold voltage of the select transistor DST10 of the string in the unselected block remains high (1
V), and after the writing is completed, the threshold value of the selection transistor of the selected string whose threshold voltage has been lowered is returned to the high threshold voltage (1 V). The generation of current can be prevented, and the channel voltage of the selected string can be controlled in the range of 0 to 3 V because the threshold voltage Vths10 of the selection transistor DST10 is 0 V. There is an advantage that controllability and characteristics of the prohibited operation can be improved.

In the above description, a memory cell transistor that stores binary data has been described as an example. However, a so-called multi-valued type in which at least three or more values of data are recorded in one memory cell transistor. Needless to say, the present invention can be applied to a nonvolatile semiconductor memory device.

For example, as shown in FIG. 7, when data is written to memory cell transistor MT13, 20 V is applied to selected word line WL13 and unselected word lines WL10 to WL10.
An intermediate voltage of 10 V is applied to WL12 and WL14 to WL17, and a threshold voltage of 3V is applied to the selection signal supply line DSG1 connected to the gate electrode of the selection transistor DST10 whose 1V is reduced to 0V, and the selection signal supply line SSG1 0V is applied to the bit line BL when writing data "00". When writing data "01", 1 V (conventionally 0.7 V) is applied to the bit line BL, and when writing data "02", 2 V (conventionally 1.4 V) is applied and data "11" is applied. Is written, 3 V is applied to the bit line BL.

As described above, the selection transistor DST10
Memory using a multi-level programming method with transistors with variable threshold values, the memory cell channel voltage can be set at sufficient voltage intervals according to the programming data, preventing erroneous programming. There are advantages that can be done.

In the above-described embodiment, a NAND type string has been described as an example. However, the present invention uses another flash EEPROM, such as a D-type flash memory, for exchanging data between a bit line BL and a memory string via a selection transistor.
Needless to say, the present invention can be applied to a flash EEPROM of an INOR type, an AND type, and the like.

[0045]

As described above, according to the present invention,
It is possible to prevent the occurrence of a leak current through the non-selected string, and the channel voltage of the selected string can be controlled in a wide range because the threshold voltage of the selection transistor is controlled to a low voltage. There is an advantage that controllability and characteristics of the write prohibition operation to the memory can be improved.

Further, in a flash memory employing a multi-level write method, the channel voltage of a memory cell corresponding to write data can be set at a sufficient voltage interval, and there is an advantage that erroneous writing can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a flash memory according to the present invention.

FIG. 2 is a diagram showing a memory cell array structure of a NAND flash memory according to the present invention.

FIG. 3 is a flowchart for explaining a write operation of the NAND flash memory according to the present invention.

FIG. 4 is a diagram showing bias conditions of a selected string and an unselected string during an erase operation before writing in a NAND flash memory according to the present invention.

FIG. 5 is a diagram showing bias conditions of a selected string and a non-selected string at the time of writing in the NAND flash memory according to the present invention.

FIG. 6 is a diagram showing bias conditions of a selected string and a non-selected string when the threshold voltage of a selection transistor is increased after a write operation in a NAND flash memory according to the present invention.

FIG. 7 is a diagram for explaining a write operation in a flash memory employing a multi-level write method according to the present invention.

FIG. 8 is a diagram showing a memory array structure of a NAND flash EEPROM.

FIG. 9 is a diagram showing the relationship between the threshold voltage Vth level and the distribution of data in the case where 2-bit data having four values is recorded in one memory transistor in the NAND flash memory according to the present invention. It is.

FIG. 10 is a diagram for explaining a write operation in a flash memory employing a conventional multi-level write method.

[Explanation of Signs] MT10 to MT17: Memory cell transistor, DST
10, SST10 ... selection transistor, WL0 to WL7
... word line, BL ... bit line, DSG10, SSG10
... selection signal supply line, RC ... row circuit, CC ... column circuit, WVC ... well voltage control circuit.

Claims (21)

[Claims] 1. A memory cell transistor in which the amount of charge stored in a charge storage unit changes according to the voltage applied to a connected word line and bit line, and the threshold voltage changes according to the change. A nonvolatile semiconductor memory device for writing data in accordance with the potential of the bit line, wherein the nonvolatile semiconductor memory device is connected between the memory cell transistor and the bit line, and responds to an input level of a selection signal to a gate electrode. Semiconductor memory device having a select transistor whose threshold voltage is variable. 2. The non-volatile semiconductor memory device according to claim 1, further comprising means for setting a threshold voltage of said select transistor low when performing a write operation. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising means for setting a threshold voltage of said select transistor to be higher than a set threshold voltage at the time of writing after a write operation is completed. 4. The non-volatile semiconductor memory device according to claim 2, further comprising means for setting a threshold voltage of said select transistor higher than a threshold voltage set at the time of said writing after completion of said writing operation. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said select transistor is constituted by a transistor having a structure equivalent to said memory cell transistor. 6. The nonvolatile semiconductor memory device according to claim 2, wherein said select transistor is constituted by a transistor having a structure equivalent to said memory cell transistor. 7. A memory cell transistor in which the amount of charge stored in a charge storage portion changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A non-volatile semiconductor memory device that performs data writing according to the potential of the bit line after performing an erasing operation, wherein the non-volatile semiconductor memory device is connected between the memory cell transistor and the bit line to select a gate electrode. A selection transistor whose threshold voltage is variable in accordance with a signal input level; and during the pre-erase operation, writing is performed by setting the threshold voltage of the selection transistor to a low value. Means for setting the threshold voltage of the memory cell higher than the set threshold voltage at the time of writing. 8. The nonvolatile semiconductor memory device according to claim 7, wherein said select transistor is constituted by a transistor having a structure equivalent to that of said memory cell transistor. 9. A memory transistor in which the amount of charge stored in the charge storage unit changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A nonvolatile semiconductor memory device having a NAND structure that outputs data based on a word line voltage and an accumulated charge amount set according to a threshold voltage to a bit line during reading, wherein the memory cell transistor and the bit line And a selection transistor connected between the gate electrode and a selection transistor whose threshold voltage is variable according to the input level of the selection signal to the gate electrode. 10. The nonvolatile semiconductor memory device according to claim 9, further comprising: means for setting a threshold voltage of said select transistor low when performing a write operation. 11. The nonvolatile semiconductor memory device according to claim 9, further comprising means for setting a threshold voltage of said select transistor to be higher than a threshold voltage set at the time of writing after a write operation is completed. 12. The nonvolatile semiconductor memory device according to claim 10, further comprising means for setting a threshold voltage of said select transistor to be higher than a set threshold voltage at the time of said write after said write operation is completed. 13. The nonvolatile semiconductor memory device according to claim 9, wherein said selection transistor is constituted by a transistor having a structure equivalent to said memory cell transistor. 14. The nonvolatile semiconductor memory device according to claim 10, wherein said select transistor is constituted by a transistor having a structure equivalent to said memory cell transistor. 15. A memory transistor in which the amount of charge stored in a charge storage unit changes according to a voltage applied to a connected word line and bit line, and a threshold voltage changes according to the change. The multi-value data of three or more values is recorded in one memory transistor according to the threshold voltage of the memory transistor, and at the time of reading, the word line voltage and the accumulated charge amount set according to the threshold voltage are stored. A non-volatile semiconductor memory device having a NAND structure for outputting data based on a bit line, wherein the threshold value is connected between the memory cell transistor and the bit line, and the threshold value is determined according to an input level of a selection signal to a gate electrode. A nonvolatile semiconductor memory device having a selection transistor whose voltage is variable. 16. The non-volatile semiconductor memory device according to claim 15, further comprising means for setting a threshold voltage of said select transistor low when performing a write operation. 17. The non-volatile semiconductor memory device according to claim 15, further comprising means for setting a threshold voltage of said select transistor higher than a set threshold voltage at the time of writing after completion of the writing operation. 18. The nonvolatile semiconductor memory device according to claim 16, further comprising means for setting a threshold voltage of said select transistor to be higher than a threshold voltage set at the time of said writing after completion of said writing operation. 19. The nonvolatile semiconductor memory device according to claim 15, wherein said select transistor is constituted by a transistor having a structure equivalent to that of said memory cell transistor. 20. The nonvolatile semiconductor memory device according to claim 16, wherein said select transistor is constituted by a transistor having a structure equivalent to said memory cell transistor. 21. A memory cell transistor in which the amount of charge stored in a charge storage unit changes according to the voltage applied to the connected word line and bit line, and the threshold voltage changes according to the change. A data writing method for a nonvolatile semiconductor memory device, in which data writing according to the potential of the bit line is performed via a selection transistor whose threshold voltage is variable after performing an erasing operation, The threshold voltage of the selection transistor is set low, data is written in a state where the threshold voltage of the selection transistor is low, and after the writing is completed, the threshold voltage of the selection transistor is set at the time of writing. A data writing method for a nonvolatile semiconductor memory device which is set higher than a value voltage.