JPS57105890A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57105890A
JPS57105890A JP18095380A JP18095380A JPS57105890A JP S57105890 A JPS57105890 A JP S57105890A JP 18095380 A JP18095380 A JP 18095380A JP 18095380 A JP18095380 A JP 18095380A JP S57105890 A JPS57105890 A JP S57105890A
Authority
JP
Japan
Prior art keywords
gate
erase
memory cell
control gate
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18095380A
Other languages
Japanese (ja)
Other versions
JPS616475B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP18095380A priority Critical patent/JPS57105890A/en
Priority to EP81305348A priority patent/EP0054355B1/en
Priority to DE8181305348T priority patent/DE3174417D1/en
Priority to US06/321,320 priority patent/US4437172A/en
Publication of JPS57105890A publication Critical patent/JPS57105890A/en
Publication of JPS616475B2 publication Critical patent/JPS616475B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors

Abstract

PURPOSE:To increase the data write-in efficiency and data readout efficiency, by giving a voltage almost equal to a control gate and an erase gate of a memory cell. CONSTITUTION:A region ABCD indicates a memory cell for one bit's share for this semiconductor storage device. This memory cell consists of a MOS transistor in which the 2nd layer conductor layer 15 is taken as a floating gate, the 3rd layer conductor layer 18 is taken as a control gate, and the 1st layer conductor layer 14 is as an erase gate. The control and erase gates are respectively common, and the erase gate is constituted with a pair of MOS transistors constituted symmetry left and right. The control gate is provided on a semiconductor substrate 11 via an isolation film, and the floating and erase gates are provided in the isolation film clipped with the control gate and the substrate 11 in parallel.
JP18095380A 1980-12-08 1980-12-20 Semiconductor storage device Granted JPS57105890A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18095380A JPS57105890A (en) 1980-12-20 1980-12-20 Semiconductor storage device
EP81305348A EP0054355B1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
DE8181305348T DE3174417D1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
US06/321,320 US4437172A (en) 1980-12-08 1981-11-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18095380A JPS57105890A (en) 1980-12-20 1980-12-20 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS57105890A true JPS57105890A (en) 1982-07-01
JPS616475B2 JPS616475B2 (en) 1986-02-26

Family

ID=16092156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18095380A Granted JPS57105890A (en) 1980-12-08 1980-12-20 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57105890A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0191395A (en) * 1987-10-01 1989-04-11 Toshiba Corp Nonvolatile semiconductor memory
JPH0250398A (en) * 1988-08-12 1990-02-20 Toshiba Corp Nonvolatile semiconductor memory
JP2007505784A (en) * 2003-09-17 2007-03-15 オーシャン パワー デリバリー リミテッド Mooring system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014225642B4 (en) 2014-12-12 2016-06-30 Continental Automotive Gmbh Valve arrangement and high-pressure pump for a fuel injection system of an internal combustion engine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0191395A (en) * 1987-10-01 1989-04-11 Toshiba Corp Nonvolatile semiconductor memory
JPH0250398A (en) * 1988-08-12 1990-02-20 Toshiba Corp Nonvolatile semiconductor memory
JP2007505784A (en) * 2003-09-17 2007-03-15 オーシャン パワー デリバリー リミテッド Mooring system

Also Published As

Publication number Publication date
JPS616475B2 (en) 1986-02-26

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