JPS5798192A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS5798192A JPS5798192A JP17291780A JP17291780A JPS5798192A JP S5798192 A JPS5798192 A JP S5798192A JP 17291780 A JP17291780 A JP 17291780A JP 17291780 A JP17291780 A JP 17291780A JP S5798192 A JPS5798192 A JP S5798192A
- Authority
- JP
- Japan
- Prior art keywords
- line
- gate
- erase
- cell
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
Abstract
PURPOSE:To erase a data a every 1 bit, by constituting so that the potential of a line-line and an erase line of a selected cell of a matrix whose memory cell of 1 bit consists of one transistor is made a low level and a high level, respectively, when erasing a data. CONSTITUTION:A cell M11 consisting of a control gate CG provided through an insulating film on a semiconductor substrate, an erase gate EG providing in the insulating film between said gate and the substrate, a floating gate FG which is provided in parallel with the gate EG, and whose end part is overlapped with a part of the gate EG, a source S and a drain D is placed in the form of a matrix consisting of (i) rows and (j) lines, and gates CG and the gates EG are connected in common by the line-line and the erase line, respectively. For instance, when erasing a data of only a cell Mij, a line-line Pi is made a low level through a line decoder 42 and transistors Qi, TRPi, other line-line are made a high level, and an erase line E-j is made a high level through a row decoder 41, an inverter Ij and a transistor TREj.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17291780A JPS5798192A (en) | 1980-12-08 | 1980-12-08 | Semiconductor storage device |
EP81305348A EP0054355B1 (en) | 1980-12-08 | 1981-11-11 | Semiconductor memory device |
DE8181305348T DE3174417D1 (en) | 1980-12-08 | 1981-11-11 | Semiconductor memory device |
US06/321,320 US4437172A (en) | 1980-12-08 | 1981-11-13 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17291780A JPS5798192A (en) | 1980-12-08 | 1980-12-08 | Semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5798192A true JPS5798192A (en) | 1982-06-18 |
JPS623995B2 JPS623995B2 (en) | 1987-01-28 |
Family
ID=15950739
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17291780A Granted JPS5798192A (en) | 1980-12-08 | 1980-12-08 | Semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5798192A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5513901A (en) * | 1978-07-17 | 1980-01-31 | Hitachi Ltd | Fixed memory of semiconductor |
-
1980
- 1980-12-08 JP JP17291780A patent/JPS5798192A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5513901A (en) * | 1978-07-17 | 1980-01-31 | Hitachi Ltd | Fixed memory of semiconductor |
Also Published As
Publication number | Publication date |
---|---|
JPS623995B2 (en) | 1987-01-28 |
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