JPS5798193A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5798193A
JPS5798193A JP17291880A JP17291880A JPS5798193A JP S5798193 A JPS5798193 A JP S5798193A JP 17291880 A JP17291880 A JP 17291880A JP 17291880 A JP17291880 A JP 17291880A JP S5798193 A JPS5798193 A JP S5798193A
Authority
JP
Japan
Prior art keywords
gate
erase
insulating film
cell
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17291880A
Other languages
Japanese (ja)
Other versions
JPS623996B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17291880A priority Critical patent/JPS5798193A/en
Priority to EP81305347A priority patent/EP0053878B1/en
Priority to DE8181305347T priority patent/DE3171836D1/en
Priority to US06/320,935 priority patent/US4466081A/en
Publication of JPS5798193A publication Critical patent/JPS5798193A/en
Publication of JPS623996B2 publication Critical patent/JPS623996B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Abstract

PURPOSE:To simultaneously erase a data of all cells in a short time, and to prevent breakdown of the cell, by connecting an erase gate of each cell of a matrix whose memory cell of 1 bit consists of one transistor, to an erase terminal through a resistance element. CONSTITUTION:A memory cell M11 of 1 bit is constituted of a control gate CG provided through an insulating film on a semiconductor substrate, an erase gate EG provided in the insulating film between said gate and the substrate, a floating gate FG which is provided in parallel with the gate EG in the insulating film, and whose end part is overlapped with a part of the gate EG through the insulating film, a source S and a drain D. A memory matrix is formed by placing these cells in N lines and M rows, and the gate EG of a cell in said matrix is connected through a resistance 45 to an erase terminal 46 to which data erase voltage is applied when erasing a data.
JP17291880A 1980-12-08 1980-12-08 Semiconductor storage device Granted JPS5798193A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP17291880A JPS5798193A (en) 1980-12-08 1980-12-08 Semiconductor storage device
EP81305347A EP0053878B1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
DE8181305347T DE3171836D1 (en) 1980-12-08 1981-11-11 Semiconductor memory device
US06/320,935 US4466081A (en) 1980-12-08 1981-11-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17291880A JPS5798193A (en) 1980-12-08 1980-12-08 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5798193A true JPS5798193A (en) 1982-06-18
JPS623996B2 JPS623996B2 (en) 1987-01-28

Family

ID=15950759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17291880A Granted JPS5798193A (en) 1980-12-08 1980-12-08 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5798193A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50109682A (en) * 1974-02-04 1975-08-28
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50109682A (en) * 1974-02-04 1975-08-28
JPS5513901A (en) * 1978-07-17 1980-01-31 Hitachi Ltd Fixed memory of semiconductor

Also Published As

Publication number Publication date
JPS623996B2 (en) 1987-01-28

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