JPS5538624A - Nonvolatile semiconductor memory device - Google Patents

Nonvolatile semiconductor memory device

Info

Publication number
JPS5538624A
JPS5538624A JP10937778A JP10937778A JPS5538624A JP S5538624 A JPS5538624 A JP S5538624A JP 10937778 A JP10937778 A JP 10937778A JP 10937778 A JP10937778 A JP 10937778A JP S5538624 A JPS5538624 A JP S5538624A
Authority
JP
Japan
Prior art keywords
memory
information
transistor
operates
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10937778A
Other languages
Japanese (ja)
Other versions
JPS6118840B2 (en
Inventor
Minoru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10937778A priority Critical patent/JPS5538624A/en
Publication of JPS5538624A publication Critical patent/JPS5538624A/en
Publication of JPS6118840B2 publication Critical patent/JPS6118840B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Non-Volatile Memory (AREA)
  • Storage Device Security (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent completely error deletion of memory information by enabling IC itself to function to prevent the memory information from being erased by mistake. CONSTITUTION:When source terminal 3 is applied externally with an erasing voltage, memory transistor Q operates as a transistor in a depletion mode, so that information in memory cell array 1 can be rewritten. When gate terminal 4 is applied externally with the above-mentioned write voltage, on the other hand, memory transister Q operates as a transistor in an enhancement mode, so that information rewriting operation of memory cell array 1 will become impossible. When resistances R2 and R3 are set to values between several and tens KOMEGA, input impedance between source terminal 3 and gate terminal 4 lowers and the binary state of memory transistor Q never changes with an exception of artificial operation. Therefore, error deletion of memory information can be prevented.
JP10937778A 1978-09-05 1978-09-05 Nonvolatile semiconductor memory device Granted JPS5538624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10937778A JPS5538624A (en) 1978-09-05 1978-09-05 Nonvolatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10937778A JPS5538624A (en) 1978-09-05 1978-09-05 Nonvolatile semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS5538624A true JPS5538624A (en) 1980-03-18
JPS6118840B2 JPS6118840B2 (en) 1986-05-14

Family

ID=14508691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10937778A Granted JPS5538624A (en) 1978-09-05 1978-09-05 Nonvolatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5538624A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128068A (en) * 1981-01-30 1982-08-09 Nec Corp Semiconductor memory storage
JPS57164899U (en) * 1981-04-08 1982-10-18
JPS5914199A (en) * 1982-07-13 1984-01-25 Sony Corp Terminal device of character pattern information system
JPS5977699A (en) * 1982-10-25 1984-05-04 Dainippon Printing Co Ltd Integrated circuit card
JPS59185799U (en) * 1983-05-25 1984-12-10 日本電気株式会社 programmable read-only memory
JPS6025099A (en) * 1983-07-22 1985-02-07 Fujitsu Ltd Ep-rom provided with preventing device of writing
JPS6057597A (en) * 1983-09-08 1985-04-03 Oki Electric Ind Co Ltd Programmable rom
JPS6157099A (en) * 1984-08-28 1986-03-22 Matsushita Electric Ind Co Ltd Write inhibit circuit for eprrom
JPS61101856A (en) * 1984-10-24 1986-05-20 Nec Ic Microcomput Syst Ltd Storage device
JPS61140000A (en) * 1984-12-10 1986-06-27 Nec Corp Programmable read-only memory
JPS63245016A (en) * 1987-03-31 1988-10-12 Toshiba Corp Programmable logic device
JPH022772U (en) * 1989-05-17 1990-01-10
EP0840327A1 (en) * 1996-10-30 1998-05-06 STMicroelectronics S.r.l. Protection circuit for redundancy registers set-up cells of electrically programmable non-volatile memory devices

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0131313B2 (en) * 1981-01-30 1989-06-26 Nippon Electric Co
JPS57128068A (en) * 1981-01-30 1982-08-09 Nec Corp Semiconductor memory storage
JPS57164899U (en) * 1981-04-08 1982-10-18
JPS5914199A (en) * 1982-07-13 1984-01-25 Sony Corp Terminal device of character pattern information system
JPH0375907B2 (en) * 1982-07-13 1991-12-03 Sony Corp
JPS5977699A (en) * 1982-10-25 1984-05-04 Dainippon Printing Co Ltd Integrated circuit card
JPS59185799U (en) * 1983-05-25 1984-12-10 日本電気株式会社 programmable read-only memory
JPH042480Y2 (en) * 1983-05-25 1992-01-28
JPS6025099A (en) * 1983-07-22 1985-02-07 Fujitsu Ltd Ep-rom provided with preventing device of writing
JPS6057597A (en) * 1983-09-08 1985-04-03 Oki Electric Ind Co Ltd Programmable rom
JPS6157099A (en) * 1984-08-28 1986-03-22 Matsushita Electric Ind Co Ltd Write inhibit circuit for eprrom
JPS61101856A (en) * 1984-10-24 1986-05-20 Nec Ic Microcomput Syst Ltd Storage device
JPS61140000A (en) * 1984-12-10 1986-06-27 Nec Corp Programmable read-only memory
JPH0524598B2 (en) * 1984-12-10 1993-04-08 Nippon Electric Co
JPS63245016A (en) * 1987-03-31 1988-10-12 Toshiba Corp Programmable logic device
JPH022772U (en) * 1989-05-17 1990-01-10
JPH0426923Y2 (en) * 1989-05-17 1992-06-29
EP0840327A1 (en) * 1996-10-30 1998-05-06 STMicroelectronics S.r.l. Protection circuit for redundancy registers set-up cells of electrically programmable non-volatile memory devices

Also Published As

Publication number Publication date
JPS6118840B2 (en) 1986-05-14

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