JPS56105666A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS56105666A
JPS56105666A JP753180A JP753180A JPS56105666A JP S56105666 A JPS56105666 A JP S56105666A JP 753180 A JP753180 A JP 753180A JP 753180 A JP753180 A JP 753180A JP S56105666 A JPS56105666 A JP S56105666A
Authority
JP
Japan
Prior art keywords
region
burried
type
row line
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP753180A
Other languages
Japanese (ja)
Other versions
JPS5833710B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55007531A priority Critical patent/JPS5833710B2/en
Priority to GB8101744A priority patent/GB2070329B/en
Priority to US06/227,918 priority patent/US4432073A/en
Priority to DE3102175A priority patent/DE3102175C2/en
Priority to DE3153137A priority patent/DE3153137C2/de
Publication of JPS56105666A publication Critical patent/JPS56105666A/en
Publication of JPS5833710B2 publication Critical patent/JPS5833710B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a dynamic memory device in high density by a method wherein when the memory is constructed with FET, an independent burried region is formed under a channel region of FET and used as a row line for writing. CONSTITUTION:An N<-> type first burried region 22 is diffusion-formed in a P<-> type semiconductor substrate 21 and in addition, the independent P<+> type second burried region 23 is formed in the region 22. Then, N<+> type source and drain regions 24, 25 are diffusion-formed in a surface region of the second burried region 22, and a shallow P<+> type channel region 26 is provided between the regions 24 and 25. Thereafter, a gate electrode 28 is cover-attached on the region 26 through a thin gate insulating film 27 and made a FET element. With this construction, the region 24 is used for the row line X1 for reading out, the region 25 for the row line Y2 for reading out, the region 23 for the row line X2 for writing and in addition, the electrode 28 for writing, respectively to form the dynamic memory device.
JP55007531A 1980-01-25 1980-01-25 semiconductor memory device Expired JPS5833710B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55007531A JPS5833710B2 (en) 1980-01-25 1980-01-25 semiconductor memory device
GB8101744A GB2070329B (en) 1980-01-25 1981-01-21 Semiconductor memory device
US06/227,918 US4432073A (en) 1980-01-25 1981-01-23 Semiconductor memory device
DE3102175A DE3102175C2 (en) 1980-01-25 1981-01-23 Semiconductor memory device
DE3153137A DE3153137C2 (en) 1980-01-25 1981-01-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55007531A JPS5833710B2 (en) 1980-01-25 1980-01-25 semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS56105666A true JPS56105666A (en) 1981-08-22
JPS5833710B2 JPS5833710B2 (en) 1983-07-21

Family

ID=11668357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55007531A Expired JPS5833710B2 (en) 1980-01-25 1980-01-25 semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5833710B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005136191A (en) * 2003-10-30 2005-05-26 Toshiba Corp Semiconductor integrated circuit device
JP2008306184A (en) * 2007-06-05 2008-12-18 Samsung Electronics Co Ltd Capacitorless dram and manufacturing method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005136191A (en) * 2003-10-30 2005-05-26 Toshiba Corp Semiconductor integrated circuit device
JP2008306184A (en) * 2007-06-05 2008-12-18 Samsung Electronics Co Ltd Capacitorless dram and manufacturing method therefor

Also Published As

Publication number Publication date
JPS5833710B2 (en) 1983-07-21

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