JPS5555557A - Dynamic memory cell - Google Patents

Dynamic memory cell

Info

Publication number
JPS5555557A
JPS5555557A JP12834378A JP12834378A JPS5555557A JP S5555557 A JPS5555557 A JP S5555557A JP 12834378 A JP12834378 A JP 12834378A JP 12834378 A JP12834378 A JP 12834378A JP S5555557 A JPS5555557 A JP S5555557A
Authority
JP
Japan
Prior art keywords
layer
substrate
memory cell
type
dynamic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12834378A
Other languages
Japanese (ja)
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12834378A priority Critical patent/JPS5555557A/en
Publication of JPS5555557A publication Critical patent/JPS5555557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To provide a dynamic memory cell adapted for high packing density integration by providing a V-shaped groove on the surface of a substrate in the drain region of an insulated gate field effect transistor (FET) to thus from an information storage capacitor so as to thereby reduce the area occupying the capacitance on the surface of the substrate. CONSTITUTION:N<+>-type source region is formed in P<->-type epitaxial layer 1 on a p-type silicon substrate 1, and a thin insulating layer 5 is formed on channel region 3 and drain region 4. A gate electrode layer 6 is formed by polycrystalline silicon layer, and coated on the surface by a SiO2 layer 7. A polysilicon electrode layer 8 is provided on the layer 5. Crystalline plane (100) is used as P<->-type silicon epitaxial layer 1A, and V-shaped groove 10 in cross section is formed on the surface by KOH anisotropic etching process. Then, information memory capacitor is formed at the portion of the groove 10.
JP12834378A 1978-10-20 1978-10-20 Dynamic memory cell Pending JPS5555557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12834378A JPS5555557A (en) 1978-10-20 1978-10-20 Dynamic memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12834378A JPS5555557A (en) 1978-10-20 1978-10-20 Dynamic memory cell

Publications (1)

Publication Number Publication Date
JPS5555557A true JPS5555557A (en) 1980-04-23

Family

ID=14982448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12834378A Pending JPS5555557A (en) 1978-10-20 1978-10-20 Dynamic memory cell

Country Status (1)

Country Link
JP (1) JPS5555557A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535530A (en) * 1980-06-03 1985-08-20 Mitsubishi Denki Kabushiki Kaisha Process for manufacturing a semiconductor memory device
US4751557A (en) * 1982-03-10 1988-06-14 Hitachi, Ltd. Dram with FET stacked over capacitor
US5428236A (en) * 1983-12-15 1995-06-27 Kabushiki Kaisha Toshiba Semiconductor memory device having trenched capicitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535530A (en) * 1980-06-03 1985-08-20 Mitsubishi Denki Kabushiki Kaisha Process for manufacturing a semiconductor memory device
US4751557A (en) * 1982-03-10 1988-06-14 Hitachi, Ltd. Dram with FET stacked over capacitor
US5428236A (en) * 1983-12-15 1995-06-27 Kabushiki Kaisha Toshiba Semiconductor memory device having trenched capicitor

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