JPS55151363A - Mos semiconductor device and fabricating method of the same - Google Patents

Mos semiconductor device and fabricating method of the same

Info

Publication number
JPS55151363A
JPS55151363A JP5901279A JP5901279A JPS55151363A JP S55151363 A JPS55151363 A JP S55151363A JP 5901279 A JP5901279 A JP 5901279A JP 5901279 A JP5901279 A JP 5901279A JP S55151363 A JPS55151363 A JP S55151363A
Authority
JP
Japan
Prior art keywords
type
oxide film
region
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5901279A
Other languages
Japanese (ja)
Inventor
Masamizu Konaka
Yoshio Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP5901279A priority Critical patent/JPS55151363A/en
Publication of JPS55151363A publication Critical patent/JPS55151363A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To prevent the increase of a threshold voltage and an irregularity thereof in a MOS semiconductor device by forming the same conducting type high impurity density buried layer as the substrate at the deep position in either one side of source or drain region side in a channel region. CONSTITUTION:An n<+>-type source region 21 and a drain region 22 are formed on a p-type silicon substrate 11, a polycrystalline silicon oxide film 18 as the gate electrode is formed through a silicon oxide film 17 as a gate insulating film on the channel region between the regions 21 and 22, and the same conducting type high impurity density p<+>-type buried layer 10 as the substrate 11 is formed at deep position at the drain region 22 side in the channel region. Further, a field oxide film 16 and a p<+>-type channel stopper are formed thereon.
JP5901279A 1979-05-14 1979-05-14 Mos semiconductor device and fabricating method of the same Pending JPS55151363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5901279A JPS55151363A (en) 1979-05-14 1979-05-14 Mos semiconductor device and fabricating method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5901279A JPS55151363A (en) 1979-05-14 1979-05-14 Mos semiconductor device and fabricating method of the same

Publications (1)

Publication Number Publication Date
JPS55151363A true JPS55151363A (en) 1980-11-25

Family

ID=13100944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5901279A Pending JPS55151363A (en) 1979-05-14 1979-05-14 Mos semiconductor device and fabricating method of the same

Country Status (1)

Country Link
JP (1) JPS55151363A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6064472A (en) * 1983-09-19 1985-04-13 Toshiba Corp Semiconductor device
JPS6243178A (en) * 1985-08-20 1987-02-25 Mitsubishi Electric Corp Mos transistor
US4680605A (en) * 1984-03-12 1987-07-14 Xerox Corporation High voltage depletion mode transistor with serpentine current path
WO1989012910A1 (en) * 1988-06-23 1989-12-28 Dallas Semiconductor Corporation Enclosed buried channel transistor
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
US5175599A (en) * 1985-04-19 1992-12-29 Kabushiki Kaisha Toshiba MOS semiconductor device
US5448101A (en) * 1992-06-26 1995-09-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having P channel high voltage transistors with improved breakdown voltages
US5731612A (en) * 1995-06-05 1998-03-24 Motorola, Inc. Insulated gate field effect transistor structure having a unilateral source extension
US6617647B2 (en) * 1996-08-13 2003-09-09 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and method of manufacturing the same
US6867085B2 (en) 1996-08-13 2005-03-15 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245279A (en) * 1975-10-07 1977-04-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS53119686A (en) * 1977-03-29 1978-10-19 Agency Of Ind Science & Technol Production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5245279A (en) * 1975-10-07 1977-04-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS53119686A (en) * 1977-03-29 1978-10-19 Agency Of Ind Science & Technol Production of semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6064472A (en) * 1983-09-19 1985-04-13 Toshiba Corp Semiconductor device
US4680605A (en) * 1984-03-12 1987-07-14 Xerox Corporation High voltage depletion mode transistor with serpentine current path
US5175599A (en) * 1985-04-19 1992-12-29 Kabushiki Kaisha Toshiba MOS semiconductor device
JPS6243178A (en) * 1985-08-20 1987-02-25 Mitsubishi Electric Corp Mos transistor
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US4906588A (en) * 1988-06-23 1990-03-06 Dallas Semiconductor Corporation Enclosed buried channel transistor
WO1989012910A1 (en) * 1988-06-23 1989-12-28 Dallas Semiconductor Corporation Enclosed buried channel transistor
US5688722A (en) * 1988-06-23 1997-11-18 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5448101A (en) * 1992-06-26 1995-09-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having P channel high voltage transistors with improved breakdown voltages
US5731612A (en) * 1995-06-05 1998-03-24 Motorola, Inc. Insulated gate field effect transistor structure having a unilateral source extension
US6617647B2 (en) * 1996-08-13 2003-09-09 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and method of manufacturing the same
US6867085B2 (en) 1996-08-13 2005-03-15 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and method of manufacturing the same

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