JPS6064472A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance as well as to suppress the short- channel effect on the titled semiconductor device by a method wherein the third impurity layer having the impurity density higher than that of a substrate is provided on the region located directly below a part of source and drain regions. CONSTITUTION:A source region 42 and a drain region 43 are formed from the first impurity layer 341 and the second impurity layer 342 located on one side and another impurity layer 341 and the second impurity layer 342 located on the other side, and the third impurity layers 36 and 37 having the impurity density higher than that of a substrate 21 is provided on the region located directly below a part of said source and drain regions 42 and 43. As the substrate impurity density of the channel region on the MDS type transistor of this construction is not high, the boosting of VTH caused by the substrate bias is remarkably reduced. Also, the improvement of short-channel effect, the reduction in substrate current, and the improvement of a breakdown voltage can be accomplished, thereby enabling to remarkably improve the junction capacitance of the titled semiconductor device.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device, and relates to a source for tFf.

This invention relates to an MOa type transistor with an improved fin region.

[Technical background of the invention and its problems]

As is well known, the increase in the degree of integration of <1 MIa type integrated circuits.

In recent years, with the increase in memory capacity, it has become increasingly important to shorten the gate length.

The thinning of gate insulating films is accelerating.

As the gate length is shortened, various problems arise in the characteristics of the MIS type transistor.

For example, due to the phenomenon of a low threshold voltage (VTll) called the short channel effect, frost near the drain occurs when operating in the saturated region, and tOL occurs due to the increase in rc and the drain tOL. As the substrate current increases due to the electron-hole pairs, the substrate near the source increases as the current increases.
A sudden increase in drain current (breakdown voltage) due to activation of an n (source)-p-(substrate)-n (drain) bipolar transistor due to a rise in potential, and a large electric field between the gate and drain. Problems such as VT fluctuation and gm reduction occur due to hot carrier injection into the gate insulating film under bias conditions. To avoid such problems, it is important to reduce the electric field strength near the drain as much as possible, and one way to solve this problem is to
s.

Electron Devicea Vol, ED-
27, NO, 8.

Aug, 1980, l), 1359 [Desig
n &Chatacteristics of the
LightlyDoped Drain-FJoac
e(LDD)InsulatedGate ll'1e
Lightly Doped Drain disclosed in ld-Effect Transistor J
An MO8 type transistor having a (LDD) structure is known.

(hereinafter) will be explained with reference to FIG. 1 in the figure is a P-type semiconductor substrate with an element isolation region 2 provided on its surface.

A gate electrode 6 is provided on the plurality of island regions 3 separated by the element isolation region 2 with a gate insulating film 4 having a thickness of approximately 200 mm interposed therebetween, and an insulating material 6 is provided on the sidewalls of the gate electrode 5. It is provided. The impurity concentration in Table 1 (2) near the gate W pole 5 in the IJ island region is relatively low (for example, lO'?
~1OI8shin-2) and has a relatively shallow diffusion depth (for example, 0.2 μm).

81 is provided, and adjacent to these impurity layers 7I and 8I and further away from the gate electrode 5 of the island region 3, there is a surface impurity layer <l! I is approximately 1×10"a, -") and the diffusion depth is deep (IuJ is 0.45 μm) and the second impurity is 7□, 8! are provided extensively. And - the first of forces. The source region 9 is constituted by the impurities 1m71+7t of ta2, and the other first. The second impurity layer 8@, +8t constitutes the strain region JO. Also.

The gate is placed on the substrate J including the pole 5, etc., with Fi and interlayer insulation P.
IAJI is provided, and a gate electrode 5. Contact holes J2... are opened in partial holes corresponding to parts of the tops of the source and fin regions 9.10, and these contact holes J2... have large Al interconnections 13... is provided.

According to the multiple transistors shown in FIG. 1, a first impurity layer 81 having a relatively low impurity concentration and forming a part of the drain region 10 is provided in the vicinity of the gate electrode 7 of the island region 3. Therefore, a depletion layer spreads within this impurity layer 81 due to the tortoise pressure (% relative to the substrate), and the drain region J
This has the effect of significantly relaxing the electric field strength near O. Therefore, it is effective in reducing the substrate current based on the generation of 'a-son-hole pairs, and it can be expected to improve the pre-down voltage.

However, this transistor is not very effective against the 7-yoto channel effect. For this reason, by ion-implanting p-type impurities into the channel region of the island region 3, VTH can be reduced due to the short channel effect.
A method to suppress this has been proposed.

However, although ion implantation into this layer region has the effect of raising the surface bottom of the channel region and lifting up the VTR, it also has the disadvantage of increasing the substrate bias effect, as shown in FIG. This substrate bias effect refers to the coupling of n-nayanel transistors, for example.
If a negative bias is applied to the substrate with respect to the source city No. 1, V T I + will be affected, and it is a good idea to minimize the increase in the armpit for the applied 1L pressure. Become. Note that 0) in FIG. 2 indicates the characteristic curve of the transistor shown in FIG.

In addition, conventionally, as an M08 type transistor that can suppress the Njot-Yanel effect and reduce the substrate bias effect,
IEDM'82 1)igca! of+echni
cal papers p, 718 [A, Half
Micro MOSFET using Double
The LL)D structure with p-pocket disclosed in eIplanted LDD j is also known.

This storehouse, Figure 3'! ! -1=Explain in the light Z] Note that transistors having the same number of gates as the transistor shown in FIG. The percentage characteristics of the transistor in FIG. 3 are the first impurity layer 71y81 with a low impurity concentration.
The point is that relatively high concentration P-type third impurity layers 14 and 15 are provided at the bottom. According to this transistor, since the third impurity layer 14°15 is provided, it is possible to suppress the spread of the depletion layer from the drain region 1° to the channel region, and it is possible to improve the 7. , in order to avoid increasing the substrate concentration in the channel part, (
As shown in Fig. 2, it is possible to suppress the rate of increase in VT)I due to the substrate bias effect to a small value. Therefore, it is effective for miniaturizing elements.

However, according to a transistor having an LDD structure with a p-type dot, the third impurity layer 14.15 is connected to the gate '1'.
1', the source and drain regions near the pole 5 must be selectively formed densely only in the source and drain regions 9.10, so the impurity concentration is inevitably higher than in the case of 1-on implantation into the channel region as described above. The need arises. In addition, the impurity layer J
4.15 is the source immediately after 1 normal gate 14 pole 5 shadow formation.

Approximately 1 impurity M7. in drain regions 9, 1o. .

8. Since it is formed at one time, a relatively long heat treatment process is added after impurity ion implantation.
Impurities will diffuse. Therefore.

The second impurity layer 7ffi+81, which forms part of the source and drain regions y and to, is diffused deeply, and the source and drain regions ffj (green 9, 10) (2) The junction table h1 becomes visually higher. This is G'''2, and the diffusion depth of the second impurity layer 7*+81 is -(-'s3 of the impurity layer 14
．． Considering the diffusion depth rc of 15), it becomes a problem of adding %I/ζ to the leakage distribution. 1st distribution IEDM'82 Digest
of 'I'technical papers p.
718, the depth of the second impurity layer 2t+81 is the third
Since the depth of the third impurity layer 14,15 is exceeded, the increase in junction capacitance due to the formation of the third impurity 1ψ14°15 is not significant. However, the second impurity layer 7. ．． 8. Increasing the depth of sales is also undesirable, as it significantly increases the separation shouting area and the lateral dimensions h).

These increases in junction capacitance lead to low V- switching speeds in logic circuits, lower operating margins in memories, and deterioration of characteristics.

[Purpose of the invention]

This invention V has been made in view of the above circumstances.

It is an object of the present invention to provide a semiconductor device having various effects such as being able to reduce junction capacitance and suppressing the /iodine channel effect.

[Summary of the invention]

The present invention comprises a g+, λ semiconductor ^4: plate having a plurality of island regions separated by candy'0# regions on one surface, and a gate electrode provided on the front brj island region via a gate insulating film. , between the low concentration first impurity layer forming a part of the source and drain regions provided very close to the gate 1a on the surface of the Shimada region, and the island region surface 'd'lr K@' as it moves away from the gate electrode, The impurity layer provided in V17A contact with the impurity layer 1rII, a high concentration second impurity layer constituting source and drain regions, respectively, and gate electrodes directly under the first impurity layer and the second impurity layer. A third impurity layer of the first exclusive type having a higher density than the substrate is formed on a portion of the side and has a different width, thereby achieving the object described in 11iJ.

[Embodiments of the invention]

An MO8 type transistor according to an embodiment of the present invention will be described below in the order of manufacturing steps with reference to FIGS. 4(a) to 4(f).

[JJ Masu, 17! For example, after the entire element portion 1iiIE head region 22 is formed on the surface of the P-type Si substrate 21 by selective oxidation, etc., the portion (polished island region 23) is formed in this element isolation region 22.
13. with a thickness of 200Δ on the surface. , conversion! , +241r was formed. Polycrystalline 7 with a thickness of 4000 A is applied to the entire surface.
Recon l'a'i 2s 'f shadow formation (ki, 4th figure (a
Moon Nu 1).

Next, by photolithography, til, Iit polycrystalline 7
A resist pattern (not shown) was formed on the silicon layer 25 in the area where the gate electrode was to be formed. Thereafter, using the resist pattern as a mask, the commercially available polycrystalline silicon layer 2 was selectively etched away to form the gate 1a pole 26. In history, peel off the resist pattern, gate 1
Using the 11-pole 26 as a mask, the target self-containing film 24 was selectively removed to form a gate insulating film 27. Continuing with the aforementioned Gate i! Using the pole 26 as a mask, an n-type impurity such as phosphorus is applied to the surface of the substrate 21 at an accelerating voltage of 25 KeV.

Ion implantation was performed at a dose of ff18 x 10"a-".

Low concentration first ion implantation layer;! 8.29 was formed (
(Illustrated in FIG. 4(b)). Note that arsenic ions may be implanted in place of phosphorus. Thereafter, a resist pattern 30 is formed by photo-etching (PEP) method so as to cover a portion of each of the ion-implanted layers 28 and 29 of A1. Boron was accelerated at a voltage of 120 KeV, with a doping amount of 2 x 10”m, -
The third ion implantation layer 31.3 was implanted under the following conditions.
2 (as shown in FIG. 4(c)).

00 Next, heat treatment is performed for 60 minutes in an oxidizing atmosphere of 900'Q to form an oxide film 33 on the exposed surface of the substrate 2 and an oxide film 33. was formed. At the same time, the phosphorus ions in the first ion implantation J@28 and 29 are activated to form a low concentration first impurity layer 341.

351 and the third ion implantation 1fds
A third impurity layer 36, :47 was formed by activating the boron atoms in i and sz to a large extent. Next, CVD-8i0. 71.900° C. at which film 38 was formed.

CVD-8i0. for 30 minutes. The membrane 38 was hardened (as shown in FIG. 4(d)). Then 1-reactive 1-on etching RIE
K! ' * n ge CvD 8 + 01 membrane 3
8 was removed by etching until the substrate 21, gate tb, and electrode 26 were exposed. As a result, the oxide film 33. is formed only on the side walls of the gate electrode 26. CVI)-8i0. membrane 38'
remained. In addition, this residual CV D-8i 0. f
The shape of Ql g' is the same as that of CVD-8i0. membrane 3s
'ノBp3. vc x test is determined. After this, game) N, a+ 26 and remaining c V D-8i 0
．． llO! 3 B' k masked 1. ”'C'iif
, arsenic is applied to the surface of the substrate 21 at an accelerating voltage of 50 KeV.
.

Ion implantation was performed at a dose of 3×1O” under 10 conditions.
High residual second ion implantation 11i J s , 4o
f was formed (as shown in FIG. 4 (-)).

011) Next, whole blood VCCVD-8i 0. GL,
Suppose a laminated film 4J is formed by sequentially depositing B P 8 G films and the like.

Heat treatment such as ring getter, glass flow, etc. at 900℃.
It lasted about 90 minutes. As a result, the arsenic ions in the second ion-implanted layer 39, 40 are activated and the second ion-implanted layer 39, 40 is activated.
impurity layers 34□, 35! is formed, and the first
Impurity layer 34. ．． 35. 9. Also spreads slightly in the depth direction.
First and second impurity layers 341, :44. A source region 42 . 1st. Second impurity layer 351.

Drain regions 43 consisting of 35 and 35 were respectively formed. Here, the first impurity layer of low @ degree 34°, 3s@,
The h-plane @a is approximately I
．． ．． 35. The surface concentration was about IQ"a-" and the diffusion depth was 0.21 μm.

Note that the first impurity layer 34. , :451 for the second impurity Id34. , 35. The controllability over the depth can be kept within ±15% with current technology. Next, the second impurity layer 34 of the source and drain regions 42 and 43 is formed. .

35 and a portion of the gate electrode 26, contact holes 44, . . . Next, an AI wiring 45 connecting the second impurity layer 34Re35N and the gate to the pole 26 via the contact hole 44 was formed to manufacture a 1M08 type transistor (as shown in FIG. 4(f)). .

The MOB type transistor according to the present invention is shown in FIG. 4'(f).
As shown in FIG. Second impurity layer 34, . 34
．． and the other 1st. Second 361.35. Source and drain regions 42 and 43 were provided respectively from the source and drain regions 42 and 43, and a third impurity layer 36 and 37 having a higher impurity concentration than that of the substrate 21 was provided directly over a portion of each of these source and drain regions 42 and 43. It has a structure.

According to one aspect of the invention, the source and drain regions 42
, 43, the impurity concentration of the substrate 21 is higher than the impurity concentration of 81I! Since the impurity layer 36,37 of 3 is provided and the substrate impurity concentration in the channel region is not high, the rise in VTH due to substrate bias is significantly reduced, and the improvement of the 7 Yot-Jannel effect, reduction of substrate current, and breakdown voltage are achieved. Once the improvement is achieved, the VC1 junction capacitance can be significantly improved. Here, the junction capacitance will be considered in comparison with the case of the transistor shown in FIG. 3, which has already been described. In the transistor shown in Fig. 3, since the second impurity layer is diffused deep, the junction capacitance in the source and drain regions is large on the sides, and the third impurity layer is in the source and drain regions. Since it is thought to be formed on the entire surface immediately below the area, the volume of the bottom surface is also taken into consideration. Therefore.

The depth of diffusion of the second impurity layer needs to be shallow in order not to reduce the side surface volume. Therefore.

Assuming that the second impurity layer is formed to the same diffusion depth as the first impurity layer as in the above embodiment, the third impurity layer is
Let's look at the area ratio of the bottom surface where the impurity 1- and the second impurity layer are in contact. In this case, the contact hole radius is 1 μm,
Assuming that the width of the impurity layer of m1 is 0.3 μm, and assuming that the 1 alignment accuracy is 8*, the third
When the area of the bottom in contact with the impurity layer is 1, the area of the transistor shown in FIG. 3 is 2 to 2.5 times larger.

Normally, the evaporation of the side and bottom surfaces of the junction is approximately 0.3 fF/
μ'', t' IyJ, O-07f F/μm2a
t1'-C6le. Mata.

The bottom capacitance R when forming the third impurity layer is approximately 0.4f
F/μm2. From these values, when considering a transistor with a channel length of L=1 μm and a channel width of W=5 μm as a whole, the junction capacitance is improved by about 30%. From the above, it can be confirmed that the MO8 type transistor according to the present invention is superior to the conventional one.

In the above embodiment, the entire island region was exposed during the ion implantation for forming the first impurity Ml, but r$i
Ions may be implanted to remove the scars. In such a case, it is effective to prevent contamination caused by exposure of the island region in one step of the first photolithography. Also, although ion implantation into the chawl portion is not mentioned, V'TH arsenic/shallow Tejnerdorf can be carried out in the same manner as in the prior art.

As an MO8 type transistor according to the present invention.

For example, not limited to what is shown in FIG. 4 mentioned above.

As shown in the fifth image, the second impurity j% s, v, s 4 of the source and drain regions 51 and 52, respectively, may be of Tsuge's type, in which the portions corresponding to the contact holes 44, 44 are formed deeper. . The source and drain regions 5t and sx are connected to a contact ball 44 to a second impurity 1i such as the MO8 type transistor C' in FIG. 4(f).
, 44, for example, by phosphorus diffusion, or by heat treatment after ion implantation of phosphorus.

This MO8 type transistor has a source.

Drain eRhA67, 5z contact hole 44
．． Since the diffusion depth of the part corresponding to 44 is deeper, Al
It is possible to prevent A4 from passing through when forming the wiring 4b.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to provide a highly reliable semiconductor koji which has various effects such as reducing junction capacitance and suppressing short channel effects.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional LDD structure MOS transistor, and Figure 2 is a cross-sectional view of a conventional LDD structure MOS transistor. FIG. 3 is a characteristic diagram for explaining the substrate bias effect due to doping. FIG. 3 is a cross-sectional view of another conventional L1) D-transverse MO8 type transistor. Figures 4 (a) to (Q) are cross-sectional views showing an MO8 type transistor according to one embodiment of the present invention in the order of manufacturing steps;
FIG. 2 is a cross-sectional view of an os-type transistor. 2) P-type Si substrate (semi-solid substrate), 22...
Group member 1i11f 餉 area, 23...Island area, 24, 33
゜, 33. ...Oxide film, 25...Polycrystalline silicon. 26... Gate electrode, 27... Gate insulating film, 28
．． 29, 31, 32, 39.40... ion implantation layer,
341 , :44z , 351 , :4.5z , :4
6゜37...Impurity N, t18, 38''・-C
VD-8in. Membrane, 47...Naralayer membrane, 42.51...Source heading. 43.52...Draining area, 4i...Contact hole, 45...Al wiring. Dispatch agent Patent attorney Suzue Akihiko Figure 1 212 Figure 2 3rd Vsub 4th WJ

Claims (1)

[Scope of Claims] 0) a semiconductor substrate of a first conductivity type having a plurality of island regions separated by element isolation regions on the surface thereof, and a gate electrode provided on the island regions with a gate insulating film interposed therebetween; a first impurity layer with a low concentration forming part of the source and drain regions, respectively, provided near the gate electrode on the surface of the island region; On the surface of the island region, a highly concentrated second impurity layer is provided which is located away from the gate electrode and adjacent to the impurity layer and constitutes source and drain regions, respectively, and directly below the first impurity layer. and a third impurity layer of a first conductivity type having a height me than the substrate and formed directly under a portion of the second impurity layer on the gate electrode side. (2) The diffusion depth of the second impurity layer at least in the region closer to the gate electrode is approximately equal to or shallower than the diffusion depth of the first impurity layer. Semiconductor equipment.