JPH06104429A - Mos transistor - Google Patents

Abstract

PURPOSE:To provide a reliable MOS transistor where a tunnel current is hard to occur even if a gate insulating film becomes thin and besides the gate insulation resistance is improved. CONSTITUTION:This is a MOS transistor where gate insulating films 2 and 2a are made thicker at the end on the side of the drain region 8 of a gate electrode or at both ends than other parts. Moreover, the breakdown strength of the substrate 1 is made lower than that of the gate electrode 3 by forming a intermediate concentration impurity region 10 of the same conductivity type as that of a semiconductor substrate between the drain region 8 and the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

The present invention relates to MOS transistors. More specifically, the present invention relates to a fine MOS transistor in which band-to-band tunnel current is unlikely to occur even when the gate insulating film becomes thin and the electrostatic withstand capability does not deteriorate.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of elements due to high integration of semiconductor circuits, MOS transistors have LDDs (Lightly Doped Drains) that prevent injection of hot electronron by making the gate electrode side of the drain region a low concentration region. The structure type has been adopted. FIG. 5 is a sectional view showing the structure of a conventional MOS transistor having an LDD structure. A gate insulating film 22 is formed on a semiconductor substrate 21 made of p-type Si, polysilicon is deposited on the surface of the gate insulating film 22, and then the periphery of the channel region is removed to form a gate electrode 23 having a gate length L.
Are formed. Then, by implanting phosphorus ions (P ⁺ ) using the gate electrode 23 as a mask, n ⁻ -type impurity diffusion regions 24 and 25 having a relatively shallow diffusion depth are formed. A side wall 26 is formed of a silicon oxide film or the like on the side of the gate electrode 23, and arsenic ions (As ⁺ ) are further implanted using the side wall 26 as a mask to form a channel region (semiconductor substrate region immediately below the gate electrode 23). An n ⁺ type source region 27 and a drain region 28 are formed on both sides of 29.

In this structure, the gate insulating film becomes thinner with the miniaturization of the transistor, but when the gate insulating film becomes thinner, soft leakage due to the band-to-band tunnel current and the electrostatic withstand capability against external surge occur. Here, the band-to-band tunnel current means a current flowing to the substrate side when the impurities in the LDD diffusion layer generate electrons due to the electric field strength of the gate electrode.

Although the LDD structure has a high resistance to hot electrons which prevents hot electrons from being injected into the gate electrode, it causes an increase in soft leak current. Also, since the breakdown voltage between the drain and the substrate is higher than that of the gate insulating film, when the drain terminal is directly connected to the output pin, the static electricity applied to the output pin is applied to the gate electrode side, and the gate insulating film is easily destroyed. As a result, the electrostatic discharge withstand capability will drop significantly. In order to solve these problems, by increasing only the gate film thickness of the I / O part which is the input / output part or increasing the concentration of the channel stopper,
The breakdown voltage between the drain and the substrate is set lower than the breakdown voltage of the gate insulating film.

[0005]

[Problems to be Solved by the Invention] However, I / O
If the gate film thickness of the portion is increased, the number of mask processes is increased by one, resulting in an increase in the number of processes and an increase in cost. Further, when the concentration of the channel stopper is increased, the depth (width in the direction perpendicular to the paper surface in FIG. 5) ΔW of the channel region increases, and as a result, a narrow channel effect occurs in which the threshold voltage increases.

In order to solve such a problem, according to the present invention, even if the gate insulating film becomes thin, a band-to-band tunnel current does not easily occur, the electrostatic breakdown resistance does not decrease, and the manufacturing process is not increased. It is an object of the present invention to provide a fine MOS transistor that can be manufactured.

[0007]

In a MOS transistor according to the present invention, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region are formed on the semiconductor substrate on both sides of the gate electrode. A MOS transistor having a low-concentration impurity region at least on the gate region side of the drain region, wherein the gate insulating film is formed thicker than other portions at least at the drain-side end of the gate electrode. And

It is preferable that the thickly formed portion of the gate insulating film is formed so as to cover the entire surface of the low concentration impurity region.

According to another aspect of the MOS transistor of the present invention, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a source region and a drain region are formed on the semiconductor substrate on both sides of the gate electrode, and at least the drain is formed. MOS in which the gate region side of the region is a low concentration impurity region
In the transistor, a high-concentration first-conductivity-type semiconductor region is formed immediately below the contact hole in the drain region,
A second-conductivity-type semiconductor region of medium concentration is formed thereunder,
A low-concentration second-conductivity-type semiconductor substrate is arranged on the lower side thereof.

[0010]

According to the present invention, since the gate insulating film is formed thick at the end portion of the gate electrode, the withstand voltage between the drain and the gate is greatly improved. On the other hand, the central part, which is the majority of the gate insulating film, can maintain a thin gate insulating film and operate at a low gate voltage. In this case, LDD
It is more effective if the entire diffusion layer (low-concentration impurity region) is covered with a thick insulating film.

Further, by increasing the concentration of the substrate in the portion in contact with the drain region, the dielectric strength between the drain region and the substrate is relatively lowered, and even if a large electrostatic field is applied, the static electricity in the gate insulating film is increased. Electric breakdown is prevented and reliability is improved.

Further, the thick oxide film is formed in a self-aligned manner and provided without increasing the number of steps.

[0013]

The present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a fine MO which is an embodiment of the present invention.
It is sectional drawing which shows the structure of an S transistor. The gate insulating film 2 is formed thick at both ends of the gate electrode 3, and the thick insulating film 2a completely covers the low concentration impurity regions 4 and 5. As a result, even if the gate insulating film 2 is thin, the low-concentration impurity regions 4 and 5 are not easily affected by the electric field strength of the gate electrode 3, so that the impurities do not generate electrons and a current does not flow to the substrate side. In this way, the generation of band-to-band tunnel current can be prevented. Further, the drain region 8 and the substrate 1 are formed by the thick insulating film 2a.
The breakdown voltage between the drain region 8 and the gate electrode 3 via the gate insulating films 2 and 2a is larger than the breakdown voltage between the gate insulating film 2 and the gate electrode 3. It is preferable that the thick insulating film 2a described above completely covers the low-concentration impurity region, but the thick insulating film 2a is effective even if it is not completely covered.

Further, the n ⁺⁺ type drain region 8 and the p type S
A medium-concentration p ⁺ type semiconductor region 10 is provided between the i substrate 1. By increasing the concentration of the substrate 1 in contact with the drain region 8 in this manner, the drain region 8
The breakdown voltage between the substrate and the substrate 1 is reduced. As a result, rather than the breakdown voltage between the drain region 8 and the substrate 1, the gate insulating film 2a
The breakdown voltage between the drain region 8 and the gate electrode 3 via the gate electrode becomes larger. Therefore, even if a surge voltage is applied, it escapes to the substrate 1 side and the gate insulating film 2 is less likely to be destroyed.

With the above configuration, even when the drain terminal is directly coupled to the output pin,
The gate insulating film is not destroyed. Moreover, there is no problem of increasing the number of mask steps for increasing the gate insulating film thickness of the I / O portion and the narrow channel effect caused by increasing the concentration of the channel stopper, unlike the conventional case.

FIG. 2A shows an I- between the drain region 8 and the substrate 1 in the fine MOS transistor of the present invention.
The V characteristic A and the IV characteristic B between the drain region 8 and the gate electrode 3 via the gate insulating film are shown in a graph. In addition, as a comparative example, FIG.
A graph shows an IV characteristic C between a drain region and a substrate and an IV characteristic D between a drain region and a gate electrode via a gate insulating film in a transistor. From the graph, in the present invention, the breakdown voltage V ₂ between the drain region and the gate electrode via the gate insulating film 2 is larger than the breakdown voltage V ₁ between the drain region and the substrate, and the drain region and the substrate are large. It can be seen that there is also no soft leak E (see FIG. 2B).

When the Si substrate 1 is p-type as described above, the medium-concentration semiconductor region 9 is also p ⁺ -type, and the drain region 8 is conversely n ⁺⁺ -type.

Although the gate insulating film 2 is formed thick at both ends of the gate electrode 3, it is not always necessary to make both ends thick. That is, it may be only on the drain region 8 side connected to the output pin to which the surge voltage is easily applied.

Further, as shown in FIG. 1, a medium-concentration p ⁺ type semiconductor region 9 may be formed between the source region 7 and the substrate 1.

FIG. 3 is a graph showing the profile of the impurity concentration along the line XX and the line YY in FIG. C _{1 to} C ₄ in the graph indicate the impurity concentrations at the positions C _{1 to} C ₄ in FIG. As can be seen from the graph, the profile of the impurity concentration along the line X-X passing through the drain contact hole 19 serving as an electrode shows a smaller change in the concentration difference than that along the line Y-Y, and thus (C ₄ concentration-C ₃ concentration ) <(C ₁ concentration−C ₂ concentration), the absolute concentration is higher in the XX line region, and the breakdown voltage is lower in the XX line portion than in the YY line portion. Therefore, the surge voltage input to the drain region 8 via the output pin easily escapes to the substrate 1 side, and the gate insulating film 2 is not destroyed.

In the embodiment described above, the gate insulating film 2a at the end of the gate electrode 3 is thickened, and the impurity concentrations of the drain region 8 and the source region 7 are increased,
Both of forming the medium-concentration regions 9 and 10 of the same conductivity type as the substrate 1 of the second conductivity type under the region have been described, but it is not necessary to perform both at the same time, and one of them has a great effect. .

Next, an example of a method for manufacturing the MOS transistor of the present invention will be described.

First, the channel stopper 11 and the field insulating film are formed on the p-type semiconductor substrate 1 by a normal manufacturing process.
12 is formed, and then the gate insulating film 2 is provided (see FIG. 4).
(See (a)).

Next, a polysilicon film 13 doped with phosphorus (P) as an impurity is deposited by a low pressure CVD method, and a thin polysilicon oxide film 14 is formed thereon by a thermal oxidation method. Further thereon, a silicon nitride film 15 is patterned (see FIG. 4B).

Next, the gate electrode 3 is formed by reactive ion etching using the silicon nitride film 15 as a mask. Then, phosphorus is ion-implanted using the gate electrode 3 as a mask to form low-concentration impurity regions 4 and 5 (see FIG. 4C).

When the substrate in this state is oxidized at about 900 ° C. for about 15 minutes, since polysilicon is more easily oxidized than single crystal silicon, the side surface of the gate electrode 3 is oxidized. Silicon nitride film
Since 15 is an antioxidant film, the surface side is not oxidized so much, and as shown in FIG. 4D, the substrate 1 side is widely oxidized and a thick oxide film 2a is formed at the gate edge portion. Then, the silicon nitride film 15 is removed using hot phosphoric acid. Subsequently, silicon oxide (S) was formed by a CVD method (820 to 850 ° C., 30 to 40 minutes) in which SiH ₄ gas and N ₂ O gas were introduced.
iO ₂ ) is deposited on the entire surface and etched back by the RIE method or the like to form the sidewall 16 (FIG. 4D).
reference).

Arsenic (As) is ion-implanted using the gate electrode 3 provided with the sidewalls 16 as a mask to form a high-concentration n-type source region 7 and drain region 8 (see FIG. 4D). .

Next, a BPSG (boron phosphorus silicate glass) film 17 is deposited on the entire surface by a low pressure CVD method, and then contact holes 18 and 19 are formed (see FIG. 4E).

First, boron (B) is ion-implanted through the contact holes 18 and 19. Boron ions are easily implanted relatively deeply, and n ⁺ type source region 7 and drain region 8 are formed.
Is neutralized to some extent, but p
⁺ Medium-concentration impurity regions 9 and 10 are formed. Then, arsenic is ion-implanted to make the portion neutralized with the boron ions into the n-type again, and the n ⁺⁺ -type source region 7 and the drain region 8 of higher concentration are formed, as shown in FIG. A MOS transistor having such a structure is completed.

[0031]

According to the present invention, since the gate insulating film is formed thick at the end portion of the gate electrode, it is possible to prevent generation of band-to-band tunnel current and improve the dielectric strength of the gate insulating film. .

Further, by increasing the concentration of the substrate in the portion which is in contact with the drain region, the breakdown voltage between the drain region and the substrate is lowered, and the breakdown voltage between the drain region and the gate electrode through the one-layer gate insulating film 2 is lowered. Is larger, and gate breakdown can be prevented.

Further, according to the present invention, it is possible to obtain a high-performance MOS transistor which can improve the gate dielectric strength without increasing the number of masking steps, is inexpensive, and can withstand a surge voltage or the like.

[Brief description of drawings]

FIG. 1 is an explanatory cross-sectional view showing the structure of a MOS transistor of the present invention.

FIG. 2 is a diagram showing an IV characteristic between a drain region of a MOS transistor and a substrate and an IV characteristic between a drain region and a gate electrode via a gate insulating film. (B) is based on a conventional transistor.

3 is a diagram showing a profile of an impurity concentration from the substrate surface to the inside of the substrate along the line XX and the line YY in FIG.

FIG. 4 is an explanatory view showing the manufacturing process of the MOS transistor of the present invention.

FIG. 5 is a cross-sectional explanatory view showing the structure of a conventional LDD structure MOS transistor.

[Explanation of symbols]

 1 semiconductor substrate 2 gate insulating film 2a thick part of gate insulating film 3 gate electrode 4, 5 low concentration impurity region 7 source region 8 drain region 9, 10 medium concentration semiconductor region

Claims (3)

[Claims] 1. A gate electrode is formed on a semiconductor substrate via a gate insulating film, a source region and a drain region are formed on the semiconductor substrate on both sides of the gate electrode, and at least the drain region on the gate region side is a low concentration impurity region. And the gate insulating film has at least a drain side end of the gate electrode,
A MOS transistor that is formed thicker than other parts. 2. The MOS transistor according to claim 1, wherein the thickly formed portion of the gate insulating film is formed so as to cover the entire surface of the low concentration impurity region. 3. A gate electrode is formed on a semiconductor substrate via a gate insulating film, a source region and a drain region are formed on the semiconductor substrate on both sides of the gate electrode, and at least the gate region side of the drain region is a low concentration impurity region. A high-concentration first-conductivity-type semiconductor region is formed immediately below the contact hole in the drain region, and a medium-concentration second-conductivity-type semiconductor region is formed thereunder. A MOS transistor in which a low-concentration second conductivity type semiconductor substrate is arranged on the lower side.