KR100221620B1 - Semiconductor device and the manufacturing method thereof - Google Patents
Semiconductor device and the manufacturing method thereof Download PDFInfo
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- KR100221620B1 KR100221620B1 KR1019960035016A KR19960035016A KR100221620B1 KR 100221620 B1 KR100221620 B1 KR 100221620B1 KR 1019960035016 A KR1019960035016 A KR 1019960035016A KR 19960035016 A KR19960035016 A KR 19960035016A KR 100221620 B1 KR100221620 B1 KR 100221620B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서 제1도전형의 반도체기판 상의 소정 부분에 소자의 활성영역을 한정하는 소자분리막으로 형성하고 상기 활성영역상의 소정 부분에 게이트산화막 및 게이트를 형성하는 공정과, 상기 게이트의 일측 측면을 포함하는 반도체기판의 소정 부분이 노출되게 감광막을 형성하는 공정과, 상기 게이트와 감광막을 마스크로 사용하여 반도체기판의 노출된 부분에 제2도전형의 불순물을 수직 방향으로 도핑하여 저농도영역을 형성하는 공정과, 상기 게이트의 상기 감광막이 형성되지 않아 노출된 일측 측면에 제1측벽을 형성하는 공정과, 상기 감광막, 게이트 및 제1측벽을 마스크로 사용하여 상기 저농도영역의 하부에 제1도전형의 펀치-스루우 스토퍼를 형성하는 공정과, 상기 제1측벽의 측면에 제2측벽을 형성하는 공정과, 상기 감광막을 제거하고 게이트와 제1 및 제2측벽을 마스크로 사용하여 상기 반도체기판에 제2도전형의 불순물을 고농도로 도핑하여 소오스 및 드레인영역을 형성하는 공정을 구비한다. 따라서, LDD 구조를 이루는 저농도영역과 펀치-스루우 스토포가 드레인영역에만 형성되므로 소오스저항이 감소되어 전류 구동 능력이 향상되며, 펀치-스루우 스토퍼가 수직 도핑에 의해 저농도영역을 에워싸지 않고 하부에 형성되므로 채널 저항 및 접합 용량이 감소될 뿐만 아니라 도핑이 용이하다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an isolation layer defining an active region of an element in a predetermined portion on a first conductive semiconductor substrate, and forming a gate oxide film and a gate in the predetermined portion on the active region; And forming a photoresist film to expose a predetermined portion of the semiconductor substrate including one side surface of the gate, and using the gate and the photoresist as a mask to expose impurities of the second conductivity type in a vertical direction to the exposed portions of the semiconductor substrate. Forming a low concentration region by doping; forming a first side wall on one side surface of the gate where the photoresist film is not formed; and using the photoresist, gate, and first side wall as a mask. Forming a punch-through stopper of the first conductivity type in the lower portion, and forming a second side wall on the side of the first side wall; Is the step of removing the photosensitive layer and using as a mask the gate and the first and second walls of the second doped with an impurity of the conductivity type at a high concentration in the semiconductor substrate includes a step of forming the source and drain regions. Therefore, since the low concentration region and the punch-through stopper forming the LDD structure are formed only in the drain region, the source resistance is reduced and the current driving capability is improved, and the punch-through stopper does not surround the low concentration region by vertical doping, The formation reduces channel resistance and junction capacity as well as facilitates doping.
Description
제1도는 종래 기술에 따른 반도체장치의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
제2a도 내지 d도는 종래 기술에 따른 반도체장치의 제조 공정도.2A to 2D are manufacturing process diagrams of a semiconductor device according to the prior art.
제3도는 본 발명에 따른 반도체장치의 단면도.3 is a cross-sectional view of a semiconductor device according to the present invention.
제4a도 내지 d도는 본 발명에 따른 반도체장치의 제조 공정도.4A to 4D are manufacturing process diagrams of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
31 : 실리콘기판 33 : 소자분리막31 silicon substrate 33 device isolation film
35 : 게이트산화막 37 : 게이트35: gate oxide film 37: gate
39 : 감광막 41 : 저농도영역39: photosensitive film 41: low concentration region
43, 47 : 제1 및 제2측벽 45 : 펀치-스루우 스토퍼43, 47: first and second side walls 45: punch-through stopper
49, 51 : 소오스 및 드레인영역49, 51: source and drain regions
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 비대칭 드레인(asymmetric drain) 구조를 이루어 소오스 저항을 감소시키는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an asymmetric drain structure to reduce source resistance.
반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져 내부의 전계 강도가 증가된다. 이러한 전계 강도의 증가는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜 게이트산화막으로 주입시키는 핫-캐리어 효과(hot-carrier effect)를 일으킨다. 상기 게이트산화막에 주입된 캐리어는 반도체기판과 게이트산화막의 계면에 준위를 생성시켜 드레쉬홀드전압(threshold voltage : VTH)을 변화시키거나 상호 컨덕턴스를 저하시켜 소자 특성을 저하시킨다. 그러므로, 핫-캐리어 효과에 의한 소자 특성의 저하를 감소시키기 위해 LDD(Lightly Doped Drain), 2중확산 드레인 또는 DI-LDD(Double Implant LDD) 등과 같이 드레인 구조를 변화시킨 구조를 사용하여야 한다.As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V TH ) or decreasing the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure having a changed drain structure such as a lightly doped drain (LDD), a double diffusion drain, or a double implant LDD (DI-LDD) should be used.
제1도는 종래 기술에 따른 반도체장치의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the prior art.
종래 기술에 따른 반도체장치는 P형의 반도체기판(11) 상에 선택산화방법인 LOCOS(Local Oxidation of Silicon) 등의 방법에 의해 소자의 활성영역을 한정하는 소자분리막(13)이 형성된다. 반도체기판(11)의 활성영역 상의 소정 부분에 게이트산화막(15)이 형성되고, 게이트산화막(15) 상에 게이트(17)와 고융점 금속의 실리사이드(refractory metal silicide)로 형성된 오믹접촉층(27)이 적층되어 형성된다. 게이트(17) 및 오믹접촉층(27)의 측면에 측벽(29)이 형성된다.In the semiconductor device according to the related art, an isolation layer 13 is formed on the P-type semiconductor substrate 11 to define an active region of the device by a method such as LOCOS (Local Oxidation of Silicon). A gate oxide layer 15 is formed on a predetermined portion of the active region of the semiconductor substrate 11, and an ohmic contact layer 27 formed of a gate 17 and a high melting point metal silicide on the gate oxide layer 15 is formed. ) Is laminated and formed. Sidewalls 29 are formed on the side surfaces of the gate 17 and the ohmic contact layer 27.
그리고, 게이트(17) 양측의 반도체기판(11)에 게이트(17)를 마스크로 사용하여 LDD 구조를 이루며 채널을 한정하는 N형의 불순물이 저농도로 도핑된 저농도영역(19)과, 상기 게이트(17)와 이온 주입 방지용 측벽(도시되지 않음)을 마스크로 사용하여 저농도영역(19)과 소정 부분이 중첩되게 N형의 불순물이 고농도로 도핑된 소오스 및 드레인영역(23)(24)이 형성된다. 소오스 및 드레인영역(23)(24)의 표면에도 오믹접촉층(27)이 형성된다. 그리고, 게이트(17)와 오믹접촉층(27)을 마스크로 사용하여 P형의 불순물이 고농도로 도핑된 펀치-스루우 스토퍼(punch-through stopper)로 사용되는 포켓영역(pocket resion: 25)이 형성된다. 상기 포켓영역(25)은 불순물 이온을 25~30°정도의 경사각을 갖도록 주입하여 형성되는 소오스 및 드레인영역(23)(24) 뿐만 아니라 저농도영역(19)을 에워싸도록 형성되어 펀치-스루울를 방지한다.In addition, the gate 17 is used as a mask on the semiconductor substrate 11 on both sides of the gate 17 to form an LDD structure, and the low concentration region 19 in which the N-type impurities defining the channel are lightly doped and the gate ( 17) and source and drain regions 23 and 24 doped with a high concentration of N-type impurities so as to overlap a low concentration region 19 with a predetermined portion using a sidewall (not shown) for preventing ion implantation. . An ohmic contact layer 27 is also formed on the surfaces of the source and drain regions 23 and 24. Then, using the gate 17 and the ohmic contact layer 27 as a mask, a pocket region 25 used as a punch-through stopper doped with a high concentration of P-type impurities is used. Is formed. The pocket region 25 is formed so as to surround the low concentration region 19 as well as the source and drain regions 23 and 24 formed by implanting impurity ions with an inclination angle of about 25 to 30 ° to form a punch-through. prevent.
제2도(a) 내지 (d)는 종래 기술에 따른 반도체장치의 제조공정도이다.2A to 2D are manufacturing process diagrams of a semiconductor device according to the prior art.
제2도(a)를 참조하면, P형의 반도체기판(11) 표면의 소정 부분에 통상의 선택산화방법인 LOCOS(Local Oxidation of Silicon)방법에 의해 소자분리막(13)을 형성하여 소자의 활성영역을 한정한다. 그리고, 반도체기판(11)의 활성영역 내에 산화막과 다결정실리콘을 순차적으로 증착한 후 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트산화막(15)과 게이트(17)를 형성한다. 그리고, 상기 게이트(17)를 마스크로 이용하여 반도체기판(11)에 N형의 불순물을 저농도로 이온 주입하여 LDD를 형성하기 위한 저농도영역(19)을 형성한다.Referring to FIG. 2 (a), the device isolation film 13 is formed on a predetermined portion of the surface of the P-type semiconductor substrate 11 by a local oxidation of silicon (LOCOS) method, which is a conventional selective oxidation method, to activate the device. Define the area. The oxide film and the polysilicon are sequentially deposited in the active region of the semiconductor substrate 11, and then patterned by photolithography to form the gate oxide film 15 and the gate 17. A low concentration region 19 for forming LDD is formed by ion implanting N-type impurities at low concentration into the semiconductor substrate 11 using the gate 17 as a mask.
제2도(b)를 참조하면, 게이트(17)의 측면에 이온 주입 방지용 측벽(21)을 형성한다. 상기 이온 주입 방지용 측벽(21)은 상술한 구조의 전 표면에 화학기상증착(Chemical Vapor Deposion : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 질화실리콘을 증착한 후 에치 백(etchback)하여 형성한다. 그리고, 게이트(17) 및 측벽(21)을 마스크로 사용하여 상기 N형의 불순물을 저농도영역(19)과 소정 부분 중첩되게 고농도로 이온 주입하여 소오스 및 드레인영역(23)(24)을 형성한다. 상기에서, 소오스 및 드레인영역(23)(24)을 형성할 때 저농도영역(19)을 형성할 때 보다 큰 에너지로 이온을 주입한다.Referring to FIG. 2B, an ion implantation preventing sidewall 21 is formed on the side of the gate 17. The ion implantation preventing sidewall 21 is formed by depositing silicon oxide or silicon nitride on the entire surface of the structure described above by chemical vapor deposition (hereinafter referred to as CVD). The source and drain regions 23 and 24 are formed by ion implanting the N-type impurities at a high concentration to partially overlap the low concentration region 19 using the gate 17 and the sidewall 21 as a mask. . In the above, when the source and drain regions 23 and 24 are formed, ions are implanted with greater energy than when the low concentration region 19 is formed.
제2도(c)를 참조하면, 게이트(17)와 소오스 및 드레인영역(23)(24)의 표면에 금속 실리사이드로 이루어진 오믹접촉층(27)을 형성한다. 상기 오믹접촉층(27)은 상술한 구조의 표면에 티타늄(Ti) 또는 텅스텐(W) 등의 고융점 금속을 CVD 방법으로 증착하고 실리콘과 반응하도록 열처리하므로써 형성된다. 이 때, 상기 고융점 금속은 소자분리막(13) 및 측벽(21)을 이루는 절연물질과 반응되지 않고 잔류하게 된다. 그러므로, 소자분리막(13) 및 측벽(21) 상에 잔류하는 고융점 금속을 제거한다. 그리고, 측벽(21)을 제거하여 저농도영역(19)을 노출시킨다.Referring to FIG. 2C, an ohmic contact layer 27 made of metal silicide is formed on the surfaces of the gate 17 and the source and drain regions 23 and 24. The ohmic contact layer 27 is formed by depositing a high melting point metal such as titanium (Ti) or tungsten (W) on the surface of the structure described above by a CVD method and performing heat treatment to react with silicon. At this time, the high melting point metal remains without reacting with the insulating material forming the device isolation layer 13 and the sidewall 21. Therefore, the high melting point metal remaining on the device isolation film 13 and the sidewall 21 is removed. The sidewalls 21 are removed to expose the low concentration region 19.
제2도(d)를 참조하면, 오믹접촉층(27)과 게이트(17)를 마스크로 사용하여 P형의 불순물을 25~30°정도의 경사각을 갖도록 고농도로 이온 주입하여 저농도영역(19)을 에워 싸는 포켓영역(25)을 형성한다. 그 다음, 게이트(17) 및 오믹접촉층(27)의 측면에 게이트(17)와 소오스 및 드레인영역(23)(24) 사이가 단락되는 것을 방지하는 측벽(29)을 형성한다.Referring to FIG. 2 (d), the low concentration region 19 is formed by ion implanting P-type impurities at a high concentration so as to have an inclination angle of about 25 to 30 ° using the ohmic contact layer 27 and the gate 17 as a mask. A pocket area 25 enclosing is formed. Next, sidewalls 29 are formed on the side surfaces of the gate 17 and the ohmic contact layer 27 to prevent a short between the gate 17 and the source and drain regions 23 and 24.
상술한 종래의 반도체장치는 소오스 및 드레인영역, 저농도영역 및 포켓영역은 서로 N+/N-, N-/P+ 및 N+/P+ 접합면을 이루므로 드레인영역에 전압이 인가되면 전계가 상기 접합면들에 분산되므로 단 채널 효과에 의한 소오스영역과 드레인영역 사이의 펀치스루우를 방지할 수 있다.In the conventional semiconductor device described above, the source and drain regions, the low concentration region, and the pocket region form N + / N-, N- / P +, and N + / P + junction surfaces. Since it is dispersed in, the punch-through between the source region and the drain region due to the short channel effect can be prevented.
그러나, 상술한 반도체장치는 저농도영역이 드레인영역 뿐만 아니라 소오스영역에도 형성되므로 소오스 저항이 증가되어 전류 구동 능력이 저하되는 문제점이 있었다. 또한, 펀치-스루우 스토퍼로 사용되는 포켓영역이 저농도영역을 에워싸므로 채널 저항 및 접합 용량이 증가될 뿐만 아니라 경사각을 갖고 도핑되어야 하므로 최적 조건으로 도핑하기 어려운 문제점이 있었다.However, the semiconductor device described above has a problem in that the low concentration region is formed not only in the drain region but also in the source region, so that the source resistance is increased and the current driving capability is reduced. In addition, since the pocket area used as the punch-through stopper surrounds the low concentration area, the channel resistance and the junction capacity not only increase, but also have to be doped with an inclination angle, which makes it difficult to dope the optimum condition.
따라서, 본 발명의 목적은 소오스 저항을 감소시켜 전류 구동 능력을 향상시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve current driving capability by reducing source resistance.
본 발명의 다른 목적은 채널 저항 및 접합 용량을 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing channel resistance and junction capacitance.
본 발명의 또 다른 목적은 펀치-스루우 스토퍼를 저농도영역의 하부에 형성하므로 이온 주입 공정이 용이한 반도체장치의 제조방법을 제공함에 있다.It is still another object of the present invention to provide a method of manufacturing a semiconductor device in which a punch-through stopper is formed under a low concentration region, and thus an ion implantation process is easy.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 제1도 전형의 반도체기판 상의 소정 부분에 소자의 활성영역을 한정하는 소자분리막을 형성하고 상기 활성영역 상의 소정 부분에 게이트산화막 및 게이트를 형성하는 공정과, 상기 게이트의 일측 측면을 포함하는 반도체기판의 소정 부분이 노출되게 감광막을 형성하는 공정과, 상기 게이트와 감광막을 마스크로 사용하여 반도체기판의 노출된 부분에 제2도전형의 불순물을 수직 방향으로 도핑하여 저농도영역을 형성하는 공정과, 상기 게이트의 상기 감광막이 형성되지 않아 노출된 일측 측면에 제1측벽을 형성하는 공정과, 상기 감광막, 게이트 및 제1측벽을 마스크로 사용하여 상기 저농도영역의 하부에 제1도전형의 펀치-스루우 스토퍼를 형성하는 공정과, 상기 제1측벽의 측면에 제2측벽을 형성하는 공정과, 상기 감광막을 제거하고 게이트와 제1 및 제2측벽을 마스크로 사용하여 상기 반도체기판에 제2도전형의 불순물을 고농도로 도핑하여 소오스 및 드레인영역을 형성하는 공정을 구비한다.In the semiconductor device manufacturing method according to the present invention for achieving the above object is formed a device isolation film to define the active region of the device in a predetermined portion on the semiconductor substrate of the first conductive type and the gate oxide film and the gate in the predetermined portion on the active region Forming a photoresist film so as to expose a predetermined portion of the semiconductor substrate including one side surface of the gate; and forming a photosensitive film on the exposed portion of the semiconductor substrate using the gate and the photoresist film as a mask. Forming a low concentration region by doping impurities in a vertical direction; forming a first sidewall on one side surface of the gate where the photosensitive film is not formed; and using the photosensitive film, the gate, and the first side wall as a mask. Forming a punch-through stopper of a first conductivity type in a lower portion of the low concentration region; and a side surface of the first side wall. Forming a second sidewall in the semiconductor substrate; and removing the photosensitive film, and using a gate and the first and second sidewalls as masks, doping a second conductive type impurity on the semiconductor substrate to form a source and a drain region. Process.
본 발명에 따른 반도체장치의 제조방법은 상기 저농도영역 형성 후 상기 감광막, 게이트 및 측벽을 마스크로 사용하여 상기 저농도영역의 하부에 제1도전형의 펀치-스루우 스토퍼를 형성하는 공정과, 상기 측벽의 측면에 다른 측벽을 형성하는 공정을 더 구비한다.In the method of manufacturing a semiconductor device according to the present invention, after forming the low concentration region, using the photoresist film, the gate, and the sidewall as a mask, forming a punch-through stopper of a first conductivity type in the lower concentration region; It further includes the step of forming another side wall on the side.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 반도체장치의 단면도이다.3 is a cross-sectional view of a semiconductor device according to the present invention.
본 발명에 따른 반도체장치는 P형의 반도체기판(31) 상의 소정 부분에 활성영역을 한정하는 소자분리막(33)이 형성된다. 상기 반도체기판(31)은 N형의 기판에 형성된 P형의 웰영역일 수도 있다. 그리고, 활성영역 내의 소정 부분 상에 게이트산화막(35)이 형성되고, 이 게이트산화막(35) 상에 게이트(37)가 형성된다.In the semiconductor device according to the present invention, an element isolation film 33 defining an active region is formed in a predetermined portion on a P-type semiconductor substrate 31. The semiconductor substrate 31 may be a P type well region formed on an N type substrate. A gate oxide film 35 is formed on a predetermined portion of the active region, and a gate 37 is formed on the gate oxide film 35.
게이트(37)의 일측 측면에 제1 및 제2측벽(43)(47)이 연속해서 형성된다. 상기 제1 및 제2측벽(43)(47)은 SiO, SiN 또는 TEOS(Tetra-Ethyl-Ortho-Silicate) 등으로 형성된다. 그리고, 게이트(37) 일측의 반도체기판(31)에 제1 및 제2측벽(43)(47)과 중첩되는 N형의 저농도영역(41)이 형성된다. 저농도영역(41)은 LDD 구조를 이루는 것으로 인(P) 또는 아세닉(As) 등의 N형의 불순물이 1×1013~3×1013/cm2정도의 농도와 30~50KeV 정도의 에너지로 도핑되어 형성된다. 또한, 반도체기판(31)의 저농도영역(41) 하부에 제2측벽(47)과 중첩되는 P형의 펀치-스루우 스토퍼(45)가 형성된다. 펀치-스루우 스토퍼(45)는 보론(B) 등의 P형 분순물이 1×1013~3×1013/cm2정도의 농도와 40~60KeV 정도의 에너지로 도핑되어 형성된다.First and second side walls 43 and 47 are continuously formed on one side surface of the gate 37. The first and second side walls 43 and 47 are formed of SiO, SiN, or Tetra-Ethyl-Ortho-Silicate (TEOS). An N-type low concentration region 41 overlapping the first and second side walls 43 and 47 is formed on the semiconductor substrate 31 on one side of the gate 37. The low concentration region 41 forms an LDD structure in which N-type impurities such as phosphorus (P) or asic (As) have a concentration of about 1 × 10 13 to 3 × 10 13 / cm 2 and energy of about 30 to 50 KeV. Is doped with. Further, a P-type punch-through stopper 45 overlapping the second side wall 47 is formed under the low concentration region 41 of the semiconductor substrate 31. The punch-through stopper 45 is formed by doping P-type impurities such as boron (B) at a concentration of about 1 × 10 13 to 3 × 10 13 / cm 2 and energy of about 40 to 60 KeV.
반도체기판(31)에 게이트(37)와 제1 및 제2측벽(43)(47)을 마스크로 사용하여 불순물이 고농도로 도핑된 소오스 및 드레인영역(49)(51)이 형성된다. 소오스 및 드레인영역(49)(51)은 인(P) 또는 아세닉(As) 등의 N형의 불순물이 1×1015~5×1015/cm2정도의 농도와 40~60KeV 정도의 에너지로 도핑되어 형성된다. 상기에서, 소오스영역(49)은 반도체기판(31)의 게이트(37) 타측에 형성되며, 드레인영역(51)은 게이트(37) 일측에 저농도영역(41) 및 펀치-스루우 스토퍼(45)와 접합을 이루며 형성된다. 상기에서 펀치-스루우 스토퍼(45)는 소오스영역(49)과 드레인영역(51) 사이의 펀치-스루우를 방지하는 것으로 저농도영역(41) 하부에만 형성되므로 채널 저항 및 접합 용량이 감소된다. 또한, 저농도영역(41)이 소오스영역(49)에 형성되지 않고 드레인영역(51)에만 형성되므로 소오스저항이 감소되어 전류 구동 능력이 향상된다.Source and drain regions 49 and 51 doped with a high concentration of impurities are formed on the semiconductor substrate 31 using the gate 37 and the first and second side walls 43 and 47 as masks. The source and drain regions 49 and 51 have an N-type impurity such as phosphorus (P) or asic (As) and have a concentration of about 1 × 10 15 to 5 × 10 15 / cm 2 and an energy of about 40 to 60 KeV. Is doped with. The source region 49 is formed at the other side of the gate 37 of the semiconductor substrate 31, and the drain region 51 is formed at the low concentration region 41 and the punch-through stopper 45 at one side of the gate 37. It is formed in conjunction with. In this case, the punch-through stopper 45 prevents punch-through between the source region 49 and the drain region 51 so that the punch-through stopper 45 is formed only in the lower concentration region 41, thereby reducing channel resistance and junction capacitance. In addition, since the low concentration region 41 is not formed in the source region 49 but only in the drain region 51, the source resistance is reduced to improve the current driving capability.
제4도(a) 내지 (d)는 본 발명에 따른 반도체장치의 제조 공정도이다.4A to 4D are manufacturing process diagrams of a semiconductor device according to the present invention.
제4도(a)를 참조하면, P형 반도체기판(31) 표면의 소정 부분을 통상의 선택산화방법인 LOCOS 방법에 의해 소자분리막(33)을 형성하여 소자의 활성영역을 한정한다. 그리고, 반도체기판(31)의 소자분리막(33)이 형성되지 않은 활성영역의 표면을 열산화하여 게이트산화막(35)을 형성하고, 이 게이트산화막(35) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착하고 포토리쏘그래피 방법으로 패터닝하여 게이트(37)를 형성한다. 그리고, 상술한 구조의 전 표면에 감광막(39)을 도포한 후 노광 및 현상하여 게이트(37) 일측의 측면을 포함하는 반도체기판(31)을 노출시킨다. 그리고, 감광막(39)과 게이트(37)를 마스크로 사용하여 반도체기판(31)의 노출된 부분에 인 또는 아세닉 등의 N형 불순물을 1×1013~3×1013/cm2정도의 농도와 30~50KeV 정도의 에너지로 수직 방향으로 도핑하여 LDD 구조를 이루는 저농도영역(41)을 형성한다.Referring to FIG. 4A, a device isolation film 33 is formed by a LOCOS method, which is a conventional selective oxidation method, to define a portion of the surface of the P-type semiconductor substrate 31 to define an active region of the device. In addition, the gate oxide layer 35 is formed by thermally oxidizing the surface of the active region in which the device isolation layer 33 of the semiconductor substrate 31 is not formed, and CVD polycrystalline silicon doped with impurities on the gate oxide layer 35. The gate 37 is formed by deposition in a method and patterning by a photolithography method. Then, the photosensitive film 39 is applied to the entire surface of the above-described structure, and then exposed and developed to expose the semiconductor substrate 31 including the side surface of one side of the gate 37. Then, using the photoresist film 39 and the gate 37 as a mask, N-type impurities such as phosphorous or arsenic are deposited on the exposed portions of the semiconductor substrate 31 at a size of about 1 × 10 13 to 3 × 10 13 / cm 2 . Doping in a vertical direction with a concentration and energy of about 30 to 50 KeV forms a low concentration region 41 forming an LDD structure.
제4도(b)를 참조하면, 감광막(39)이 형성되지 않고 노출된 부분에 TEOS를 CVD방법으로 증착한다. 이 때, TEOS는 감광막(39) 상에 증착되지 않는다. 그리고, TEOS를 반응성 이온 식각(Reactive Ion Etching : 이하, RIE라 칭함) 등의 비등방성 식각 방법으로 에치 백(etch back)하여 게이트(37)의 노출된 일측 측면에 500~1500Å 정도 두께의 제1측벽(43)을 형성한다. 게이트(37)와 제1측벽(43)을 마스크로 사용하여 보론(B) 등의 P형 불순물을 1×1013~3×1013/cm2정도의 농도와 40~60KeV 정도의 에너지로 수직 방향으로 도핑하여 저농도영역(41)의 하부에 펀치-스루우 스토퍼(45)를 형성한다. 이 때, 제1측벽(43)과 중첩되는 부분에는 불순물이 도핑되지 않으므로 펀치-스루우 스토퍼(45)가 형성되지 않는다. 상기에서 펀치-스루우 스토퍼(45)를 형성하기 위해 불순물 이온을 수직 방향으로 도핑하므로 도핑 조건의 최적화하기 용이하다.Referring to FIG. 4 (b), TEOS is deposited on the exposed portion without the photosensitive film 39 being formed by CVD. At this time, TEOS is not deposited on the photosensitive film 39. Then, the TEOS is etched back by an anisotropic etching method such as reactive ion etching (hereinafter referred to as RIE) and has a thickness of about 500 to 1500 Å on the exposed side of the gate 37. The side wall 43 is formed. Using the gate 37 and the first side wall 43 as a mask, P-type impurities such as boron (B) are perpendicular to a concentration of about 1 × 10 13 to 3 × 10 13 / cm 2 and energy of about 40 to 60 KeV. Doping in the direction to form a punch-through stopper 45 under the low concentration region 41. At this time, since the impurity is not doped in the portion overlapping with the first side wall 43, the punch-through stopper 45 is not formed. Since the impurity ions are doped in the vertical direction to form the punch-through stopper 45 in the above, it is easy to optimize the doping conditions.
제4도(c)를 참조하면, 제1측벽(43)을 형성하는 동일한 물질 및 방법으로 제1측벽(43)의 측면에 제2측벽(47)을 형성한다. 즉, 감광막(39)이 형성되지 않고 노출된 부분에 TEOS를 CVD 방법으로 증착하고 RIE 등의 비등방성 식각 방법으로 에치 백하여 제1측벽(43)의 측면에 500~1500Å 정도 두께의 제2측벽(47)을 형성한다.Referring to FIG. 4C, the second side wall 47 is formed on the side of the first side wall 43 by the same material and the method of forming the first side wall 43. That is, TEOS is deposited on the exposed portion without forming the photoresist film 39 by CVD method and etched back by anisotropic etching method such as RIE, so that the second side wall having a thickness of about 500-1500 mm on the side of the first side wall 43 is formed. Form 47.
제4도(d)를 참조하면, 감광막(39)을 제거한다. 그리고, 게이트(37)와 제1 및 제2측벽(43)(47)을 마스크로 사용하여 반도체기판(31)에 인(P) 또는 아세닉(As) 등의 N형의 불순물을 고농도로 도핑하여 소오스 및 드레인영역(49)(51)을 형성한다. 상기에서, 소오스 및 드레인영역(49)(51)은 1×1015~5×1015/cm2정도의 농도와 40~60KeV 정도의 에너지로 도핑하여 형성되는데, 반도체기판(31)의 게이트(37) 일측에 저농도영역(41) 및 펀치-스루우 스토퍼(45)와 접합을 이루도록 형성되는 것이 드레인영역(51)이며, 게이트(37) 타측에 형성되는 것이 소오스영역(49)이 된다.Referring to FIG. 4D, the photosensitive film 39 is removed. Then, using the gate 37 and the first and second side walls 43 and 47 as a mask, the semiconductor substrate 31 is doped with an N-type impurity such as phosphorus (P) or arsenic (As) at a high concentration. The source and drain regions 49 and 51 are formed. The source and drain regions 49 and 51 are formed by doping with a concentration of about 1 × 10 15 to 5 × 10 15 / cm 2 and an energy of about 40 to 60 KeV. 37) The drain region 51 is formed at one side to be in contact with the low concentration region 41 and the punch-through stopper 45, and the source region 49 is formed at the other side of the gate 37.
상술한 바와 같이 본 발명에 따른 반도체장치는 게이트 일측의 반도체기판에 게이트의 일측 측면에 형성되는 제1측벽과 타측에 형성되는 감광막을 마스크로 사용하여 도핑된 LDD 구조를 이루기 위한 저농도영역과 이 저농도영역의 하부에 제1측벽의 측면에 형성된 제2측벽과 감광막을 마스크로 사용하여 도핑된 펀치-스루우 스토퍼가 드레인영역과 접합을 이루며 형성된다.As described above, the semiconductor device according to the present invention has a low concentration region and a low concentration region for forming a doped LDD structure using a first side wall formed on one side of the gate and a photosensitive film formed on the other side as a mask on a semiconductor substrate on one side of the gate A doped punch-through stopper is formed in contact with the drain region using the second side wall formed on the side of the first side wall and the photosensitive film as a mask under the region.
따라서, LDD 구조를 이루는 저농도영역과 펀치-스루우 스토퍼가 드레인영역에만 형성되므로 소오스저항이 감소되어 전류 구동 능력이 향상되며, 펀치-스루우 스토퍼가 수직 도핑에 의해 저농도영역을 에워싸지 않고 하부에 형성되므로 채널 저항 및 접합 용량이 감소될 뿐만 아니라 도핑이 용이한 잇점이 있다.Therefore, since the low concentration region and the punch-through stopper forming the LDD structure are formed only in the drain region, the source resistance is reduced and the current driving capability is improved, and the punch-through stopper does not surround the low concentration region by the vertical doping. The formation not only reduces channel resistance and junction capacity, but also facilitates doping.
상기에서 본 발명의 실시예를 P형의 반도체기판에 형성된 N모스트랜지스터로 설명하였으나, 본 발명의 다른 실시예로서 N형의 반도체기판에 형성된 P모스트랜지스터도 가능하다.Although the embodiment of the present invention has been described as an N MOS transistor formed on a P-type semiconductor substrate, as another embodiment of the present invention, a P MOS transistor formed on an N-type semiconductor substrate is also possible.
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