JPS61241967A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To implement a high speed in operation, by providing a semiconductor region at the lower part of a source or drain region and the junction part of a semiconductor substrate or a well region so that the junction part constitutes a low-impurity-concentration p-n junction part. CONSTITUTION:An MISFET having an LDD structure provided with a semiconductor region 8 is formed in a semiconductor integrated circuit device. A semiconductor region 12 is provided at the lower part of a source or drain region (semiconductor region 10) in said circuit device. Thus the extension of a depletion region at a p-n junction in a well region 2 can be made large. Therefore, junction capacity added to the MISFET can be reduced. A semiconductor region 11 having a reverse conducting type is formed in an MISFET having an LDD structure in the semiconductor integrated circuit device. In this device, the semiconductor region 12 is provided at the lower part of the source or drain region (semiconductor region 10). Therefore, the extension of the depletion region at the p-n junction with the semiconductor region 11 can be made large. Thus, the junction capacity added to the MISFET can be decreased. In this way, the speed of the semiconductor integrated circuit device is made high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a MISFET.

[Background technology] In semiconductor integrated circuit devices, which are trending toward higher integration, M
ISFET reduces the electric field strength near the drain region,
It is necessary to suppress fluctuations in threshold voltage (vth) due to the generation of hot carriers. Therefore, in order to reduce the electric field strength near the drain region, L D D (Lig
An n-channel MISFET with a doped drain structure has been proposed. In this structure, a semiconductor region (LDD region) is provided between the drain region and the channel forming region, which is of the same conductivity type as the drain region, is electrically connected, and has a lower impurity concentration than the drain region. This LD
The D portion makes the impurity concentration gradient between the drain region and the channel forming region gentle.

Furthermore, since the impurity concentration in the LDD portion is lower than that in the drain region, the impurity concentration in the LDD portion is small, so that it is suitable for shortening the channel.

However, as higher integration progresses and the channel length becomes approximately 0.8 [μm] or less, punch-through is likely to occur between the source region and the drain region due to the coupling of the respective depletion regions.

Therefore, in an LDD structure MISFET, in order to form a pn junction with a high impurity concentration with the source or drain region, a semiconductor region of the opposite conductivity type (p' type) is
It has been proposed to provide it along the DD section. This suppresses the extension of the depletion region formed from the source region or the drain region to the channel formation region, thereby suppressing the occurrence of punch-through.

However, as a result of studies on this technology, the present inventor found that providing a semiconductor region of one opposite conductivity type increases the parasitic capacitance added to the source region or drain region. Semiconductor regions of opposite conductivity type are
It is necessary to prevent variations in the electrical characteristics of the LDD portion, such as variations in threshold voltage and deterioration of pn junction breakdown voltage in the channel forming region. Therefore, in the semiconductor region of the opposite conductivity type, the maximum impurity concentration portion is provided in a portion deeper than the source region and the drain region, so that a pn junction with a high impurity concentration is formed along the lower part of the source region or the drain region. Resulting in.

Due to the increase in the parasitic capacitance added to the M I S FET, a problem arises in that the semiconductor integrated circuit device cannot increase its operating speed.

In addition, a p type semiconductor region is provided along the LDD part.
INPLANTED LDp)” p718-P721
It is described in.

[Object of the Invention] An object of the present invention is to provide a technique that can increase the operating speed of a semiconductor integrated circuit device including a MISFET.

Another object of the present invention is to provide a technique that can increase the operating speed and improve the degree of integration in a semiconductor integrated circuit device equipped with an MI S FET.

Another object of the present invention is to provide a technology capable of increasing the operating speed and increasing the capacity in a semiconductor integrated circuit device having a memory function in which memory cells are configured with MISFETs. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device having an LDD end fabricated MZS FET, at the junction between the lower part of the source region or drain region and the semiconductor substrate or well region,
Semiconductor regions are provided such that they constitute a pn junction with a low impurity concentration.

This makes it possible to reduce the parasitic capacitance added to the MISFET, thereby increasing the operating speed of the semiconductor integrated circuit device.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

[Embodiment] Embodiment I describes the present invention in a semiconductor integrated circuit device (hereinafter referred to as SRAM) equipped with a static random access memory.
This section describes an example in which the method is applied to

FIG. 1 shows an SRAM for explaining Embodiment I of the present invention.
FIG. 2 is an equivalent circuit diagram showing a memory cell of FIG.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, word lines WL extend in one row direction, and a plurality of word lines are provided in the column direction (hereinafter, the direction in which the word lines extend will be referred to as the row direction).

The word line WL is for controlling a switch MISFET which will be described later.

DL and DL are data lines extending in the column direction.

A plurality of data lines are provided in the row direction (hereinafter, the direction in which the data lines extend is referred to as the column direction). The data lines DL and OL are for transmitting charges serving as information between a memory cell and a write circuit or a read circuit, which will be described later.

Ql=Q2 is an M I S FET, and one end is connected to the power supply voltage wiring Vcc (for example, 5
．． 0 [Vl'), the other (7) M I S F E
TQ2.

It is connected to the gate electrode of Q+ and the switch MISFET, and the other end is connected to the reference voltage wiring Vss (for example.

0 [Vl).

R1 and R2 are resistance elements. These resistance elements R1, R2
controls the amount of current flowing from the power supply voltage wiring Vcc,
It is configured to stably hold written information.

A flip-flop circuit having a pair of input and output terminals has two
M I S F E TQ I-Qn and resistance element R
+ and R2. This flip-flop circuit is configured to store information of "111%0"° transmitted from the data lines DL, DL.

Q3t and Qsz are switching M I S FETs, one end of which is connected to the data lines DL and DL, and the other end connected to a pair of input/output terminals of the flip-flop circuit. The switching MISFETs Qs+ and Qs2 are controlled by the word line WL and are configured to perform a switching function between the flip-flop circuit and the data lines DL and DL.

C is an information storage capacitance (parasitic capacitance), which is mainly added to the gate electrode of one MISFETQs (or Q2) and one semiconductor region (source region or drain region) of the other MISFETQ2 (or Qn). has been done. This information storage capacitor C is configured to store charges that serve as information in the memory cell.

An SRAM memory cell consists of a flip-flop circuit having a pair of input/output terminals, a MISFET Qs system for switching,
Qsx.

The memory cell includes a word line WL, a data line DL,
A plurality of them are arranged at predetermined intersections with [)L, and constitute a memory cell array.

Next, the specific configuration of this embodiment will be explained.

FIG. 2 shows an SRAM for explaining Embodiment 1 of the present invention.
The main part plan views showing the memory cell of FIGS. 3 to 5 are as follows.
FIG. 6 is a sectional view taken along the line Vl--Vl in FIG. 2, and FIG. 7 is a plan view of the main parts of the memory cell shown in FIG. I
S F E T Q s The enlarged main part sectional view of the s portion, FIG. 8, is the M I S F E T shown in FIG. 7.
FIG. 3 is a diagram showing an impurity concentration distribution of a source region or a drain region of Q s I.

Note that, in the plan views shown in FIGS. 2 to 5, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure of this embodiment easier to understand.

In FIGS. 2 and 8, 1 is single crystal silicon.

This is an n-type semiconductor substrate consisting of a semiconductor substrate. This semiconductor substrate 1 is for configuring an SRAM.

Reference numeral 2 denotes a P-type well region, which is provided on a predetermined main surface portion of the semiconductor substrate 1. This well region 2 is for configuring a complementary MISFET. The well region 2 is 1, for example, 10" as shown by the reference numeral 2 in FIG.
' The impurity concentration is about [ajons/cm3].

A field insulating film 3 is provided on the main surface of the semiconductor substrate 1 and the well region 2 between the semiconductor element forming regions. This field insulating film 3.

It is configured to electrically isolate semiconductor elements.

M I S FETQs, Q constituting the memory cell
2 and switch MI 5FETQst, QB2 are:
It is surrounded and defined by a field insulating film 3. Then, MISFET Q2 and switch MI
S F E T Q s 2 is integrally defined by the field insulating film 3 for cross-coupling. M I S F E T Q t and M for switch
I S F E T Q st means the above M I S
F E T Q * and M I S F E for switch
It is separated and defined by field insulation 1113 at a position intersecting with T Q a 2. MI5
FET Qi and switch Mi S F E T Q s
t is designed to be cross-coupled by a conductive layer provided on the top of the field insulating film 3.

Reference numeral 4 designates a P-type channel stopper region, which is provided on the main surface of the well region 2 under the field insulating film 3 to prevent parasitic MISFETs and further electrically isolate semiconductor elements. is configured to do so.

Reference numeral 5 denotes an insulating film, which is provided on the upper main surface of the semiconductor substrate l and the well region 2, which serve as semiconductor element formation regions. This insulating film 5 is mainly used to constitute a gate insulating film of the MISFET.

Reference numeral 6 denotes a connection hole, which is provided by removing a predetermined portion of the insulating film 5. This connection hole 6 is connected to a semiconductor element (semiconductor region).
and a wiring (a conductive layer used as a mask for impurity introduction to form a semiconductor region) are electrically connected to each other.

Conductive layers 7A to 7D are provided extending over a predetermined upper portion of the field insulating film 3 or the insulating film 5.

The conductive layer 7A is a switch M I S F E T Q
It is provided above the insulating film 5 in the s1-QB2 formation region, and is provided extending above the field insulating film 3 in the row direction. This conductive layer 7A is MI 5FE for switch.
The TQss and QS2 forming regions constitute a gate electrode, and the other portions constitute a word mWL.

The conductive layer 7B is provided so as to be electrically connected to one semiconductor region of the MI 5FETQs, Q2 constituting the flip-flop circuit through the connection hole 6, and similarly to the conductive layer 7A, the conductive layer 7B extends over the field insulating film 3 in the row direction. It is located extending to. This conductive layer 7B constitutes a reference voltage wiring Vss connected to one semiconductor region of each of a plurality of memory cells arranged in one row direction.

The conductive layer 7C has one end electrically connected to the semiconductor region of the switch MISFETQsI through the connection hole 6, and the other end connected to the field insulation [3 and one MTSF Insulating film 5 in E T Q x formation region
the other M I S F through the connecting hole 6.
It is provided so as to be electrically connected to the semiconductor region of the ETQ. This conductive layer 7C has M I on top of the insulating film 5.
constitutes a gate electrode of S F E T Q 2, and
The switch MISFET Qst is configured to cross-couple with the other MISFET QI.

The conductive layer 7D has one end electrically connected to the semiconductor region of the switch MISFET Qs 2 through the connection hole 6, and the other end connected to the field insulating film 3 and the other MISFET Qt formation region. It is provided so as to extend above the insulating film 5. This conductive layer 7D constitutes a gate electrode of M T S F E T Q I above the insulating film 5. MI S F E for switch
Since T Q s 2 and M I S F E T Q 2 integrally constitute a semiconductor region as described above, there is no need for cross-coupling with this conductive layer.

In addition, M I S F E T Q $ 2 for the switch
and MISFE TQ 2 means MIS for switch.
Similar to the cross-coupling of FETQst and MI 5FETQ+, the conductive layer 7D may be formed into a predetermined shape for cross-coupling.

The conductive layers 7A to 7D are made of polycide (MoSiz p TiSi2.
iz, WSi2/polysi) film.

Further, the conductive layers 7A to 7D are made of the following conductive materials:
Polycrystalline silicon film, silicide (MOSi2 tTiS
i2. TaSi2. WSiz) film, high melting point metal (Mo
It may also be composed of a r T x r Ta * W ) film or the like.

The conductive layers 7A to 7D are formed by a first conductive layer forming step in the manufacturing process. '8 is an i-type semiconductor region (LDD section), and MISFETQs+ for switch
, Qs2. Conductive layers 7A and 7G which become MISFETQt and Q2 formation regions.

They are provided on the main surface of the well region 2 on both sides of the well region 7D (between the source region or drain region and the channel forming region). This semiconductor region 8 constitutes an LDD structure.

This semiconductor region 8 has a lower impurity concentration than a semiconductor region that becomes a substantial source region or drain region, which will be described later. As a result, the electric field strength at the pn junction between the semiconductor region 8 and the well region 2 can be relaxed, so that the pn junction breakdown voltage (source or drain breakdown voltage) of the MI S FET can be improved.

Furthermore, since the semiconductor region 8 can be formed with a shallow junction depth xj), it is possible to reduce the wraparound to the lower part of the gate electrode (channel formation region). Thereby, short channel effects can be suppressed.

The semiconductor region 8 mainly includes conductive layers 7A, fc.

Since conductive layer (gate electrode) 7A,
Constructed with self-alignment for 7G and 7D. The semiconductor region 8 is 1, for example, 10" as shown by reference numeral 8 in FIG.
[With an impurity concentration of about atoms/am31, the junction depth is about 2.0 [μm], and the maximum impurity concentration part is 0.
．． It is configured to have a depth of about 1 [μm].

Reference numeral 9 denotes a mask for impurity introduction, which is provided on both sides of the conductive layers 7A to 7D in self-alignment with them. This impurity introduction mask 9 is used to constitute a substantial source region or drain region, and is mainly adapted to constitute an LDD structure. Note that the impurity introduction mask 9 is removed after forming an n-type semiconductor region, which will be described later, and does not need to be present when the SRAM is completed.

10 is an n-type semiconductor region, and is a conductive layer 7A.

Connection holes 6 on the main surface of well region 2 through insulating film 5 on both sides of 7G and 7D, or on the lower part of conductive layers 7B, 7C, and 7D
It is provided on the main surface of the well region 2 in the section. This semiconductor region 10 constitutes a substantial source region or drain region of a MISFET, or a cross-coupling wiring of a flip-flop circuit.

The semiconductor region IO includes conductive layers (gate electrodes) 7A to 7D.
Since impurities are introduced by ion implantation using the impurity introduction mask 9, the conductive layers 7A to 7D are self-aligned with the impurity introduction mask 9 and the conductive layers 7A to 7D. The semiconductor region IO is.

For example, as shown by reference numeral 10 in FIG.
The junction depth is configured to be approximately 0.2 [μm] at an impurity concentration of approximately 0.2 [μm].

Reference numeral 11 denotes a p0 type (hereinafter referred to as such since the concentration is higher than that of the well region 2) semiconductor region, which is in contact with the semiconductor region 10 on the main surface of the well region 2 along the lower part of a predetermined semiconductor region 10. It is provided. Semiconductor region 11
are the impurity introduction mask 9 or the conductive layers 7A to 7D.
consists of self-alignment.

For example, the semiconductor region 11 has a surface impurity concentration of 10" [atoms/CI
It is composed of about l'1. The semiconductor region 11 is configured to have a maximum impurity concentration of approximately 0.4 to 0.5 [μm] in depth, for example.

The semiconductor region 11 provided on the side of the channel formation region is called a P pocket, and the pn junction between the semiconductor region (source region or drain region) 10 and the well region 2 is formed into a pn junction with a high impurity concentration. are doing. That is,
Since the extension of the depletion region formed on the channel forming region side can be suppressed, punch-through between the semiconductor regions 10 due to the bonding of the depletion regions can be suppressed. As a result, the short channel effect can be prevented and the channel length can be shortened, so that the area occupied by the MISFET can be reduced.

In addition, the semiconductor region 11 is particularly arranged in the lower part of the semiconductor region 10 of the MI5FETQs and Q2 of the flip-flop circuit, the lower part of the semiconductor region 10 of one of the switch MISFETQst and Q82, that is, the amount of charge accumulated as information in the memory cell. It is provided in a part that contributes to increasing the The semiconductor region 11 can form a pn junction with a higher impurity concentration than the pn junction between the well region 2 and the semiconductor region 10, increasing the junction capacitance and accumulating charges that serve as information in the information storage capacitor C. The amount can be increased. This makes it possible to prevent soft errors caused by alpha (hereinafter referred to as α) rays.

In addition, since the semiconductor region 11 is configured with a higher impurity concentration than the well region 2, it is possible to enhance the barrier effect of suppressing unnecessary invasion of minority carriers generated by α rays, and as described above, soft error can be prevented. Therefore, in the SRAM memory cell,
There are semiconductor regions 11 that are not canceled or reversed by semiconductor regions 12 (described below).

12 is an n-type semiconductor region, and one semiconductor region 10 of MI 5FETQ+-Q2 is connected to the conductive layer 7B.
It is provided at the pn junction between the lower part of the semiconductor region 10 and the semiconductor region 11 of the MISFET Qst y Qlsa. That is, the semiconductor region 12 is the same as the semiconductor region 1.
0 and the semiconductor region 11 to avoid an increase in the parasitic capacitance added to the pn junction.

The semiconductor region 12 cancels out the semiconductor region 11 under the predetermined semiconductor region 10 or reduces its impurity concentration (makes the semiconductor region 11 n p n-# P or p- type),
It is configured to increase the extension of the depletion region extending from the semiconductor region 10 to the semiconductor region 11. This makes it possible to reduce the increase in junction capacitance added to the semiconductor region 10.

MI 5FETQj, Qs provided with semiconductor region 12.

Qs I+ Qs2 can increase its operating speed.

The semiconductor region 12 is formed, for example, as shown by reference numeral 12 in FIG. It is desirable that the semiconductor region 12 has a parasitic capacitance value added to the pn junction between the semiconductor region 10 and the semiconductor region 11 equal to or less than that between the semiconductor region 10 and the well region 2. .The semiconductor region 12 is
It is provided in the lower part of the semiconductor region 10 other than the region surrounded by the dotted line indicated by the reference numeral 12 in FIGS. 2 and 5.

M I S F E T Q s Iy Q for switch
s2 is mainly the well region 2.s2. Insulating film5. A conductive layer 7A, a pair of semiconductor regions 8, a pair of semiconductor regions 10.
It is composed of a semiconductor region 11 and a semiconductor region 12.

M I S F E T Q r mainly includes a well region 2°, an insulating film 5, a conductive layer 7D, a pair of semiconductor regions 8,
A pair of semiconductor regions 10. Semiconductor region 11 and conductive layer 7B
It is constituted by a semiconductor region 12 provided under a semiconductor region 10 connected to the semiconductor region 10.

M I S F E T Q 2 mainly consists of a well region 2, an insulating film 5. conductive layer 7C1 pair of semiconductor regions 8;
A pair of semiconductor regions 10. Semiconductor region 11 and conductive layer 7B
It is constituted by a semiconductor region 12 provided under a semiconductor region 10 connected to the semiconductor region 10.

Reference numeral 13 denotes an insulated I# film, which is provided so as to cover the conductive layers 7A to 7D, the semiconductor region 10, and the like. This insulating film 13
is configured to electrically isolate the conductive layers 7A to 7D, the semiconductor region 10, etc., and the conductive layer provided thereover.

Reference numeral 14 denotes a connection hole, which is provided by removing the insulating film 13 above the predetermined conductive layer 7C17D and the semiconductor region IO. This connection hole 14 is for electrically connecting the predetermined conductive layers 7G, 7D and the semiconductor region 1O to the conductive layer provided thereabove.

15A is a conductive layer, and conductive layer 7B (reference voltage wiring V
ss) and conducts the upper part of the insulating film 13.
It is provided extending in the row direction in substantially the same manner as the i-layer 7B.

This conductive layer 15A constitutes a power supply voltage wiring vcct- connected to each of the memory cells arranged in one row direction.

15B is a resistive element, one end of which is electrically connected to the conductive layer 15A, and the other end connected to the conductive layer 7C5 semiconductor region 10 or conductive layer 7i), the semiconductor region 1 through the connection holes 6 and 14.
electrically connected to 0.

This resistance element 15B constitutes resistance elements Rs and R2.

The conductive layer 15A and the resistance element 15B are formed by a second conductive layer forming step in the manufacturing process.
It is composed of a polycrystalline silicon film formed by chemical vapor deposition (hereinafter referred to as CVD) technology. The conductive layer 15A is formed by introducing an impurity into the polycrystalline silicon film to reduce the resistance value, and the resistance element 15B is formed by introducing an impurity into the polycrystalline silicon film as it is or by appropriately introducing a smaller amount of impurity into the polycrystalline silicon film than in the conductive layer 15A. and form it. The impurity constituting the conductive layer 15A is introduced by ion implantation using, for example, arsenic ions.

16 is an insulating film, which includes a conductive layer 15A and a resistive element 15B.
It is located at the top. This insulating film 16 is similar to the conductive layer 15.
The resistive element A and the resistive element ISB are electrically isolated from a conductive layer provided thereon.

17 is a connection hole, and MISFET Q s for switch
It is provided by removing the insulating film 5, 13, 16 above one of the semiconductor regions 10 of 1e Q s x.

This connection hole 17 is configured to electrically connect the semiconductor region 10 and a conductive layer provided on the insulating film 16 .

1B is a conductive layer, which is electrically connected to a predetermined semiconductor region 10 through a connection hole 17, and the upper part of the insulating film 16 is connected to the conductive layer 7.
It extends in the column direction so as to intersect with A, 7B, and 15A, and is provided to be overlapped with conductive layers 7C, 7D, and resistance element 15B. This conductive layer 18 constitutes data lines OL and DL.

The conductive layer 1B is formed by a third conductive layer forming step in the manufacturing process.

A plurality of memory cells configured in this manner are arranged in the row direction in line symmetry with respect to the Xa-Xa line or the xb-xb line,
A plurality of them are arranged in the column direction with rotational symmetry at a rotation angle of approximately 180 [degrees] at point Ya or point yb, forming a memory cell array.

Next, the manufacturing method of this example will be explained.

FIGS. 9 to 13 are cross-sectional views of main parts of an SRAM memory cell in each manufacturing process for explaining the manufacturing method of Example 2 of the present invention.

First, an i-type semiconductor substrate 1 made of single crystal silicon is prepared. An i-type well region 2 is formed on a predetermined main surface portion of this semiconductor substrate l.

The well region 2 is, for example, 2
BF2 ions of about 60[K
It is introduced by ion implantation technology with an energy of about [eV].

Formed by stretching and diffusing.

Then, a field insulating film 3 is formed on the semiconductor substrate 1 and a predetermined main surface of the well region 2, and a p-type channel stopper region 4 is formed on a predetermined main surface of the well region 2.

The field insulating film 3 is a silicon oxide film formed by a selective thermal oxidation technique on the main surface of the well region 2.

The channel stopper region 4 is, for example, 3×10 13 [at
BF2 ions of about 60 [KeV]
The field insulating film 3 is introduced by an ion implantation technique with a certain energy, and then stretched and diffused by a thermal oxidation technique to form the field insulating film 3.

Next, as shown in FIG. 9, an insulating film 5 is formed on the upper main surfaces of the semiconductor substrate 1 and the well region 2, which will be the semiconductor element formation region.
form.

The insulating film 5 is made of, for example, a silicon oxide film formed by thermal oxidation of the semiconductor substrate 1, and has a thickness of about 200 to 300 angstroms (hereinafter referred to as A) so as to constitute the gate insulating film of the MISFET. to form.

After the step of forming the insulating film 5 shown in FIG.

A predetermined portion of the insulating film 5 is removed to form a contact hole 6.

Then, conductive layers 7A to 7D are formed so as to be connected to the main surface of a predetermined well region 2 through the upper part of the field insulating film 3, the upper part of the insulating film 5, or the connection hole 6.

These conductive layers 7A to 7D are each made of a polycrystalline silicon film 7.
a and a molybdenum silicide film 7b. The polycrystalline silicon film 7a is formed over the entire surface of the substrate by, for example, CVD technology, and phosphorus is introduced to reduce the resistance value. At this time,
As shown in FIG.
, 7G or 7D on the main surface of the well region 2,
The phosphorus ions introduced into the polycrystalline silicon film 7a diffuse.

After the n0 type semiconductor region 10A is formed, a molybdenum silicide film 7b is formed thereon by sputtering. The thickness of the polycrystalline silicon film 7a is, for example, 2000 mm.
[A], and the molybdenum silicide film 7b has a thickness of 1
For example, it is formed at about 3000 [A]. After this,
Polycrystalline silicon film 7a and silicide film 7b are patterned to form conductive layers 7A to 7D. Conductive layer 7A
Since the elements 7D to 7D are made of molybdenum silicide 7a, the resistance value thereof can be set to about several [Ω/hole].

After the step of forming the semiconductor region 10A, the semiconductor region 1
form 1. The semiconductor region 11 is, for example, 1XIO"
[aeoms/cm”] of boron at 80 [Ke
The conductive layers 7A to 7D are used as a mask to introduce the conductive layers 7A to 7D somewhat deeply into the substrate using an ion implantation technique with an energy of about V], and are formed by stretching and diffusing the conductive layers 7A to 7D. After this.

As shown in FIG. 11, an n-type semiconductor region 12 is formed on the main surface of the well region 2 through the insulating film 5 in a portion where addition of parasitic capacitance to the source region or drain region is desired to be avoided. The semiconductor region 12 is, for example, 4Xl01"
Phosphorus ions of about [at, oms/am”] are
It is introduced using an ion implantation technique with an energy of about 0 [KaV], and is formed by stretching and diffusing.

The semiconductor region 12 is formed by forming the conductive layers 7A to 7D or their etching mask (to prevent impurities from being introduced into the channel forming region) and the portion surrounded by the dotted line 12 described in FIGS. 2 and 5 above. Using a mask for introducing impurities that covers
It is formed in self alignment with the conductive layers 7A to 7D.

After this, as shown in FIG. 11, an LDD structure is formed on the main surface of the well region 2 on both sides of the conductive layers 7A, 7G, and 7D through the insulating film 5.

An n-type semiconductor region 8 is formed. The semiconductor region 8 is.

Using the conductive M7A, 7G, 7D and the field insulating film 3 as a mask for impurity introduction, for example, 1×10” [
50 [Ke
It is introduced by an ion implantation technique with an energy of about V], and is formed by stretching and diffusing.

After the step of forming semiconductor region 8 shown in FIG. 11, impurity introduction masks 9 are formed on both sides of conductive layers 7A to 7D in self-alignment. This impurity introduction mask 9 is formed, for example, by applying an anisotropic etching (for example, reactive ion etching) technique to a silicon oxide film formed by a CVD technique. Further, as the impurity introduction mask 9, a polycrystalline silicon film formed by CVD technology may be used.

Then, as shown in FIG. 12, an impurity introduction mask 9
A [1゜ type semiconductor region 10 is formed in a predetermined main surface portion of the well region 2 in self-alignment with the impurity introduction mask 9 or the conductive layers 7A to 7D.

This semiconductor region lO is formed by, for example, lX
Arsenic ions of the order of IO'@[ajoms/c+m2] are introduced by an ion implantation technique with an energy of about 80 [KeV], and are formed by stretching and diffusion.

That is, semiconductor regions 8, 10, 11, and 12 are formed in self-alignment with conductive layers 7A to 7D.

After the step of forming semiconductor regions 10.11 shown in FIG. 12, an insulating film 13 is formed. This insulation [13] is formed using, for example, a silicon oxide film formed by CVD technology, and has a thickness of about 1000 to 2000 [A1].

Then, predetermined conductive layers 7C, 7D and the insulating film 13 above the semiconductor region 10 are removed to form a contact hole 14.

After this, in order to form power supply voltage wiring and a resistance element, connection is made to a predetermined semiconductor region 10 through the connection hole 14,
A polycrystalline silicon film is formed to cover the upper part of the insulating film 13. This polycrystalline silicon film is formed by, for example, CVD technology, and has a thickness of about 1000 to 200 A].

Then, an impurity is introduced into the polycrystalline silicon film, which is a power supply voltage wiring formation region other than the resistance element formation region, in order to reduce the resistance value. This impurity.

Using arsenic ions, introduced by ion implantation technology,
Dispersed by heat diffusion technology.

Thereafter, as shown in FIG. 13, the polycrystalline silicon film is patterned to form a conductive layer 15A used as the power supply voltage wiring Vcc and a resistance element 15B used as the resistance element Rl-R2. .

The impurities introduced to form the conductive layer 15A and the resistive element 15B are indicated by reference numeral 1 in FIGS. 2 and 5.
It is introduced into the polycrystalline silicon film outside the region surrounded by the dotted line indicated by 5B.

After the step of forming the conductive layer 15A and the resistive element 15B shown in FIG. 13, an insulating film 16 is formed.

This insulating film 16 is made of, for example, a silicon oxide film formed by CVD technology, and has a thickness of 3000 to 400 mm.
It is formed to about 0 [A].

Then, the insulating film 5°13 on the upper part of the predetermined semiconductor region 10 is
．． 16 is removed to form a connection hole 17.

After this 1. As shown in FIGS. 2 and 6, it is electrically connected to a predetermined semiconductor region 10 through a connection hole 17,
A conductive layer 18 is formed on the insulating film 16 to extend in the column direction so as to intersect with the conductive layer 7A.

For the conductive layer 18, for example, an aluminum film formed by sputter deposition technology is used.

Through these series of manufacturing steps, the SRAM of this embodiment is completed. Note that, after this, a treatment process such as a protective film may be performed.

Next, another manufacturing method of Example 1 will be explained.

FIGS. 14 to 16 are cross-sectional views of essential parts of an SRAM memory cell in each manufacturing process for explaining another manufacturing method of Embodiment 2 of the present invention.

After the step of forming the semiconductor region 10A shown in FIG. 1O, the semiconductor region 8 is formed as shown in FIG.

After the step of forming the semiconductor region 8 shown in FIG. 14, an impurity introduction mask 9 is formed.

Then, as shown in FIG. 15, an impurity introduction mask 9
using the impurity introduction mask 9 or the conductive layers 7A to 7D.
The semiconductor region lO and the semiconductor region 11 are self-aligned with respect to each other.
form.

After the step of forming the semiconductor region 10 and the semiconductor region 11 shown in FIG. 15, for example, a mask for impurity introduction (15) shown by dotted lines 12 in FIGS. (not shown in the figure).

Then, as shown in FIG. 16, a semiconductor region 12 is formed using the impurity introduction mask.

After the step of forming the semiconductor region 12 shown in FIG.
By performing the steps after the step of forming the semiconductor regions 10 and 11 shown in FIG.
is completed.

Although the latter manufacturing method cannot form the semiconductor region 12 in self-alignment with the conductive layers 7A to 7D, similar to the former manufacturing method, it can sufficiently reduce the parasitic capacitance in the portion where its addition is desired to be avoided. be able to.

In Example 2, the present invention is implemented by providing a semiconductor region 11 of an opposite conductivity type in an LDD structure MISFET having an LDD section (semiconductor region 8), and converting the junction capacitance between the semiconductor region 11 and the semiconductor region 10 into a semiconductor region. Although the present invention is applied to an example in which the capacitance is reduced in the region 12, it may also be applied to an example in which the semiconductor region 12 is simply provided in an LDD structure M r S FET and the junction capacitance between the semiconductor region 10 and the well region 2 is reduced.

As explained above, according to the present embodiment (2), the following effects can be obtained.

(L) In a semiconductor integrated circuit device equipped with an LDD structure MISFET having an LDD section (semiconductor region 8), the well region 2 Since the extension of the depletion region at the pn junction with the MISFET can be increased, the junction capacitance added to the MISFET can be reduced.

(2) In a semiconductor integrated circuit device in which a semiconductor region 11 of an opposite conductivity type is provided in a MISFET having an LDD structure, the semiconductor region 11 and p of
Since the extension of the depletion region at the n-junction can be increased, the junction capacitance added to the MISFET can be reduced.

(3) According to (1) or (2) above, the speed of the semiconductor integrated circuit device can be increased.

(4) According to (1) or (2) above, it is possible to reduce the flow of impurities into the channel forming region in the LDD portion, so that a sufficient effective channel length of the MISFET can be ensured.

(5) According to (4) above, the short channel effect can be suppressed, so the area occupied by the MI S FET can be reduced and the degree of integration of the semiconductor integrated circuit device can be improved.

(6) According to (2) above, it is possible to suppress the coupling of the depletion region between the source region and the drain region in the semiconductor region 11, so that bunch-through can be suppressed.

(7) According to (2) above, the junction capacitance added to the source region or the drain region in the semiconductor region 11 can be increased, so the amount of information storage in the SRAM memory cell can be increased.

(8) According to (2) above, in the memory cell of the SRAM, the semiconductor region 11 can form a barrier in the portion where charges serving as information are accumulated.

Intrusion of unnecessary carriers caused by α rays can be suppressed.

(9) According to (7) or (8) above, soft errors can be suppressed, so the electrical reliability of the SRAM can be improved.

(lO) According to (2) above, it is possible to add junction capacitance to a predetermined portion of the semiconductor region 11 provided to suppress punch-through in order to increase the amount of information stored, which increases the manufacturing process. There's nothing left to do.

(11) According to (1) or (2) above, the back bias for reducing junction capacitance and its circuit are unnecessary, so the design of the semiconductor integrated circuit device is simplified and the area occupied by it is eliminated. The degree of integration can be improved.

(12) According to (3), (5) and (9) above.

It is possible to simultaneously increase the operating speed, increase the degree of integration (or increase the capacity), and improve the electrical reliability of a semiconductor integrated circuit device.

[Embodiment 2] This embodiment 2 is an embodiment of the present invention in which the semiconductor region of the opposite conductivity type is provided below the channel region of the MISFET.

FIG. 17 shows an SR for explaining Embodiment ① of the present invention.
FIG. 3 is a cross-sectional view of a main part of an AM memory cell.

In FIG. 17, 11A is a p+ type (opposite conductivity type) semiconductor region, which is provided on the main surface of the well region 2 along the lower part of the predetermined semiconductor region 10 and the semiconductor region 8, in contact with them. There is. Semiconductor region 11 shown in FIG.
Similarly to the embodiment (2), A has a structure in which the junction depth is shallower than that of the semiconductor region 12.

The semiconductor region 11A is self-aligned with the impurity introduction mask 9° or the conductive layers 7A to 7D.

Semiconductor region 11. A has substantially the same function as the semiconductor region 1 described above.

A feature of this embodiment is that the semiconductor region 11A wraps around the channel forming region, which causes fluctuations in the threshold voltage and fluctuations in the impurity concentration of the semiconductor region (LDD section) 8. Therefore, the impurity concentration of the channel forming region and the impurity concentration of the semiconductor region 8 are
It is only necessary to control in advance the variation in impurity concentration due to 1A and 11B.

As explained above, according to one embodiment (■), the above-mentioned embodiment (■)
Almost the same effect can be obtained.

Example (2) This example (2) is an example in which the semiconductor region of the opposite conductivity type is provided deeper.

FIG. 18 shows an SRA for explaining embodiment ① of the present invention.
FIG. 3 is a cross-sectional view of a main part of a memory cell of M.

In FIG. 18, 11B is a P type (opposite conductivity type) semiconductor region, which is provided on the main surface of the well region 2 along the lower part of the predetermined semiconductor region 10 and the semiconductor region 8, in contact with them. ing. Semiconductor region 11 shown in FIG.
B has a deeper junction depth than the semiconductor region 12.

The semiconductor region 11B is self-aligned with the impurity introduction mask 9° or the conductive layers 7A to 7D.

The semiconductor region 11B has substantially the same function as the semiconductor region 11A. Therefore, the impurity concentration of the channel forming region and the impurity concentration of the semiconductor region 8 are
It is only necessary to control in advance the amount by which the impurity concentration changes due to B.

As explained above, according to Example 1, Example I
Almost the same effect can be obtained.

[Example 2] This example 2 applies the present invention to a semiconductor integrated circuit device (hereinafter referred to as DRA) equipped with a dynamic random access memory.
It is applied to M).

FIG. 19 is a DRA for explaining Embodiment 2 of the present invention.
FIG. 3 is an equivalent circuit diagram showing M memory cells.

In FIG. 19, DL is a data line extending in the row direction;
WL is a word line extending in the column direction.

Qs is MISFET for switch, Go is MI
This is an information storage capacitive element connected in series with SFETQs.

A DRAM memory cell is constituted by a MISFET Qs and an information storage capacitive element C0, and is provided at a predetermined intersection with a data line DLq and a word line WL.

Next, the specific structure of this embodiment (2) will be explained.

FIG. 20 is a DRA for explaining Embodiment 2 of the present invention.
FIG. 2 is a cross-sectional view of a main part of a memory cell of M. FIG.

In FIG. 20, IOB is an n3 type semiconductor region, electrically connected to the semiconductor region 10, and provided on the main surface of the well region 2 in the information storage capacitive element formation region. The semiconductor region 10B constitutes one electrode of the information storage capacitive element.

11C is a P1 type semiconductor region, which is electrically connected to the semiconductor region 11 and is provided in contact with the semiconductor region 10B on the main surface of the well region 2 below the semiconductor region 10B. The semiconductor region 11C.

The other electrode of the information storage capacitive element is configured.

Compared to the well region 2, the semiconductor region 11C has a pn junction with the semiconductor region 10B having a higher impurity concentration. That is, semiconductor region 1
The structure is such that the junction capacitance added to 0B and the semiconductor region 11C is increased to increase the amount of charge stored as information in the information storage capacitive element.

Reference numeral 19 denotes an insulating film, which is provided on the upper main surface of the semiconductor region 10B in the information storage capacitive element formation region.

A conductive plate 20 is provided on the insulating film 19 and the field insulating film 3. The conductive plate 20 is formed by a first conductive layer forming step in the manufacturing process, and uses, for example, a polycrystalline silicon film formed by CVD technology.

Note that the semiconductor regions 10B and 11G are formed before the step of forming the conductive plate 20.

The insulating film 19 and the conductive plate 20 constitute an information storage capacitive element.

The information storage capacitive element Co of the memory cell is located in the semiconductor region 1
A first information storage capacitive element composed of a semiconductor region 11C and a semiconductor region 10B.

A second information storage capacitive element composed of an insulating film 19 and a conductive plate 20 is connected in parallel.

Reference numeral 21 denotes an insulating film, which is provided to cover the conductive plate 20. The insulating film 21 is configured to electrically isolate the conductive plate 20 and the conductive layer provided thereon.

5A is an insulating film, which is provided above the main surface of the well region 2 in the MI S FET formation region. The insulating film 5A mainly constitutes the gate electrode of the MISFET.

A conductive layer 7E is provided extending in the column direction on a predetermined upper part of the insulating film 5A and a predetermined upper part of the insulating film 21. The conductive layer 7E is M I S F on the upper part of the insulating film 5A.
The gate electrode of ET is formed, and the upper part of the insulating film 21 forms a word line WL.

The switch MISFETQs of the memory cell are mainly used in the well region 2. It is composed of an insulating film 5A, a conductive layer 7E, a pair of semiconductor regions 8, a pair of semiconductor regions 10, a semiconductor region 11, and a semiconductor region 12. That is, M of the LDD structure in which one semiconductor region 11 of opposite conductivity type is provided.
In ISFETQ8, by providing the semiconductor region 12, the impurity concentration of the semiconductor region 11 is reduced, and the parasitic capacitance added to the source region or the drain region (semiconductor region 10) can be reduced.

In addition, in the embodiment, the semiconductor region 11 and the semiconductor region l
Although a memory cell in which an IC and an IC are formed in separate processes has been described, they may be formed in the same manufacturing process. Specifically, before the step of forming the conductive plate 20, a semiconductor region of the opposite conductivity type (p'' type) is formed over the entire surface of the memory cell formation region.

[Effects] As explained above, according to the novel technology disclosed in the present application, the following effects can be obtained.

(1) In a semiconductor integrated circuit device equipped with an LDD structure MISFET having an LDD section, the pn of the lower part of the source region or drain region and the semiconductor substrate or well region is
By providing a semiconductor region in which the n-junction part constitutes a pn junction with a low impurity concentration, the extension of the depletion region at the pn junction can be reduced, so that the source region or drain region can be Added parasitic capacitance can be reduced.

(2) In a semiconductor integrated circuit device in which a MISFET having an LDD structure is provided with a semiconductor region of an opposite conductivity type.

By providing a semiconductor region that forms a pn junction with a low impurity concentration at the pn junction between the lower part of the source or drain region and the semiconductor region of the opposite conductivity type, the depletion region at the pn junction is reduced. Since the elongation can be increased, the junction capacitance added to the source region or drain region can be reduced.

(3) According to (1) or (2) above, the speed of the semiconductor integrated circuit device can be increased.

(4) According to (1) or (2) above, it is possible to reduce the flow of impurities into the channel forming region in the LDD portion, so that a sufficient effective channel length of the MISFET can be ensured.

(5) According to (4) above, the short channel effect can be suppressed, so the area occupied by the MISFET can be reduced and the degree of integration of the semiconductor integrated circuit device can be improved.

(6) According to (2) above, it is possible to suppress the coupling of the depletion region between the source region and the drain region in the semiconductor region of opposite conductivity type, so that punch-through can be suppressed.

(7) According to (2) above, it is possible to increase the junction capacitance added to the source region or drain region in the semiconductor region of the opposite conductivity type, so that information can be stored in the memory cell of a semiconductor integrated circuit device with a memory function. The amount can be increased.

(8) According to (2) above, in the memory cell, it is possible to form a barrier with a semiconductor region of the opposite conductivity type in the part where electric charge serving as information is accumulated, thereby suppressing the intrusion of unnecessary carriers generated by α rays. be able to.

(9) According to (7) or (8) above, soft errors can be suppressed, so that the electrical reliability of a semiconductor integrated circuit device with a memory function can be improved.

(10) According to (2) above, junction capacitance can be added to a predetermined portion in order to increase the amount of information stored in the semiconductor region of the opposite conductivity type provided to suppress bunch-through. There is no need to increase the manufacturing process.

(11) According to (1) or (2) above, the back bias for reducing junction capacitance and its circuit are unnecessary, so the design of the semiconductor integrated circuit device is simplified and the area occupied by it is eliminated. The degree of integration can be improved.

(12) According to (3), (5) and (9) above.

It is possible to simultaneously increase the operating speed, increase the degree of integration (or increase the capacity), and improve the electrical reliability of a semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically explained in the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course it is possible.

For example, the embodiment described above describes how the present invention can be applied to M I of an LDD structure.
S FET or LD with semiconductor region of opposite conductivity type
D structure + 7) SRAM or DRA with MISFET
I have explained an example where this is applied to M.

In addition to these semiconductor integrated circuit devices with memory functions, the present invention may also be applied to semiconductor integrated circuit devices with logic functions.

[Brief explanation of drawings]

FIG. 1 shows an SRAM for explaining embodiment ① of the present invention.
FIG. 3 is an equivalent circuit diagram showing a memory cell of FIG. Figure 2 shows an SRAM for explaining Embodiment 1 of the present invention.
FIG. 3 is a plan view of main parts of a memory cell. 3 to 5 are plan views of main parts in predetermined manufacturing steps of the memory cell shown in FIG. 2, and FIG.
- A cross-sectional view along the Vl cutting line. FIG. 7 shows MISFETQs of the memory cell shown in FIG.
FIG. 8 is an enlarged cross-sectional view of the main part at the t portion, and FIG. 8 is a diagram showing the impurity concentration distribution of the source region or drain region of the MISFET Q 81 shown in FIG. 7. FIGS. 9 to 13 are FIG. 3 is a cross-sectional view of a main part of an SRAM memory cell in each manufacturing process for explaining the manufacturing method of Example I of the present invention. 14 to 16 are main part cross-sectional views showing the SRAM memory cell in each manufacturing process for explaining another manufacturing method of Embodiment 1 of the present invention, and FIGS. 17 and 18 are 1
FIG. 2 is a cross-sectional view of a main part of an SRAM memory cell for explaining embodiments (1) and (2) of the present invention. FIG. 19 shows a DRA for explaining embodiment ① of the present invention.
FIG. 20 is an equivalent circuit diagram showing a memory cell of M. FIG. 20 is a sectional view of a main part of a DRAM memory cell for explaining embodiment (2) of the present invention. In the figure, 1... semiconductor substrate, 2... well region, 5...
... Insulating film, 7... Conductive layer, 8, 10j11, 12.
...Semiconductor region, 9...Mask for impurity introduction, Q, Q
s...MIS FET. Figure 2 X9
Xr) Fig. 4 δ 4(P) Fig. 5

Claims (1)

[Claims] 1. A conductive layer is provided on the main surface of the first semiconductor region of the first conductivity type with an insulating film interposed therebetween;
A second semiconductor region of a second conductivity type is provided on the main surface of the semiconductor region, and a second semiconductor region of the second conductivity type is provided on the main surface of the first semiconductor region between the second semiconductor region and the channel forming region. A semiconductor integrated circuit device having a MISFET configured by providing a third semiconductor region having a lower impurity concentration than the second semiconductor region, the semiconductor integrated circuit device having a third semiconductor region having a lower impurity concentration than the third semiconductor region, wherein A semiconductor integrated circuit device comprising: a fourth semiconductor region having a predetermined conductivity type and a low impurity concentration. 2. A patent claim characterized in that the fourth semiconductor region is formed by introducing an impurity of the same conductivity type as that of the second semiconductor region into the junction portion and stretching and diffusing the impurity. The semiconductor integrated circuit device according to scope 1. 3. The fourth semiconductor region is configured to increase the extension of the depletion region at the junction between the second semiconductor region and the first semiconductor region. The semiconductor integrated circuit device according to item 1. 4. The maximum impurity concentration portion of the fourth semiconductor region is higher than that of the second semiconductor region or the third semiconductor region.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided deep from the main surface of the semiconductor region. 5. A conductive layer is provided on the main surface of the first semiconductor region of the first conductivity type with an insulating film interposed therebetween, and the first conductive layer is provided on both sides of the conductive layer.
A second semiconductor region of a second conductivity type is provided on the main surface of the semiconductor region, and a second semiconductor region of the second conductivity type is provided on the main surface of the first semiconductor region between the second semiconductor region and the channel forming region. and a third semiconductor region having a lower impurity concentration than the second semiconductor region, and a third semiconductor region having a first conductivity type and having a higher impurity concentration than the first semiconductor region on the main surface of the first semiconductor region along the second semiconductor region. M configured by providing a fourth semiconductor region having a concentration
A semiconductor integrated circuit device having an ISFET, wherein a fifth semiconductor region having a predetermined conductivity type and a low impurity concentration is provided in a part of the junction between the second semiconductor region and the fourth semiconductor region.
1. A semiconductor integrated circuit device comprising a semiconductor region. 6. A patent claim characterized in that the fifth semiconductor region is formed by introducing an impurity of the same conductivity type as that of the second semiconductor region into the junction portion and stretching and diffusing the impurity. The semiconductor integrated circuit device according to item 5. 7. The fifth semiconductor region is configured to increase the extension of the depletion region at the junction between the second semiconductor region and the fourth semiconductor region. The semiconductor integrated circuit device according to item 5. 8. The maximum impurity concentration portion of the fifth semiconductor region is provided deeper from the main surface of the first semiconductor region than the second semiconductor region, third semiconductor region, or fourth semiconductor region. The semiconductor integrated circuit device according to claim 5, characterized in that the semiconductor integrated circuit device comprises: 9. The maximum impurity concentration portion of the fifth semiconductor region is deeper than the maximum impurity concentration portion of the second semiconductor region,
The first semiconductor region is shallower than the maximum impurity concentration portion of the fourth semiconductor region.
6. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is provided on a main surface of a semiconductor region. 10. Each of the semiconductor integrated circuit devices according to claims 5 to 9, wherein the fourth semiconductor region is also provided along the third semiconductor region. 11. A conductive layer is provided on the main surface of the first semiconductor region of the first conductivity type with an insulating film interposed therebetween, and a conductive layer of the second conductivity type is provided on the main surface of the first semiconductor region on both sides of the conductive layer. A second semiconductor region is provided in the main surface portion of the first semiconductor region between the second semiconductor region and the channel formation region, and has a second conductivity type and a lower impurity concentration than the second semiconductor region. A third semiconductor region is provided, and a fourth semiconductor region having a first conductivity type and a higher impurity concentration than the first semiconductor region is provided on the main surface of the first semiconductor region along the second semiconductor region. A semiconductor integrated circuit device having a MISFET configured by providing a MISFET having a predetermined conductivity type and a low impurity concentration in a part of the junction between the second semiconductor region and the fourth semiconductor region. 1. A semiconductor integrated circuit device comprising: a first MISFET configured with five semiconductor regions; and a second MISFET without the fifth semiconductor region. 12. The first MISFET is a switch MISF
12. The semiconductor integrated circuit device according to claim 11, which is used as an ET. 13. The semiconductor integrated circuit device according to claim 11, wherein the second MISFET constitutes an information storage MISFET that stores information of a memory cell with a storage function. 14. The semiconductor integrated circuit device according to claim 13, wherein the second MISFET is an information storage MISFET constituting a memory cell of a static random access memory. 15. In the second MISFET, a fourth semiconductor region is provided under the second semiconductor region in a portion where charges serving as information are accumulated, and the fifth semiconductor region is provided in the other portion. Claim 1 characterized in that
The semiconductor integrated circuit device according to item 1. 16. The semiconductor integrated circuit device according to claim 15, wherein the second MISFET constitutes a memory cell of a dynamic random access memory.