JPS62249474A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase stored charge and avoid soft errors by a method wherein a high concentration semiconductor region which is brought into contact with the drain region of a driving MISFET and has the conductivity type opposite to that of the drain region is formed below the drain region and the channel forming region of the driving MISFET. CONSTITUTION:The drain region of a driving MISFET (Q) is composed of a semiconductor region 9 which has a deeper junction depth than the source region or the drain region (semiconductor region 11) of a transfer MISFET (Qs) and a high concentration semiconductor region 5 which is brought into contact with the semiconductor region 9 is provided on the main surface of a well region 2 at a deep position below the semiconductor region 9 and a channel forming region. With this constitution, a potential barrier region against minority carriers created by alpha-ray can be formed without inducing fluctuation in threshold of the driving MISFET (Q) and, at the same time, the capacity of the p-n junction composed of the high concentration semiconductor region 5 and the high concentration semiconductor region 9 can be increased. Therefore, penetration of minority carriers into an information storing capacity C is avoided while electrical reliability at the time of information writing is being improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device (hereinafter referred to as SRAM) equipped with a static random access memory. It is about effective techniques.

[Conventional technology]

The memory cell of the SRAM is composed of a transfer MISFET and a flip-flop circuit having a driving Mr S FET. This SRAM needs to prevent soft errors caused by alpha rays in order to improve reliability in information read operations and achieve high integration.

Therefore, the patent application filed earlier by the applicant in 1982-
The techniques described in Japanese Patent Application No. 218470 and Japanese Patent Application No. 59-260744 are effective in preventing soft errors.

In the former first technique, a highly doped p-type semiconductor region is provided below a heavily doped n-type drain region of a driving MISFET used as an information storage capacitive element and in contact with the n-type drain region. In other words, this P-type semiconductor region increases the pn junction capacitance, that is, the amount of charge storage that becomes information, and can prevent information from being inverted due to minority carriers. In the p-type semiconductor region, p-type impurities are introduced by ion implantation, and driving MI
It is configured in a self-aligned manner with respect to the gate electrode of the SFET.

The latter second technology is a deep position below the driving MISFET used as a capacitive element for information storage.

That is, a highly doped P-type semiconductor region is provided at a deep position separated from the drain region. In other words, this P-type semiconductor region constitutes a potential barrier region against minority carriers generated by α rays, thereby preventing minority carriers from entering the information storage capacitive element and preventing information from being reversed. The p-type semiconductor region is formed in substantially the entire area of the memory cell by introducing p-type impurities by high-energy ion implantation.

[The problem that the invention is trying to solve]

The inventor of the present invention investigated electrical reliability against soft errors using each of the first and second techniques described above, and found that the first problem occurred.

In the first technique described above, the p-type semiconductor region can also be used as a potential barrier region, but cannot be configured as a channel formation region under the gate electrode. For this reason, even though the amount of charge storage serving as information is increased, minority carriers in an amount equal to or more than the increased amount enter from the channel forming region, and soft errors cannot be sufficiently prevented.

In addition, in the second technique described above, in order to sufficiently prevent soft errors, p
It is necessary to configure the type semiconductor region with a high concentration. However, when the impurity concentration of the p-type semiconductor region is increased, the p-type impurity diffuses into the channel formation region, and the transfer and drive MI
Changes the threshold voltage of S FET and reduces electrical reliability.

An object of the present invention is to provide a technique that can prevent soft errors and improve Wi electrical reliability in a semiconductor integrated circuit device with a memory function.

Another object of the present invention is to provide a technique capable of reducing the memory cell area and improving the degree of integration in a semiconductor integrated circuit device having a memory function.

The above and other objects and novel features of the present invention will become apparent from the description of the present MAv and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In an SRAM in which a memory cell is composed of a transfer MISFET and a drive MISFET, the drain region of the drive MISFET is The driving MIS
Below the drain region and channel forming region of the FET,
A high concentration semiconductor region is formed which is in contact with the drain region of the driving MISFET and has a conductivity type opposite to that of the drain region.

[For production]

According to the above-mentioned means, it is possible to increase the pn junction capacitance between the drain region and the highly doped semiconductor region, and increase the amount of charge storage that serves as information, thereby making it possible to prevent soft errors and improve the performance of the driving MTSFET. Since a potential barrier region for minority carriers can be formed in the semiconductor region at a position that does not affect the threshold voltage, soft errors can be prevented and electrical reliability can be improved.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to an SRAM having a memory cell that constitutes a flip-flop circuit with a high resistance load element and a driving MISFET.

A memory cell of an SRAM that is an embodiment of the present invention is shown in FIG. 1 (equivalent circuit diagram), and an input section of the SRAM is shown in FIG. 2 (equivalent circuit diagram).

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

The memory cell of SRAM is as shown in FIG.

A pair of data lines DL are provided at intersections between DL and word line WL. That is, the memory cell includes a flip-flop circuit having a pair of input/output terminals, and a transfer M T
It is composed of S F E T Q s + and Q S 2.

M for transfer (or as a switch for memory cell selection)
One end of ISFETQs is the input/output terminal of the flip-flop circuit, and the other end is the data line DL.

Gate electrodes are respectively connected to word lines WL.

The flip-flop circuit is driven by MISFETQ, ,Q
2 and high resistance load elements R1 and R2. The drain region of the drive MISFETQ is connected to the power supply voltage wiring Vcc via a high resistance load element R. The source region of the drive MISFETQ is connected to the reference voltage wiring V
connected to ss.

For example, the circuit operating voltage 5 is connected to the power supply voltage wiring Vcc.
．． 0 [V] is applied, and 1, for example, a ground potential of the circuit 0 [V] is applied to the reference voltage wiring Vss.

The memory cell has “i” in the information storage capacitance (parasitic capacitance) C.
, "o" Information can be considered to be stored by accumulating charges that become information. The capacity C is mainly M
It consists of the gate capacitance of ISFET Q+, Q2 and the pn junction capacitance between the drain region and the substrate (actually the well region).

The input section of the SRAM is configured as shown in FIG. That is, the external terminal (bonding butt) BP
, an input stage circuit (input buffer circuit or address buffer circuit) (2), and an electrostatic breakdown prevention circuit (2) inserted between them.

The external terminal BP is configured to input an output signal from an external device to the SRAM, and is configured to input an output signal from an external device to the SRAM, and inputs the data extending on the aforementioned memory cell array! It is composed of the same conductive layer as IIDL.

The input stage circuit I is composed of an inverter circuit composed of a p-channel MISFET Qp and an n-channel MISFET Qn s. MISFETQ
Each gate electrode of P + Q n 3 is connected to the external terminal BP. The drain regions of MISFETQp and Qn3 are connected to the output signal input terminal P of the next stage circuit.
Connected to out. The source region of MISFETQp is connected to the power supply voltage wiring Vcc, and the MISFETQp
The source region of Qns is connected to the reference voltage wiring Vss.

The electrostatic breakdown prevention circuit (2) is composed of a protective resistance element R3, and n-channel MI5FE71''Qn+ and Qn2 for clamping.

Protective resistance element R3 prevents electrostatic damage (input stage circuit
It is configured to smooth out the excessive voltage that would cause damage to the gate insulating film of I S F E T Q P , Q n 3). Although not shown, the protective resistance element R3 has, for example, a predetermined low resistance value (for example, about 1 [KΩ]). It is composed of a polycrystalline silicon film or a semiconductor region into which impurities (arsenic, phosphorus, or boron) are introduced.

The gate electrodes of MISFETQn+ and Qn2 are connected to the reference voltage wiring Vss. M.I.S.
Drain region of FETQnr and MISFE
The source region of T Q n 2 is connected to the external terminal BP and the input stage circuit I. MISFET
The source region of Q n s is connected to reference voltage wiring Vss, and the drain region of MISFET Q n 2 is connected to power supply voltage wiring Vcc. This M
I S FETQn+, Qn2 are configured to clamp excessive voltage.

Next, the specific configuration of the SRAM of the ninth embodiment will be explained. M I S FETQ n of the input stage circuit l
3 is M I S F E T Q for memory cell transfer.
5 (QsI, QS2) and M of the electrostatic breakdown prevention circuit ■
The I5FETQrz+Qn2 has substantially the same configuration as the memory cell driving MI5FETQ (Q+, Q2).

A memory cell of an SRAM which is an embodiment of the present invention is shown in FIG. 3 (a plan view of main parts), and a cross section taken along the line IV--IV in FIG. 3 is shown in FIG. 4A. Note that in FIG. 3 and FIGS. 5 and 6, which will be described later, insulating films other than the field insulating film provided between each 17111 are not shown in order to make the structure of the SRAM of this embodiment easier to understand. Further, FIG. 4B shows the configuration of the MISFET of the circuits ① and ① described above.

In FIGS. 3 and 4A, 1 is an n-type semiconductor substrate made of single crystal silicon, and 2 is a P-type well region provided on a predetermined main surface of the semiconductor substrate 1. In FIG. The well region 2 is, for example, 10” [at, on+s/cn+
It is composed of an impurity concentration of about 1.

A field insulating film 3. is formed on the main surface of the well region 2 between the semiconductor element forming regions. A P-type channel stopper region 4 is provided. Each of the field insulating films 3 and channel stopper regions 4 is formed to electrically isolate semiconductor elements, as shown in detail in FIG. It is configured.

Transfer MISFET Qst l QS2. Drive MI
In particular, each of the 5FETs Q+ and Q2 is formed on the main surface of the well region 2 in the region surrounded by the field insulating film 3, as shown in detail in FIG. It is set in.

That is, the transfer MISFETQs is formed within the well region 2, and the gate insulating film 6. Gate electrode7. sauce,
It is composed of a pair of n-type semiconductor regions 8 and a pair of n0-type semiconductor regions 11, which are drain regions.

The driving MI 5FETQ is formed in the well region 2, and the gate insulating film 6. Gate electrode7. It is composed of a pair of 4-type semiconductor regions 11 and 11°n-type semiconductor regions 9, which are source and drain regions.

Gate ffi ti 7 is 1. For example, high melting point metal silicide (MoSi2.TiSi
2゜TaSi2. WSi. ) is composed of a polycide film provided with a film. Further, the gate electrode 7 is a single layer polycrystalline silicon film or a high melting point metal silicide film.

It may be composed of a high melting point metal film (Mo, Ti, Ta, W) or a composite film in which a high melting point metal film is provided on top of a polycrystalline silicon film.

One end of the gate @tliA7 of the driving MI 5FETQ is connected to the semiconductor region 11 through a connection hole 6A provided in the gate insulating film 6, so-called direct contact.

Gate electrode 7 of transfer MISFETQs
A word line (WL) 7A extending in the column direction on the field insulating film 3 is integrally formed in the field insulating film 3.

Further, a reference voltage wiring (Vs
s) 7B is connected.

Highly doped semiconductor region 11 is used as a source region or a drain region. The semiconductor region 11 is connected to the gate electrode 7
The impurity introduction mask 10 is provided on the side of the impurity introduction mask 10. The semiconductor region 11 is 1, for example, 1
It is constructed with an n-type impurity (eg, arsenic) at a concentration of about 0.021 [atoms/c+++3], and has a junction depth of about 0.25 [μm].

A low concentration (low impurity concentration) semiconductor region 8 of the transfer MIS and FET QS is provided between a high concentration (high impurity concentration) semiconductor region 11 and a channel forming region (well region 2). The semiconductor region 8 is
Htly Doped Drain) structure MISFE
It is designed to constitute T. The semiconductor region 8 has a concentration of, for example, about 10"[amotas/lyn'
Consisting of type impurities (e.g. phosphorus), 0.10 [μm]
Constructed with a bonding depth of approximately

The high concentration semiconductor region 9 is provided on the main surface of the well region 2 in a portion that contributes to improving the amount of charge storage serving as information (a portion constituting the information storage capacitor C). That is, the semiconductor region 9 is particularly provided in the drain region of the driving MISFETQ.

In addition, the semiconductor region 9 is one of the source region and the drain region of the transfer MISFET Qs (driving MISFET
It is also provided in a part of the semiconductor region 11 on the side connected to the semiconductor region 11. This semiconductor region 9 is a transfer MISFETQ
Compared to the semiconductor region 11 of S.

The junction depth of the drain region of the driving MI S FETQ is configured to be deep. Note that the semiconductor region 9
is also formed in the source region of the driving MISFETQ.

Specifically, the semiconductor region 9 is within the region indicated by the reference numeral 9 in FIGS. 3 and 6 and surrounded by a dashed line, and is self-aligned with the field insulating film 3 and the gate electrode 7 configured. This semiconductor region 9 has 102' to lO2'
It is formed with an n-type impurity (for example, phosphorus) at a concentration of about [at, oms/c5+'] and has a junction depth of about 0.4 to 0.5 [μm].

In this way, by providing the semiconductor region 9 in the semiconductor region 11 used as the drain region of the driving MISFETQ and configuring the junction depth to be deep (by increasing χj),
This allows the semiconductor region 9 to wrap around below the gate electrode 7 of the driving MISFETQ (toward the channel formation region side).

By increasing the overlapping area of the semiconductor region 9 (drain region) and the gate electrode 7, the mirror capacitance can be increased, and the amount of charge stored as information in the information storage capacitor C can be increased. Therefore, when minority carriers generated by α rays in the well region 2 invade the information storage capacitive element C,
Since information can be reversed and made more beautiful, soft errors can be prevented.

This driving MISFETQ is designed to increase the channel length of the gate electrode 7 in order to actively increase the mirror capacitance.
- Long dimension) may be configured to be large, and the driving MI
In the SFETQ, the channel length of the gate electrode 7 may be configured to be large so that the effective channel length can be ensured even if the semiconductor region 9 wraps around to the channel forming region side.

In the memory cell configured as described above, a buried type p A semiconductor region 5 of the type is provided. Specifically, the semiconductor region 5 is.

It is formed at a deep position at least below the semiconductor region 9 used as the drain region of the driving MI 5FETQ and the channel forming region, and in contact with the pn junction surface between the semiconductor region 9 and the well region 2.

That is, the semiconductor region 5 is formed at a deep position and impurity concentration such that it does not affect the channel formation region of the driving MISFETQ while actively increasing the pn junction capacitance with the semiconductor region 9. In the semiconductor region 5, when the impurity diffuses into the channel formation region, the substrate effect constant becomes large and the threshold voltage becomes high. Therefore, the write voltage during the information write operation decreases, and stable information write operation is achieved. I can't do it.

Specifically, the semiconductor region 5 is 1, for example -tol? ~10
`` '' It is composed of an n-type impurity (for example, boron) with a concentration of about [atoms/cm3], and is configured to have a peak value of the impurity concentration at a depth of about 0.7 [μm]. The semiconductor region 5 is formed by introducing an n-type impurity using, for example, the field insulating film 3 as a mask for impurity introduction, and forming the semiconductor region 5 over substantially the entire area of the memory cell (excluding the field insulating film 3r). Note that the semiconductor device 5 may be configured in a peripheral circuit other than the memory cell array, but it does not need to be configured in a part where it is particularly desired to reduce the threshold voltage and increase the operating speed.

Thus, compared to the source or drain region (semiconductor region 11) of the transfer MISFET Qs.

The drain region of the driving MISFETQ is composed of a semiconductor region 9 with a deep junction depth, and on the main surface of the well region 2 at a deep position below this semiconductor region 9 and the channel forming region,
By providing the highly concentrated semiconductor region 5 in contact with the semiconductor region 9, a potential barrier region (barrier) is formed against minority carriers generated by α rays without causing any fluctuation in the threshold voltage of the driving MISFETQ. In addition, it is possible to increase the pn junction capacitance formed by the high concentration semiconductor region 5 and the high concentration semiconductor region 9.

Therefore, while improving the electrical reliability during the information writing operation, it is possible to prevent minority carriers from entering the information storage capacitor C, and even if the minority carriers enter the information storage capacitor C, the information Since it is possible to prevent the reversal of , it is possible to prevent soft errors.

Furthermore, by preventing soft errors, the memory cell area can be reduced, so the degree of integration of the SRAM can be improved.

An interlayer insulating film 12 is provided on the MISFET Q and Qs to cover them. A connection hole 13 is provided in the glabella insulating film 12 above the predetermined semiconductor region 11 .

On the interlayer insulating film 12 in the memory cell, a power supply voltage wiring (Vcc) 14A and high resistance load elements (R+, R
2) 14B is provided.

One end of the high resistance load element 14B is connected to the power supply voltage wiring 14.
Connected to A. The other end of the high resistance load element 14B is connected to the MISFET Qs I, Q through the connection hole 13.
S2 semiconductor region 11 and MISFE T Q I
, Q2 is electrically connected to the gate electrode 7 of Q2.

Each of the power supply voltage wiring 14A and the high resistance load element 14B is a conductor 1tWJ whose resistance value can be controlled by introducing impurities;
For example, it is made of a polycrystalline silicon film. The power supply voltage wiring 14A is made of a polycrystalline silicon film into which an n-type impurity (arsenic or phosphorus) is introduced to reduce the resistance value. The high resistance load element 14B is made of a so-called non-doped polycrystalline silicon film into which the impurities that reduce the resistance value are not introduced. The high resistance load element 14B is the third
It is formed within a region (indicating the pattern of an impurity introduction mask) surrounded by a dashed line marked 14B in the figure.

15 is an interlayer insulating film covering each of the power supply voltage wiring 14A and the high resistance load element 14B, and 16 is a connection hole provided by removing the insulating films 6, 12, and 15 above the semiconductor region 11 of MISFETQs.

Reference numeral 17 denotes data lines DL, DL, which are electrically connected to the semiconductor region 11 of the M I S FET Qs through the contact hole 16 and are configured to extend in the row direction above the first interlayer insulating film 15. The data line 17 is an aluminum film,
It is composed of an aluminum film or the like containing predetermined additives (Si, Cu).

FIG. 4B shows the p and n channel M making up the internal circuit.
The configuration of ISFETQP and Qn3 and the n-channel MISFETQnI (and Qn2) that constitutes the electrostatic breakdown prevention circuit (2) is shown. M I S FETQ
n3 is the P-type well region 2. It is composed of a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 8 serving as source and drain regions, and a pair of n'-type semiconductor regions 11. M I S F E T Q n 3 is
It is configured almost the same as MISFETQs. MISF
ETQn+ (and Qn2) is formed by the P- type well region 2, the gate insulating film 6. Gate electrode7. sauce.

It is composed of a pair of n° type semiconductor regions 9 which are drain regions. M I S F E T Q n + ,
The 6p channel MI 5FETQp, each of which has a configuration substantially similar to the 1Ml5FETQ, is formed in an n-type semiconductor substrate l, and includes a gate insulating film 6, a gate electrode 7, and a gate electrode 7. It is composed of a pair of p° type semiconductor regions 18 which are source and drain regions.

The semiconductor area 9 is an input stage circuit! M I S FETQ
p and LDD structure M I S F E T Q n
Compared to the electrostatic breakdown voltage of 3, MI S FET
It is configured to lower the breakdown voltage (surface breakdown voltage or punch-through voltage) of the drain region or source region of Q n + and Q n2.

In other words, the semiconductor region 9 is configured so that the electrostatic breakdown prevention circuit (2) clamps the excessive voltage before the input stage circuit I causes electrostatic breakdown, thereby improving the electrostatic breakdown voltage. The present invention thus provides a semiconductor region 9 provided in the peripheral circuit portion of the SRAM in order to increase the electrostatic breakdown voltage.
Another feature of the device is that it is actively provided in the memory cell portion that constitutes the internal circuit.

Note that MISFET Qn+ and Q na are formed in well regions 2 that are different from the well region 2 for forming memory cells and are independent from each other. Further, the channel stopper region 4 is formed under the field insulating film 3 in the well region 2 .

17 is an aluminum layer formed in the same process as the data line (DL) 17. Although the resistor R3 is not shown in the figure,
It should be formed in the same region as the second layer polycrystalline silicon film 14A (portion into which impurities are introduced).

Although not shown in Fig. 4, 1M I S FETQnl
train area and M L S F E T Q n
Only the second source region may be formed of the semiconductor region 9.

In addition, a region formed in the same process as the p° type semiconductor region 5 in the memory cell is M I S F E T Q n
+ and/or may be formed below Q n 2. Due to this.

Furthermore, the breakdown voltage can be reduced.

Next, regarding the manufacturing method of this embodiment, Figs.
This will be briefly explained using figures (cross-sectional views of main parts of memory cells in each manufacturing process).

First, a P-type well region 2 is formed in an n-type semiconductor substrate 1 made of single crystal silicon.

Thereafter, a field insulating film 3 and an n-type channel stopper region 4 are formed on the main surface of the well region 2 between the semiconductor element forming regions.

Then, as shown in FIG. 7, a gate insulating film 6 is formed on the main surface of the well region 2 in the semiconductor element formation region.

After the step of forming the gate insulating film 6 shown in FIG. 7, a P' type semiconductor region 5 is formed on the main surface of the well region 2, as shown in FIG. The semiconductor region 5 mainly includes:
Using the field insulating film 3 as a mask for introducing impurities 1
For example, it is formed by introducing boron of about 1013 [at, am, q/cm''1] by ion implantation with an energy of about 300 [KeV].

After the step of forming the semiconductor region 5 shown in FIG. 8, a predetermined portion of the gate insulating film 6 is removed and a connection hole 6A for direct contact is formed.

After that, a gate electrode 7 is formed on a predetermined upper part of the gate insulating film 6, and a word line 7A and a reference voltage wiring g7B are formed.
form. Each of the gate electrode 7, the word 1it7A, and the reference voltage wiring 7B is made of a polycrystalline silicon film 7, for example.
It is composed of a polycide film in which a high melting point metal silicide film 7b is formed on top of a. The polycrystalline silicon film 7a is formed by, for example, CVD, and the high melting point metal silicide film 7b is formed by, for example, sputtering. Although not labeled, impurities diffused into the polycrystalline silicon film 7a to reduce the resistance value diffuse into the main surface of the well region 2 through the connection hole 6A.
n used as part of the source or drain region
A semiconductor region (not numbered) of the type is formed. This n-type semiconductor region is the semiconductor region 5
It is also possible to further improve the amount of charge accumulation that serves as information by diffusing deeply enough so as to come into contact with the information.

As shown in FIG.
A mold semiconductor region 8 is formed. The semiconductor region 8 mainly uses the gate electrode 7 and the field insulating film 3 as a mask for impurity introduction.

It is formed by introducing an n-type impurity (for example, phosphorus) by ion implantation.

After the step of forming the semiconductor region 8 shown in FIG.
As shown in FIG. 0, a semiconductor region 9 is formed on the main surface of the well region 2 (semiconductor region 8) in a portion where the amount of "ε" charge accumulation serving as information is improved. M I S for clamping electrostatic breakdown prevention circuit■
The train region and source region 9 of FETQn+rQn2 are formed in the same manufacturing process. The semiconductor region 9 is indicated by the reference numeral 9 in FIG. 3 and FIG. It can be formed by introducing mold impurities. In this step of introducing n-type impurities, regions where n-type impurities are not introduced (other than the region marked with 9 and surrounded by a dashed line) are covered with a mask such as a photoresist film. . Semiconductor region 9 has a deep junction depth of 1, for example 5XIO" [at
, oms/am21 by ion implantation with an energy of about 50 [KeV].

In this way, the semiconductor region 9 used as the drain region of the driving MISFETQ is replaced by the clamping MISFET
By forming the drain region and source region of Qn+ and Qn2 in the same manufacturing process.

Impurity introduction steps can be reduced.

Further, although not shown, the drain region of the Ω channel MISFET constituting the output stage circuit is also formed of the semiconductor region 9.

After the step of forming the semiconductor region 9 shown in FIG. 1O, an impurity introduction mask 10 is formed on the side of the gate electrode 7. The impurity introduction mask 10 can be formed, for example, by subjecting a silicon oxide film formed by CVD to anisotropic etching such as reactive ion etching.

After this, as shown in FIG.
n used as a source region or a drain region on the main surface of the well region 2 on the side of the gate electrode 7 with n
A type 1 semiconductor region 11 is formed. The semiconductor region 11 is
For example, it is formed by introducing arsenic of about 10'' [atonIs/Cll12] by ion implantation with an energy of about 80 [KeV].

Note that the semiconductor region 11 may be formed before the step of forming the semiconductor region 9. Although not shown in the figure, the P-channel MIS FETQ of the input stage circuit I mentioned above
A p-type semiconductor region 18 used as a p-type source region and a p-type train region is formed after the step of forming the semiconductor region 11.

After the step of forming the semiconductor region 11 shown in FIG.
An interlayer insulating film 12 is formed, and a predetermined portion of the interlayer insulating film 12 is formed.
is removed to form the connection hole 13.

Thereafter, as shown in FIG. 12, a power supply voltage wiring 14A and a high resistance load element 14B are formed on the one-layer insulating film 12. Power supply voltage wiring 14A.

The high resistance load element 14B is formed by forming a polycrystalline silicon film over the entire surface of the interlayer insulating film 12, and by introducing or not introducing an n-type impurity into the polycrystalline silicon film to reduce the resistance value.

After the step of forming each of the power supply voltage wiring 14A and the high resistance load element 1413 shown in FIG.
．． Connection holes 16 are formed one after another. Then, as shown in FIGS. 3 and 4, the M I S
A data line 17 is formed on the interlayer insulating film 15 so as to be electrically connected to one semiconductor region 11 of the FETQs.

By performing these series of manufacturing steps, the S
RAM is completed. Note that a protective film such as a passivation film may be formed after this.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments. However, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, one aspect of the present invention is the drain region of the clamping MISFET of the electrostatic breakdown prevention circuit H, and the drain region of the MISFET for driving the memory cell.
The deep junction drain region (semiconductor region 9) of ISFETQ may be formed in separate manufacturing steps.

Further, the present invention provides an S f<AM
It can be applied to

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are briefly explained below.

MTS FET for transfer and MISFET for drive
In SRAM, which constitutes a memory cell with T,
Transfer MIS that does not contribute to an increase in the amount of charge accumulation that serves as information
The junction depth of the drain region of the driving MISFET is configured to be deeper than the source region or train region of the FET,
By configuring a high concentration semiconductor region that is in contact with the drain region of the driving MISFET and has a conductivity type opposite to that of the drain region under the drain region and channel forming region of the driving MISFET, the drain region By increasing the pn junction capacitance with the high-concentration semiconductor region and increasing the amount of charge storage that serves as information, it is possible to prevent soft errors and to
Since a potential barrier region for minority carriers can be formed in the semiconductor region at a position that does not affect the threshold voltage of the semiconductor device, soft errors can be prevented and electrical reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing a memory cell of an SRAM which is an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram showing an input section of SRA:VI which is an embodiment of the present invention. 3 is a plan view of a main part showing a memory cell of an SRAM which is an embodiment of the present invention, and FIG. 4A is a sectional view taken along the line IV--IV in FIG. 3. FIG. 4B is a cross-sectional view showing the configuration of the peripheral circuit of the SRAM. 5 and 6 are plan views of main parts of the memory cell shown in FIG. 3 in a predetermined manufacturing process. Figures 7 to 12 show an SRA which is an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of each manufacturing process of a memory cell of M. In the figure, 2...well region, 6...gate insulating film, 7
...Gate electrode, 7A...Word line (WL), 7B
.

Claims (1)

[Claims] 1. A transfer MISFET and a driving MISFET are provided on the main surface of a first semiconductor region of a first conductivity type that is electrically isolated from other regions.
The semiconductor integrated circuit device includes a memory cell configured with a flip-flop circuit having an SFET, and the transfer MIS does not contribute to an increase in the amount of charge accumulation serving as information.
The drain region of the driving MISFET is formed with a deeper junction depth in the main surface of the first semiconductor region than the source region or the drain region of the FET, and the driving MISFET
A second semiconductor region that is in contact with the drain region of the driving MISFET and has the same conductivity type as the first semiconductor region and a higher impurity concentration than the first semiconductor region, on the main surface of the first semiconductor region below the drain region and the channel forming region. A semiconductor integrated circuit device comprising: 2. The second semiconductor region increases the amount of accumulated charge that serves as information, and also constitutes a potential barrier region for minority carriers in the first semiconductor region. Semiconductor integrated circuit device. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the second semiconductor region is configured at a position that does not affect the threshold voltage of the driving MISFET. Device. 4. The second semiconductor region covers substantially the entire area of the memory cell.
4. Each semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided on a main surface of a semiconductor region. 5. Claim 1, wherein the memory cell constitutes a static random access memory.
Each of the semiconductor integrated circuit devices described in Items 1 to 4. 6. The drain region of the driving MISFET is formed in the same manufacturing process as the source region or drain region of the clamping MISFET of the electrostatic breakdown prevention circuit provided between the external terminal and the input stage circuit. Each semiconductor integrated circuit device according to claims 1 to 5. 7. The second semiconductor region is a MISFE for transfer and driving.
7. Each of the semiconductor integrated circuit devices according to claim 1, wherein each of the semiconductor integrated circuit devices is configured in a self-aligned manner with respect to a field insulating film that electrically isolates each of the Ts.