JPS5954260A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent software errors of a static RAM comprising an IGFET, by coating the bottom of a memory node layer of memory cells by a P layer or an N layer. CONSTITUTION:N<+> layers 26, 13, and 27 are provided in the P layer of an N type substrate as specified and operated as a memory node. An ion implanting layer 9 is selectively formed so as to cover the bottoms of the N<+> layers 26, 13, and 27. For this purpose, at first, memory cell forming region is provided in a field oxide film 8, and then the ion implanting layer 9 is provided. Heat treatment for a long time period at the time of forming the thick oxide film is avoided, and the rediffusion of the layer 9 is prevented. Thus software errors can be sufficiently prevented and the adverse effect on the FET characteristics is prevented. For example, in the implantation into a memory cell forming part X1, a resist mask is provided, and the ions are implanted into only the memory node connecting a driving FET Q2 and an FET Q4 for transmission. Thus the implantation to the unrelated nodes for peripheral circuits, data lines, and the like are avoided. By this method, a highly reliable static RAM is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device and a manufacturing method thereof;
In particular, 11-shi prevents the occurrence of soft errors caused by alpha rays,
Hor1 edge gate field effect transistor (MIS)
11
．． A M (StaticR, andom Arc
ess Memory (hereinafter referred to as S-nAM) and its manufacturing method.

Memory cells in S-R, A, and M, especially silicon memory cells, are susceptible to α particles if they are exposed to radiation [a), and trace amounts of i are contained in the ceramic package phase or lid side that seals the memory element.
α released from natural uranium (U), etc.
Due to the incidence of the beam into the tesog, a large number of costron-hole pairs are generated in the substrate, and the emitted particles move through the substrate and are accumulated in the memory cell (t+ -C) (W f'14 (π
This causes the phenomenon 5 to occur, causing the memory to become more active. This is what is called a soft error. As the memory size (number of bits) increases, the area occupied by the memory cell becomes smaller, and the amount of information stored in the memory cell becomes smaller, causing soft errors. To prevent this, it is possible to coat the surface of the semiconductor tape with a polymeric material such as polyimide resin, or to form a P-type well region in the substrate using a PN junction. The 1r1 wall of the PN junction seals the deuterons generated by α rays in the substrate and returns them to improve the soft error strength.

Formation of this P-type well region improves the soft error strength, but as mentioned above (as the memory size becomes thicker, soft errors occur). 1st, the S of a distinguished guest of 64 Kbit or more
5-11A memory or 5 is not enough (
・I found out.

On the other hand, in order to prevent soft errors caused by such alpha rays, the present inventors, in addition to forming a
We considered forming a P+ type semiconductor region under a partial region of the storage node (drain region). It also constitutes a memory cell. We considered surrounding all the elements in the f+ rewell with a P type semiconductor device 1).

However, in the former method of forming a P type semiconductor region under the drain region as a storage node, the P+
Since the process of forming a type semiconductor region is adopted, the process is complicated, the mask alignment margin for forming the P type region is tight, and the TE shielding effect is also reduced due to the size of forming the P'' type semiconductor region in a part of the storage node. The problem is that it is insufficient and has little soft error reduction effect.

Also, do not configure the latter memory cell a) All elements are P+ type half 2! When surrounded by a q-type region (b:r in the 5 method, the corresponding ■) in the peak process) + type semiconductor region) When a field insulating film is formed after the z formation (the 5 method is obsolete.For this reason, During the formation of the field insulating film, the P+ type semiconductor region is re-diffused due to long-term annealing.
The element characteristics change due to Kozai 1, for example,
City 11゛ro-゛shift, change the fill-value of the element! "j
In addition, in this case, the P+ type semiconductor region is diffused by 1J, resulting in a region with a predetermined impurity concentration being reduced to 1(), which is a problem to reduce the soft error effect. 1 point is power)ro.

An object of the present invention is to form a region for preventing the occurrence of soft errors due to alpha rays by a simple method.

The present invention will be explained below with reference to embodiments shown in the drawings.

1 to 16 show cross-sectional views of each step of the manufacturing process of AM according to the present invention. The explanation will focus on one transistor that constitutes the peripheral circuitry related to the memory cell array.

In each figure, region X shows a partial sectional view of each process for obtaining the memory cell M-CE L shown in FIG.
3 shows partial cross-sectional views of each process for obtaining a P-channel MISFET constituting a peripheral circuit such as the following.

FIG. 1 shows a P-type well region 3 in the region X of the semiconductor substrate J.
An oxide film 4 is formed on the region, and the X of the substrate 1 is
A state in which oxide film 2 is formed in two regions is shown. Next, we will explain the process used to obtain the semiconductor device whose cross section is shown in FIG.

A semiconductor substrate, for example, an N-type crystalline silicon substrate having a (100) crystal plane and a specific resistance of 8 to 2 Ωαn, is prepared, and an N-type impurity, for example, phosphorus, is added to the entire main surface of the silicon substrate 1. , for example by ion implantation, preferably implantation energy]-25KeV, dose 3X 10
Introduced at 12 atoms/tan24). One trick is to form an N region by implanting N-type impurities in advance, and form a channel stopper to prevent 'r' from occurring. It's because I can do it. Next, a silicon oxide film (Si
20 film) 2, and then selectively form a photoresist film on the 5tO2 film to remove the Sin film over the area where the well is to be formed. Then, the 5102 film is etched using the photoresist film as a mask. Next, with the first photoresist film remaining, p jq
P-type impurities are introduced to form the ll well. The preferred method of introduction is ion implantation force. In addition, boron (13), for example, is preferable as the P halogen impurity, and in this case, the implantation energy is 75i (eV, and the dose is preferably 8 x 1012 atoms/river2. At this time, the boron is used so that the photoresist film remains. On the other hand, the phosphorus introduced into the silicon substrate 1 compensates for the concentration of phosphorus that was previously implanted into the entire surface and forms a P-type well. Enough to form.

After removing the photoresist film, the P-type impurity selectively introduced into the silicon substrate 1 is thermally diffused at a temperature of about 200° C. to form a well region 3 as shown in FIG. is formed and increases. At this time, a thin silicon oxide film 4 is formed on the surface of the silicon substrate 10. In this well region 3, a memory cell as shown in FIG. 2() is formed.

Next, the steps shown in Figure 2 and below will be explained.

(Process for forming field insulating film and channel stopper) Remove all the oxide film on the silicon substrate 1 shown in FIG. .

Next, as shown in FIG. 2, an oxide film (S102 film) 5 with a thickness of about 50 OA is formed on the surface of the silicon substrate 10 by thermal oxidation.
form. And then add one pile of oxygen to this -] second.
・An insulating film (oxidation-resistant film), for example, Si, N4 film 6, is formed by chemical vapor reaction method (Chemical Vapor 1) epo
location.

(hereinafter referred to as CVD method) to a depth of approximately 1,400 mm. This Si, N4 film 6 is used as a mask for selectively forming a field insulating film to be described later.

Note that the S+02 film 5 should be formed for the following reason. That is, if the Si, N4 film 6 is directly formed on the surface of the silicon substrate 10, crystal defects will occur on the surface of the silicon substrate 10 due to the heat 9 caused by the difference in expansion coefficient ρ between the two. 5 to protect against 1
io211ω5 is formed at the same time.

Next, in order to complete the mask for forming a field insulating film, which will be described later, a fumetresist film 7 of Si, N,
4 selectively formed on the film. That is, the photoresist film 7 is formed in a region other than the region where the field insulating film is to be formed. Then, using this photoresist 7 as a mask, the 5L3N4 film 6 is etched by plasma etching to form a mask for field isolation and edge film formation. reactor.

With the photoresist film 7 remaining (-), P-type impurities are introduced into the silicon substrate 1 to form a channel stopper. As a method of introduction, for example, ion implantation is used. In that case, the P-type impurities are In the region where the photoresist film 7 remains, it does not reach the 5i02 film 5 and the silicon substrate 1, while in the region where the surface of the SIO2M'k 5 is exposed (. 5 and reaches the inside of the silicon substrate 1.

As the above-mentioned type (1) impurity, boron fluoride B F is preferable. The implant energy was 30 KeV and the dose was 5
X1013 atoms 10In2 are preferable.

Boron ions implanted into the P-type well form a P+-type region and serve as a channel stopper. On the other hand, the boron ions implanted into the N-type silicon substrate 1 are compensated for by phosphorus, that is, N phosphorus impurity introduced by the phosphorus implantation shown in FIG. Therefore, this region is an N-type region and 1
．． It is clear that there is a channel stopper for NWV.

(Field insulating film forming step) After removing the photoresist film 7, as shown in FIG. 3, the surface of the silicon substrate 10 is selectively thermally oxidized in an oxidizing atmosphere at about 1000° C. to a thickness of about 950 OA. A field insulating film 8 is formed. At this time, the oxidation-resistant film should be 5il.
Since the N4 film 6 does not reverse oxygen, S I! I N,+
The silicon 11m below is oxidized to Jt7':1.

During this heat treatment, the above-mentioned channels and brim are stretched and expanded under the surface of the field insulation IK'+. 7.
A tethered buckwheat with the desired depth is formed in the first filter.

(Not shown) (Surface oxide film removal process) The SI3N4 film 6 is heated with hot phosphorus (IT, PO), for example.
4), in order to obtain a clean gate oxide film, the 5i02 film 5 on the surface of the silicon substrate 1 is first removed as shown in FIG.
) to remove the 5102 film 5 and expose the surface of the silicon substrate 10 where the field insulating film 8 is not formed.

A plan view of M-CET in this state is shown in FIG.
.

In other words, the cross-sectional view of X, F-X in FIG.
It is shown in area X1 of the figure.

(Step of Forming Impurity Implant Layer) An impurity implant layer 9 is formed as shown in FIG. 5 on the surface of the silicon substrate shown in FIG. In the embodiment shown in FIG. 5, P-type axes were used as impurities.

Ion implantation is the most effective method of infiltration. Also, 1
) As the M'l impurity, for example, boron (t-tri) is preferable, and the implant energy key in this case is 125 KeV.
姐'L 10 ''' ~ 2 x 10 ''m (/''2 is good.

This ■)-type impurity implant layer may also be formed on the field insulating film (・).

In this way, the present invention forms a P-type impurity implant layer after forming a field insulating film. By forming this implant layer, it is possible to prevent the occurrence of soft errors due to alpha rays. Preventing the occurrence of α-ray soft errors by this imprint layer 11 will be described later.

(Gate insulating film formation process and private chamber pressure control process) In an oxidizing atmosphere of approximately 1000"C, the surface of the silicon substrate shown in Fig. As shown,
A gate insulating film 10 having a thickness of about 4 ooA is formed by thermal oxidation. This gate insulating film 1 (1) is in contact with the gate insulating films of all MISFETs formed on the silicon substrate 1.

Next, in this state, ignition is carried out with P-type ion f]. Koga is all M (S F E T threshold inn)
'? This is done to determine the H pressure. As the P-type impurity, boron (B) is preferable (.The energy including tJ is: toKev, the dose amount is 5.5
, f) "Atoms/1ytn2 (・) This dose meter changes depending on ■, 1. This ion implantation is performed on the entire surface without using a mask at all. Therefore, All N channels MI S l"T': T is the same σ] (・Value pressure Vtl+'?
Channel M I S F E T is the same threshold ↑■
1. C.

(During direct contact hole formation, a contact hole for direct connection between Pi ηλ and polycrystalline silicon group &'I is formed on the 5I02 film IO to form a so-called direct contact hole. Photoresist film 1 + 'G: ; is selectively formed. Then, using this photoresist film convex 11 as a mask, as shown in FIG. to expose the surface of the silicon substrate 1,
Dire Tatokon, 9ri) Hall CH,. . form 1-
reactor. This CJI. . (゛↓MI shown in Figure 20
S F E '1. 'Q2-Q4: I·l and high mechanical resistance, connection part with polycrystalline silicon R24).

(T-culm for formation of row body layer) After removing the photoresist film 1, 12 first conductor layers are formed on the entire surface as shown in FIG. A polycrystalline silicon layer doped with impurities is used as the -j-N body layer.

First, a first polycrystalline silicon layer 12 having a thickness of about 3500 Å is formed over the entire surface by CVD. Next, in order to reduce the specific fire resistance of the first polycrystalline silicon layer 12, N is applied to the entire surface.
Type impurities, such as phosphorus, are introduced by diffusion.

At this time, a direct contact hole CH, is formed from the single polycrystalline silicon layer 12. . Through this process, phosphorus is also diffused into the silicon substrate 1, and an N-type region 13 is formed.

These N-type regions are diffused to a desired depth in a later heat treatment step. Region 1:3 is M ) S shown in FIG.
Connection between F, T, TQ and Q: Row 5, (P-bar polycrystalline silicon layer treated with phosphorus as described above) 2nd row, 9th row As shown in the figure, the gate electrode is etched into the desired shape by plasma etching with high accuracy (1/1.lfi, word width).
A gate electrode 17 is formed in direct contact with the region 13.Subsequently, Sin, IIφlO are etched in the same shape))'-),l(6, and the edge films 18 to 20 are formed.At this time, As shown in FIG. 9, the surface of the silicon plate 1 is selectively exposed.

(Step of Forming Source/Drain Regions and Heath Extracting Layer) A mask is formed to form P type source/drain regions. As this mask, for example, a 5I02 film 21 selectively formed with a thickness of about 15 OrlA by the CVD method may be used. In other words, the region where the N-channel MTS FET including the memory cell is formed is S
iQ, by the membrane 21.

Then, in this state, a pi impurity is introduced by the diffusion method by inverting the tube. Boron is preferably diffused into the P channel M r SF as shown in FIG. 10.
I': '? Source/drain regions 22 and 23 are formed.A thin oxide film (not shown) is formed on the surface of the silicon substrate 10 along with the heat treatment during this diffusion.

(Source/drain region and emitter region forming step) The 5102 film 21 and the thin film (by removing the oxide film), -
After that, a new mask 24 is formed in order to form N+ type source/drain regions. As this mask, for example, a 5I02 film 24 selectively formed to a thickness of about 150 (LX) by CVD method is used. The formed region is covered with a Sin film 24.

Then, in the state shown in FIG. 11, N-type impurities are introduced by, for example, a diffusion method. As this N-type impurity, phosphorus (P) is preferable. Phosphorus diffuses into the silicon substrate 1! 1, source/drain regions 25 to 28 of the N channel MT SFR1' are formed. In addition, during the Wpt treatment during this diffusion (1'), an N(-oxide film (not shown) is formed on the surface of the silicon substrate 10. In this state, the memory cell has a plane of I-CI', L. The diagram is shown in FIG. 18.The X, L-X, and cut cross-sections of FIG.

(Contact hole formation process) After removing the above-mentioned Sin, film 24 and lake (oxidation I11'), as shown in FIG. form. At this time, silicon substrate 1 and polycrystalline silicon layer 14
Since the oxidation rate is different between 17 and 4), SiO of about 1 (J!p-
, the polycrystalline silicon layer 14 to 170 has a thickness of about 400
A SI Q 2 film with a thickness of A is formed.

Next, apply a new CV l) N7: approximately 1500 to the entire surface.
An S + 02 film 30 having a thickness of Aσ) is formed. This 5l
(The film 3 ( ) is provided for insulation between the silicon substrate and a second conductor layer to be described later).

Next, a two-four resist 1lrJ is applied on the S+02 film 30.
(not shown) is selectively formed, and the S + 02 film 30 and the Sin film 29 are sequentially etched using a mask of 1 and 1 to form a contact hole (-4'').ξ
0) The contact hole is opened for connection between a second conductor layer, which will be described later, the first polycrystalline silicon layer 17, or a semiconductor region formed in the silicon substrate 1, respectively.

11o, the thickness of the 5in2 film 29 is 11φ, and as mentioned above, the thickness of the polycrystalline silicon layers 14 to 17 is approximately 300^,
Approximately 100. Different from A. Therefore, it is necessary to perform etching until the sIo film on the polycrystalline silicon layers 14 to 17 is completely etched.

At this time, as the enching liquid) T F −+−NH,
It is preferable to use F. In other words, this F-Bunda solution has no effect on silicon, so
Don't be naughty (・.

(Second conductor layer forming step) As shown in FIG. 13, a second conductor layer 31 is formed on the entire surface. A polycrystalline silicon layer doped with a 1-(.', l-polymer) is used as the second solution layer.

First, a second polycrystalline silicon layer 31', CV I
) method to form approximately 2 (old) 60 9 - (-). On this second polycrystalline silicon layer 31, as will be described later, a third conductor layer and a silicon 1-4-1 silicon layer are formed. It is also used for interconnection with the semiconductor region or the first polycrystalline silicon layer 17 in the 20th section, the source voltage supply avCc-, IJ and Square loading machine resistance It,.

Also use it as R7 i'1. reactor.

(Resistor formation process) Next, as shown in FIG. 13, CV 1. ) Approximately 1500. J length of A) Si02 film 32~:34
Fire 1 so? ; Formed in folds, the second polygonal irises? ) Silicon layer: 31 is partially removed.

In this state, in order to reduce the resistivity of the second polycrystalline silicon layer 31, it is introduced by, for example, a phosphorous diffusion method.

At this time, phosphorus is not introduced into the second polycrystalline silicon layer in the portion covered by the Si(') films 32 to 34 (. Therefore, the polycrystalline silicon, which still has a high specific reluctance, is partially What will be the remaining state?The phosphorus diffused into the second polycrystalline silicon layer 31 will be diffused to some extent in the plane direction, but the Sin and films 32 to 34, which serve as a mask, are set up with this in mind. has been done.

(Second Conductor Layer Selective Removal Glue) After removing the Sin films 32 to 34, the second polycrystalline silicon layer 31 is etched into a desired shape to form electrodes 38 to 41 as shown in FIG. Go form.

'r [pole 40. 41ha Pf + NekM I SF ET
(7) The pole 39 is used for connection to the source and drain fan regions.
Used as an electrode for SFETQ4. 1 pole 38
(vC6-■,) is the high-resistance polycrystalline silicon layer 35 ([
L2) via M Ding SJ'ETQ+, Q4's 7-
The light is attached to the first polycrystalline silicon #17 through a so-called direct contact that is directly connected to the drain region.

(Interlayer A! Edge film forming step) As shown in FIG. 15, an interlayer insulating film 42 is formed on the entire surface. Interlayer P #
It is formed to a thickness of 10A. This PSG film 42 is supplied with a third conductor layer, which will be described later, and η) a double-striped silicon layer, especially a power supply voltage V 1 . It is necessary as an interlayer insulating film between the Tl electrode 8 and the (CoC) layer.

Next, a photoresist film (not shown) is selectively formed, and using this as a mask, I) the S G/II 42 is etched to form a contact hole.

−□□ □ □□ 輛ζ〜−−−−□−□□□−１□□
□ζ □-/ ,,, / //'7/'' 2/ /''77' , / 7, / 2/ Two (Third conductor layer forming process) As shown in Fig. 16, the third conductor H1143-45
selectively formed. As a third conductor layer.

For example, aluminum, which is P-type with respect to silicon, (A
-6) is preferred. The aluminum layers 43 to 45 are formed to a thickness of about 8000 Å by vacuum evaporation.

At this time, the electrode 4 made of the second polycrystalline silicon layer with high resistance
Inside the 0.41 mm aluminum oxide is diffused, resulting in a conductor layer with a small ratio of P type (electrode 4:3 is shown in FIG. 20), which is used as a data line.

FIG. 19 shows a plan view of M-CE L in this state. That is, a cross-sectional view taken along lines X, -X, and Q in FIG. 19 is shown in region X in FIG.

FIG. 20 shows a schematic layout of the memory cell section formed by the above process, and FIG. 22 shows an equivalent circuit diagram of the memory cell section.

In the layout pattern diagram of the memory cell M-CELL in FIG. 20, the quadrupled portion (A-
This is the area occupied by B-C-D) F-CEL.

First, in the IC chip, semiconductor regions 5R1-8It and 1, which function as wiring and the source/drain of the MISFET, are arranged as shown in the figure.

This IC chip has a first conductor layer (polycrystalline silicon layer) K through an insulating film as shown by the thick solid line.
Therefore, wa・-1・' ＃、! il W and gate 1E
The poles G 1 + G2 are formed. word line lol
The VL semiconductor region SR,,S, as well as the transmission MISFETQ3 and the semiconductor region SR,.

MISFET for transmission along with 5rta
It constitutes Q4. It's a matter of Gate'fiI, YG.
1 is the semiconductor region SR, , Sf (3) and the semiconductor region (iJ)
] V1. I SFh: T Q I , and the gate electrode G2 is a semi-n1 body region SR.

Both SR and 7 constitute driving M and 15FETQ2, respectively. Note that the gate electrode G is connected to the connecting point N2 of the gate electrode M I S F E T Qt and IVIISFETQ.
It is in direct contact with the semiconductor region SR6 which is electrically connected to the semiconductor region 4.

Word line W and gate electrode G, , G2-t, )1
, as shown by the thick dotted line, the insulating film is closed and the second conductive layer (polycrystalline silicon layer) K is connected to the power supply line ■c
cI-', load resistance R, , R, and connection point N, , N,
The wiring between them is integrally formed.

That is, one end of the load resistors R, , R, is integrally connected to the branched power supply voltage supply line VcC-L. The other end of the load resistor R1 is connected to the gate electrode G2 at the connection point N6, crosses the gate electrode G1 as a wiring, and connects the MISFET Q+ and M at the connection point N and VC.
It is connected to the semiconductor region SRt, which electrically connects the ISFETQs.

The cross-coupling shown in FIG. 22 can be achieved by the intersection of the wiring (second conductor layer) between the connection points N, , N and the gate electrode Gl (first conductor layer). On the other hand, the other end of the load resistor R7 is connected to the gate electrode G at a connection point N2. As will be explained later, the above-mentioned load resistance IR, is determined by controlling the introduction of impurities into the first layer conductor J@, that is, the polycrystalline silicon layer, to the - part of the polycrystalline silicon layer. It is formed.

Power supply voltage supply line■. C-Ll load JI (anti-■(1,,I
'? ,.

And on the wiring between the connection points N1 and No.
) (Aluminum layer) to ground 71 (Iku) l'F
V6 B-L, data line and D are parallel to each other, and word line W and power supply voltage supply line ■. It is formed to directly parent o-L. MISF at the ground potential supply line V8S-Lil-f connection point N.
It is connected to a semiconductor region SR3 that electrically connects ETQ and MISFETQ2, and is further in contact with a semiconductor region (well region) SR6 at a connection point H□.

Data lines D, J) are fully connected to semiconductor regions SR, SR, at connection points N, , N4, respectively.

The circuit diagram of the above memory cell M-CE L L is shown in the 22nd page.
As shown in the figure. This memory cell is a flip circuit that cross-couples the input and output of a pair of inverter circuits connected in series and consisting of load resistors R, , R2 and driving MISIi"ET (insulated gate field effect transistors) Q, , Q. M, I 5F for flop and pair of transmission gates
It consists of ETQs and Q4. The flip-flop is used as an information storage means, and the transmission gate is used as an address means for controlling the transmission of information between the flip-flop and the complementary data line pair D. Its operation is controlled by the row decoder R- D.C.
is controlled by an address signal applied to a word line W connected to the

FIG. 21 shows the memory cell M-CEL or I shown in FIG.
A layout pattern 4 of a J-9 memory array M-ARY arranged in plurality in a C chip is shown.

One M-AIζY' kl indicated by a dashed double-dashed line:
The M-CEL (A-B-C-D) of the bits shown in FIG. 32 in the line direction, 1 in the vertical direction and the data line direction
2828 pieces have been distributed.

These M-CELs are arranged in the following manner.

First, the l-bit 8tI −CE L shown in FIG.
Based on the layout pattern of M-, CJ L1 to M-CJ L4 as shown in FIG.
The basic blocks of the ARY configuration are -C.

In this basic block, M-CEL2 adjacent to M-CE L1 in the horizontal direction is its M-CE; L
M-CEL3, which is arranged line-symmetrically with M-CEL1, and which is vertically aligned with M-CEL1, is
They are arranged in a state rotated by 180 degrees with respect to I. Then, for M − CE L 3, the horizontally adjacent M
-CEL4 is arranged line-symmetrically with M and -CEL3.

These basic blocks are successively arranged vertically in a length of 41'·λ to form one M-A Ft Y of 11·-. That is, as shown in FIG. 21, 16 basic blocks are arranged in the horizontal direction, and 64 basic blocks are arranged in the vertical direction in such a manner that the four parts of the basic blocks and the convex parts that fit each other are sandwiched and are appropriately spaced.

Ground potential supply lines V88-L, shown in FIG. 20, are arranged on both sides of M-ARY. You're talented, M-A11 Y
On both sides of the outside are power supply voltage supply lines 3, which are made of a third conductor layer and run parallel to the ground potential supply line VSS-L. -L
INEs are arranged. This power supply voltage supply line■
cc-LINE is connection point N. , it is connected to the power supply voltage supply line ■cC-L shown in FIG.

In the 5-RAM memory cell according to the embodiment of the present invention described above, MISFETQz, which serves as a storage node forming a part of the storage capacitor C8 shown in FIG.
A peak region 9 with high impurity concentration is located below the N1 type drain and source region 2G, 13.27 of Q4 (Ql, Qs) at a position slightly deeper than the depth of these regions.
Ion inburan l-8 to have P (P+ type region)
49 is formed.

Therefore, due to the peak region 9P having a high υ impurity concentration as compared to the P-type well 3, the N-l-type region 26 serves as a storage node.
．． 13.27 and the PN that the P-type well 3 forms with the substrate 1.
A potential barrier can be formed between the high impurity concentration region 9P and the junction. This potential barrier prevents electrons generated by α rays from diffusing into the storage node.

Moreover, at this time, the MIspli of the memory cell surrounded by the thick field insulation [8]
'i' formation region (formed so as to cover the entire bottom of the By forming the layer so as to cover the bottom of the region (forming region), it is possible to significantly reduce the rate at which electrons generated by α rays reach the source and drain portions (storage nodes) of the MISI"ET portion constituting the memory cell.

Of course, in the present invention, since the memory cell is formed in the P-type well, α
This reduces the inflow of electrons into the well due to the rays.

Furthermore, according to the present invention, the P-type well is in instant contact with the N+-type storage node, source, and drain regions 26, 13, and 27 that constitute a part of the storage capacitor C8 shown in FIG. Since the region is made highly doped by the ion implant layer 9, the capacitance value of the storage node capacitor formed by the N'1' type source and drain regions can be increased. By increasing the capacitance value, it is possible to further reduce the adverse effects caused by noise charges caused by α rays.

In addition, in the soil ftL example, after the field insulating film is formed,
Although an example of forming the impurity implant layer 9 has been shown,
After forming the gate electrodes 14, 16, etc., using the first polycrystalline silicon shown in FIG. 9, an impurity/implant layer may be formed. The former power is preferable because it allows you to secure a good imbrandt. Dimension C1 The above embodiment shows an example in which a P-type impurity impurity layer is formed, but an N-type impurity implant layer may also be formed, and this stage also uses the above-mentioned P-type impurity implant layer. A similar effect can be obtained.

In the manufacturing method according to the present invention, the formation of the impurity implant layer 9 that acts as an α-ray prevention region is performed using the previously formed thick field insulating film 8 surrounding the memory cell formation region as a mask. No special mask formation is required for layer formation. this is,
Simplify the process.

Furthermore, in the manufacturing method according to the present invention, the ion implant layer 9 for preventing alpha rays is formed after the thick field oxide film 8 is formed in advance to separate the element forming regions. The ion implant layer 9 can be formed while avoiding the heat treatment step for a length of IIh that is required during film formation.

Therefore, it is possible to prevent the deformation (re-diffusion) of the ion implant layer's grofile due to the oxidation heat treatment step V, thereby obtaining a sufficient soft nigma prevention effect, and at the same time, it is possible to prevent MiSFE T. Adverse effects on device characteristics can be prevented.

In the above-mentioned embodiment, the whole blood impurity implant Ki was formed in the element forming region XI of the memory cell. It is preferable to take care not to indiscriminately inject impurities 6 and implant wires into unrelated nodes such as wires and node wires. This will be explained based on FIG. 23. FIG. 23 is a simplified cross-sectional view of a modified example of the S-1 A, M device of the present invention which prevents the occurrence of soft errors due to alpha rays. As shown in FIG. 23, the ion implant region 9 can be selectively formed to cover the bottom of the N1 type region 26, 13, 27 which acts as a storage node. This makes it possible to avoid implanting impurities into nodes unrelated to storage nodes, such as data lines. That is, the above tfJ, M-CEL shown in Figure 22C
In the circuit diagram, it is preferable to implant ions only into the storage node N that connects the drive MISFET Q2 and the transmission gate MISFET Q4 to avoid implanting ions into unrelated nodes. Yes. Just N.

However, for ease of mask alignment and stability of V and control, ions may be implanted into a portion of adjacent nodes.

[Brief explanation of drawings]

The drawings show an example of the length hf[j of the present invention, FIGS. Plan view of memory cell, 1st
8 is a plan view of the memory cell shown in FIG. 11, FIG. 19 is a plan view of the memory cell shown in FIG. 16, FIG. 20 is a schematic diagram of the memory cell, and FIG. FIG. 20 is a layout pattern diagram of a memory array corresponding to FIG. 20, FIG. 22 is an equivalent circuit diagram 1 of a memory cell, and FIG. 23 is a sectional view showing another embodiment of the present invention. 8.Field insulating film, 25-28...N'' region 9...
Impurity implant layer. Agent Patent Attorney Susuki 1) Toriyuki, ha, ha,
・Ya;:'j' N (1) t', ! "4 ε) \ 1 71" (1 1st;・<I'+q , XJL (combined 1 () 1 I

Claims (1)

[Scope of Claims] 1) A type or N type impurity implant layer is formed under the semicircular region of the first node of the memory cell so as to treat the bottom surface of the semiconductor region. Characteristic semiconductor memory device. 2. A method for manufacturing a semiconductor memory device, which includes ion-implanting P-type or N-type impurities into a semiconductor region F of a storage node of a memory cell by masking at least a portion of a field insulating film.