JPH0340955B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device and a method for manufacturing the same, and in particular, to a semiconductor memory device and a method for manufacturing the same, and in particular to a semiconductor memory device that prevents the occurrence of soft errors due to alpha rays and is composed of an insulated gate field effect transistor (hereinafter referred to as MISFET). RAM (Static Random Access Memory
(hereinafter referred to as S-RAM) and its manufacturing method.

Memory cells in S-RAM, especially silicon memory cells, are susceptible to alpha particles contained in radiation, and are emitted from natural uranium (U), etc., which is contained in the ceramic package material and lid material that seal the memory element. When alpha rays enter the chip, a large number of electron-hole pairs are generated in the substrate, and the generated electrons move through the substrate, destroying the information (charge) stored in the memory cells and destroying the memory. This causes the phenomenon of malfunction. This is a phenomenon called a so-called soft error. As the memory capacity (number of bits) increases, the area occupied by the memory cell decreases, and the amount of charge as information stored in the memory cell decreases, making soft errors more likely to occur. To prevent this, it is possible to coat the surface of the semiconductor chip with a polymeric material such as polyimide resin, or to create a
A type well region is formed, and the potential barrier of this PN junction is used to repel electrons generated by α rays in the substrate to improve the soft error strength. Formation of this P-type well region improves the soft error strength, but as mentioned above, as the memory capacity increases, soft errors become more likely to occur.According to the inventors' studies, we found that It has been found that this is still not sufficient for S-RAM memory.

On the other hand, in order to prevent soft errors caused by such alpha rays, the inventors of the present invention have created a P ⁺ type semiconductor region under a part of the storage node (drain region) in addition to forming the P type well region. We considered forming a Furthermore, we considered surrounding all the elements in the P-type well constituting the memory cell with a P ⁺ -type semiconductor region.

However, in the former method of forming a P ⁺ type semiconductor region under the drain region as a storage node, in order to adopt the process, that is, the step of forming the P ⁺ type semiconductor region after forming the source and drain regions, The process is complicated, the mask alignment margin for forming the P type region is tight, and the shielding effect is insufficient just by forming the P ⁺ type semiconductor region in a part of the storage node, and the soft error reduction effect is low. There is.

Also, all the elements that make up the latter memory cell are
In the method of surrounding it with a P ⁺ -type semiconductor region, a method is adopted in which a field insulating film is formed after the P ⁺ -type semiconductor region is formed. Therefore, during the formation of the field insulating film, the P ⁺ type semiconductor region is re-diffused due to long-term annealing, which changes the device characteristics, for example, shifts the threshold voltage and The problem is that the design value of . Furthermore, in this case, as a result of re-diffusion of the P ⁺ -type semiconductor region, a region having a predetermined impurity concentration cannot be obtained, which reduces the soft error effect.

An object of the present invention is to form, by a simple method, a region for preventing the occurrence of soft errors due to alpha rays.

Hereinafter, the present invention will be explained with reference to the drawings and examples.

1 to 16 show cross-sectional views at each step of the S-RAM manufacturing process according to the present invention. In order to make the explanation easier to understand, the explanation will focus on one memory cell section and one transistor forming a peripheral circuit related to the memory cell array.

In each figure, region _X1 shows a partial cross-sectional view of each process for obtaining the memory cell M-CEL shown in FIG. 20, which will be described later, and region _X2 constitutes peripheral circuits such as data output buffer DOB. A partial cross-sectional view of each process for obtaining a P-channel MISFET is shown.

FIG. 1 shows a P-type well region 3 in an _X1 region of a semiconductor substrate 1 and an oxide film 4 formed on the region.
Also shown is a state in which an oxide film 2 is formed in the X ₂ region of the substrate 1. Next, the process to obtain the semiconductor device whose cross section is shown in FIG. 1 will be described.

A semiconductor substrate, for example, an N-type single crystal silicon substrate 1 having a (100) crystal plane and a resistivity of 8 to 12 Ωcm is prepared, and an N-type impurity such as phosphorus is implanted into the entire main surface of the silicon substrate 1, for example, by ion implantation. According to
Preferably, the implantation energy is 125 KeV and the dose is 3×10 ¹² atoms/cm ² . This can ^be achieved by implanting N-type impurities in advance.
This is because a channel stopper for preventing a parasitic MISFET can be formed by forming a region in advance. Next, a silicon oxide film (SiO ₂ film) 2 with a thickness of about 500 Å is formed on the surface of the silicon substrate 1 by thermal oxidation, and then the SiO ₂ film on the area where the well is to be formed is removed. Next, a photoresist film is selectively formed on the SiO ₂ film. Then, the SiO ₂ film is etched using the photoresist film as a mask. Next, with the photoresist film remaining, P-type impurities are introduced to form a P-type well. Ion implantation is preferred as the introduction method. Further, as the P-type impurity, for example, boron (B) is preferable, and in this case, the implantation energy is preferably 75 KeV and the dose is preferably 8×10 ¹² atoms/cm ² . At this time, the boron introduced into the silicon substrate 1 in the area where the photoresist film remains is sufficient to compensate for the concentration of phosphorus implanted into the entire surface and form a P-type well. It is.

After removing the photoresist film, the P-type impurity selectively introduced into the silicon substrate 1 was heated to about 1200°C.
The well region 3 as shown in FIG. 1 is formed by thermal diffusion at a temperature of . At this time, a thin silicon oxide film 4 is formed on the surface of the silicon substrate 1. In this well region 3, a memory cell as shown in FIG. 20 is formed.

Next, the steps shown in FIG. 2 and subsequent steps will be explained.

(Steps for Forming Field Insulating Film and Channel Stopper) All the oxide films on the silicon substrate 1 shown in FIG. 1 are removed to expose the clean surface of the silicon substrate 1.

Next, as shown in FIG. 2, an oxide film (SiO ₂ film) 5 having a thickness of about 500 Å is formed on the surface of the silicon substrate 1 by thermal oxidation. Then, on top of this, an insulating film that does not allow oxygen to pass through (oxidation-resistant film), such as Si ₃ N ₄ film 6
Chemical Vapor
Deposition (hereinafter referred to as CVT method)
Formed to a thickness of 1400 Å. This Si ₃ N ₄ film 6 is used as a mask for selectively forming a field insulating film to be described later.

Note that the SiO ₂ film 5 is formed for the following reason. That is, if the Si ₃ N ₄ film 6 is directly formed on the surface of the silicon substrate 1, crystal defects will occur on the surface of the silicon substrate 1 due to thermal strain caused by the difference in thermal expansion coefficient between the two. do. To prevent this, the SiO ₂ film 5 is formed.

Next, in order to complete a mask for forming a field insulating film to be described later, a photoresist film 7 is selectively formed on the Si ₃ N ₄ film. That is,
The photoresist film 7 is formed in a region other than the region where the field insulating film is to be formed. and,
Using this photoresist film 7 as a mask, Si ₃ N ₄ is etched by plasma etching, which allows for highly accurate etching.
Film 6 is etched to form a mask for forming a field insulating film.

With the photoresist film 7 remaining, P-type impurities are introduced into the silicon substrate 1 to form a channel stopper. As a method of introduction, for example, ion implantation is used. In that case, the P-type impurity is present in the region where the photoresist film 7 remains.
In the area where the surface of the SiO ₂ film 5 is exposed, it does not reach the SiO ₂ film 5 and the silicon substrate 1.
It reaches the inside of the silicon substrate 1 through the SiO ₂ film 5.

Boron fluoride BF ₂ is preferable as the P-type impurity. The implantation energy is preferably 30 KeV and the dose is preferably 5×10 ¹³ atoms/cm ² .

The boron ions implanted into the P-type well are P ⁺
Forms a mold area and serves as a channel stopper. On the other hand, the poron ions implanted into the N-type silicon substrate 1 are compensated by phosphorus, that is, N-type impurity, introduced by the phosphorus implantation shown in FIG.
Therefore, this region is an N-type region, and an N-type channel stopper exists.

(Field insulating film forming process) After removing the photoresist film 7, as shown in FIG. 3, the surface of the silicon substrate 1 is selectively thermally oxidized in an oxidizing atmosphere at about 1000° C. to a thickness of about 9500 Å. A field insulating film 8 is formed. At this time, since the Si ₃ N ₄ film 6, which is an oxidation-resistant film, does not pass oxygen,
The silicon under this Si ₃ N ₄ film is not oxidized.

During this heat treatment, the aforementioned channel stopper is stretched and diffused directly under the field insulating film, thereby forming a channel stopper having a desired depth. (Not shown) (Surface oxide film removal step) After removing the Si ₃ N ₄ film 6 using, for example, hot phosphoric acid (H ₃ PO ₄ ), in order to obtain a clean gate oxide film, as shown in FIG. As shown in FIG.
The SiO ₂ film 5 on the surface is removed. For example, use hydrofluoric acid (HF) to thinly etch the entire surface to form a SiO ₂ film 5.
, the surface of the silicon substrate 1 is exposed in a portion where the field insulating film 8 is not formed. FIG. 17 shows a plan view of M-CEL in this state. In other words, the X _1F - X _1F switching sectional view in Figure 17 is the fourth
Shown in area X ₁ of the figure.

(Step of forming impurity implant layer) A fifth layer is formed on the surface of the silicon substrate shown in FIG.
An impurity implant layer 9 is formed as shown in the figure. In the embodiment shown in FIG. 5, a P-type impurity was used as the impurity. Ion implantation is preferred as the introduction method. In addition, boron (B), for example, is preferable as the P-type impurity, and the implantation energy in this case is
125 KeV, and the dose is preferably about 10 ¹³ to 2×10 ¹³ atoms/cm ² .

This P-type impurity implant layer may also be formed on the field insulating film.

In this way, the present invention forms the P-type impurity implant layer after forming the field insulating film. By forming this implant layer, it is possible to prevent the occurrence of soft errors due to alpha rays. Prevention of α-ray soft errors by this implant layer will be described later.

(Gate insulating film formation process and threshold voltage control process) Under an oxidizing atmosphere at about 1000°C, the surface of the silicon substrate shown in FIG. A gate insulating film 10 with a thickness of 400 Å is formed. This gate insulating film 10 serves as a gate insulating film for all MISFETs formed on the silicon substrate 1.

Next, in this state, P-type impurity ions are implanted. This is the threshold voltage of all MISFETs.
This is done to define V _th . As the P-type impurity, boron (B) is preferable. The driving energy is
30KeV, and the dose is preferably 5.5×10 ¹¹ atoms/cm ² .
This dose amount changes depending on the value of V _th .

This ion implantation does not use a mask at all,
It is done completely. Therefore, all N channels
The MISFETs will have the same threshold voltage V _th , while all P-channel MISFETs will have the same threshold voltage V _th .

(Direct contact hole formation step) In order to form a contact hole for direct connection between the first polycrystalline silicon layer and the silicon substrate 1, a so-called direct contact hole, a heotresist film 11 is selected on the SiO ₂ film 10. to form. Then, using this photoresist film 11 as a mask, as shown in FIG. 7, the SiO ₂ film 10 which will become the gate insulating film is etched to expose the surface of the silicon substrate 1 and form a direct contact hole CH ₁₀₀ . This CH ₁₀₀ is the 20th
This is the connection between MISFETs Q ₂ and Q ₄ and high-resistance polycrystalline silicon R ₂ shown in the figure.

(First conductor layer forming step) After removing the photoresist film 11, a first conductor layer 12 is formed on the entire surface as shown in FIG. A polycrystalline silicon layer doped with impurities is used as the first conductor layer.

First, a first polycrystalline silicon layer 12 having a thickness of about 3500 Å is formed over the entire surface by CVD. Next, in order to reduce the specific resistance of the first polycrystalline silicon layer 12, an N-type impurity such as phosphorus is introduced into the entire surface by a diffusion method.

At this time, phosphorus is also diffused into the silicon substrate 1 from the first polycrystalline silicon layer 12 through the direct contact hole CH ₁₀₀ , and the N ⁺ type region 13
is formed.

These N ⁺ type regions are diffused to a desired depth in a subsequent heat treatment step. Region 13 is shown in FIG.
Make the connection between MISFET Q ₂ and Q ₄ .

(First conductor layer selective removal step) The first polycrystalline silicon layer 12, which has been subjected to the phosphorus treatment as described above, is etched into a desired shape by plasma etching, which allows for highly accurate etching, as shown in FIG. gate electrodes 14, 16, word line 15
(W), a gate electrode 17 is formed in direct contact with the region 13.

Subsequently, the SiO ₂ film 10 is etched into the same shape to form gate insulating films 18-20. At this time, as shown in FIG. 9, the surface of the silicon substrate 1 is selectively exposed.

(Source/drain region and base electrode extraction layer formation step) For forming P ⁺ type source/drain regions,
Form a mask. For example, this mask can be
A SiO ₂ film 21 selectively formed to a thickness of about 1500 Å by the CVD method is used. That is, the region where the N-channel MISFET including the memory cell is formed is covered with the SiO ₂ film 21.

Then, in this state, a P-type impurity is introduced by, for example, a diffusion method. As this P-type impurity, boron (B) is preferable. As shown in Figure 10, boron is diffused into a P-channel MISFET.
Source/drain regions 22 and 23 are formed. Note that a thin oxide film (not shown) is formed on the surface of the silicon substrate 1 as a result of the heat treatment during this diffusion.

(Step of forming source/drain regions and emitter regions) After removing the SiO ₂ film 21 and the thin oxide film, in order to form N ⁺ type source/drain regions,
A new mask 24 is formed. As this mask, a SiO ₂ film 24 selectively formed to a thickness of about 1500 Å by, for example, the CVD method is used. In other words, the region where the P-channel MISFET is formed is
It is covered with a SiO ₂ film 24.

Then, in the state shown in FIG. 11, the N-type impurity is
For example, it is introduced by a diffusion method. As this N-type impurity, phosphorus (P) is preferable. Phosphorus is diffused into the silicon substrate 1 to form source/drain regions 25 to 28 of the N-channel MISFET.
Note that a thin oxide film (not shown) is formed on the surface of the silicon substrate 1 as a result of the heat treatment during this diffusion. A plan view of the memory cell M-CEL in this state is shown in FIG. That is, X _1L − in FIG.
A cross-sectional view of X _1L is shown in region X ₁ of FIG.

(Contact Hole Formation Step) After removing the SiO ₂ film 24 and the thin oxide film, as shown in FIG. 12, an oxide film 29 is formed on the entire exposed surface of the silicon substrate 1 by thermal oxidation. At this time, since the oxidation rate is different between the silicon substrate 1 and the polycrystalline silicon layers 14 to 17, a layer of about 100 Å thick is formed on the silicon substrate 1.
An SiO ₂ film having a thickness of about 300 Å is formed on the polycrystalline _silicon layers 14 to 17.

Next, a new SiO ₂ film 30 with a thickness of about 1500 Å is formed on the entire surface by the CVD method. This SiO ₂ film 30 is provided for insulation between the silicon substrate and a second conductor layer to be described later.

Next, a photoresist film (not shown) is selectively formed on the SiO ₂ film 30, and this is used as a mask.
Contact holes are formed by successively etching SiO ₂ film 30 and SiO ₂ film 29. This contact hole is opened for connection between a second conductor layer, which will be described later, and the first polycrystalline silicon layer 17 or a semiconductor region formed in the silicon substrate 1, respectively.

Note that the thickness of the SiO ₂ film 29 is approximately 300 Å on the polycrystalline silicon layers 14 to 17, as described above.
On the silicon substrate 1, the difference is about 100 Å. Therefore, it is necessary to perform etching until the SiO ₂ film on the polycrystalline silicon layers 14 to 17 is completely etched. At this time, HF + NH ₄ F was used as the etching solution.
It is preferable to use That is, since this etching solution does not work on silicon, the silicon substrate 1 is not etched.

(Second conductor layer forming step) As shown in FIG.
form. A polycrystalline silicon layer doped with impurities is used as the second conductor layer.

First, a second polycrystalline silicon layer 31 is applied to the entire surface.
It is formed to a thickness of approximately 2000 Å using the CVT method. This second polycrystalline silicon layer 31, as described later,
It is used to connect the third conductor layer and the semiconductor region in the silicon substrate 1 or the first polycrystalline silicon layer 17 to each other. In addition, the power supply voltage supply line Vcc-L and the load resistance R ₁ shown in FIG.
Also used as _R2 .

(Resistor formation process) Next, as shown in FIG. 13, SiO ₂ films 32 to 34 with a thickness of about 1500 Å are selectively formed by CVD to partially cover the second polycrystalline silicon layer 31. cover.

In this state, in order to reduce the resistivity of the second polycrystalline silicon layer 31, for example, phosphorus is introduced by a diffusion method. At this time, the SiO ₂ films 32 to 3
Phosphorus is not introduced into the portion of the second polycrystalline silicon layer covered by 4. Therefore, polycrystalline silicon with a high specific resistance remains partially. Note that the phosphorus diffused into the second polycrystalline silicon layer 31 also diffuses to some extent in the planar direction, and the SiO ₂ films 32 to 34 serving as masks are designed with this in mind.

(Second conductor layer selective removal step) After removing the SiO ₂ films 32 to 34, the second polycrystalline silicon layer 31 is etched into a desired shape to form electrodes 38 to 41 as shown in FIG. Form.

Electrodes 40 and 41 are used for connection to the source and drain regions of the P-channel MISFET. The electrode 39 is a MISFET Q ₄ shown in FIG.
Used as an electrode. Electrode 38 (Vcc-L)
is connected to the first polycrystalline silicon layer 17 which is in direct contact with the source/drain regions of MISFETs Q ₁ and Q ₄ via the high resistance polycrystalline silicon layer 35 (R ₂ ). There is.

(Interlayer insulating film forming step) As shown in FIG. 15, an interlayer insulating film 42 is formed on the entire surface. As the interlayer insulating film, a phosphosilicate glass film (hereinafter referred to as PSG film) is preferable. This PSG film 42 is formed to a thickness of about 6500 Å by CVD method. This PSG film 42 is supplied with a third conductor layer and a second polycrystalline silicon layer, which will be described later, and particularly with a power supply voltage Vcc. This is necessary as an interlayer insulating film between the electrode 38 and the electrode 38.

Next, a photoresist film (not shown) is selectively formed, and using this as a mask, the PSG film 42 is etched to form a contact hole.

(Third conductor layer forming step) As shown in FIG.
45 is selectively formed. As the third conductor layer,
For example, aluminum (Al), which is P-type with respect to silicon, is preferable. The aluminum layers 43-45 are formed to a thickness of about 8000 Å by vacuum evaporation.

At this time, aluminum is diffused into the electrodes 40 and 41 made of the high-resistance second polycrystalline silicon layer, resulting in a P-type conductor layer with a low specific resistance. Electrode 43 is used as data line D shown in FIG. A plan view of M-CEL in this state is shown in FIG. That is, in Figure 19
A cross-sectional view of X _1Q -X _1Q is shown in region X ₁ of FIG.

FIG. 20 shows a schematic layout of the memory cell section formed by the above process, and FIG. 22 shows an equivalent circuit diagram of the memory cell section.

In the layout pattern diagram of the memory cell M-CELL in FIG.
This is the area occupied by

First, as shown in the figure, semiconductor regions SR ₁ to _{SR 6} are arranged inside the IC chip, which serve as wiring and sources and drains of MISFETs.

As shown by the thick solid line, word lines W and gate electrodes are formed on this IC chip by a first conductor layer (polycrystalline silicon layer) through an insulating film.
G ₁ and G ₂ are formed. The word line W is used for transmission along with semiconductor regions SR _{1 and} SR ₂ .
MISFET Q ₃ and semiconductor regions SR ₄ and SR ₅ constitute MISFET Q ₄ for transmission. Furthermore, the gate electrode G ₁ is connected to the semiconductor region SR ₂ ,
Drive MISFET Q ₁ along with SR ₃ is connected to the gate electrode.
G ₂ is used for driving along with semiconductor regions SR ₅ and SR ₃
Each constitutes MISFET Q ₂ . Note that the gate electrode G ₁ is connected to MISFETQ ₂ at the connection point N ₂ .
Semiconductor area electrically connected to MISFIT Q ₄
Direct contact with SR ₅ .

On the word line W and gate electrodes G ₁ and G ₂ ,
As shown by the thick dotted line, the second conductive layer (polycrystalline silicon layer) connects the power supply voltage V _cc -L, the load resistances R ₁ , R ₂ and the connection point N ₁ , through the insulating film.
The wiring between _N6 is integrally formed. That is, one ends of the load resistors R ₁ and R ₂ are integrally connected to the branched power supply voltage supply line V _cc -L. The other end of the load resistor R ₁ is connected to the gate electrode G ₂ at the connection point N ₆ , and crosses the gate electrode G ₁ as a wiring, and connects the MISFET to the connection point N ₁ .
It is connected to a semiconductor region SR ₂ that electrically connects Q ₁ and MISFET Q ₃ . The cross-coupling shown in Figure 22 is achieved by crossing the wiring between connection points N ₁ and N ₆ (second conductor layer) and gate electrode G ₁ (first conductor layer). can. On the other hand, the other end of the load resistor _R2 is connected to the gate electrode _G2 at a connection point _N2 . The load resistances R ₁ and R ₂ are formed in a portion of the polycrystalline silicon layer by controlling the introduction of impurities into the first conductor layer, that is, the polycrystalline silicon layer, as will be explained later.

As shown in the figure, a third conductor layer (aluminum layer) is placed on the wiring between the power supply voltage supply line V _cc -L, the load resistances R ₁ and R ₂ , and the connection points N ₁ and N ₆ through an insulating film. ), the ground potential supply line Vss-L and the data line D are formed parallel to each other and perpendicular to the word line W and the power supply voltage supply line _Vcc -L. The ground potential supply line Vss-L is connected to the semiconductor region SR ₃ electrically connecting MISFET Q ₁ and MISFET Q ₂ at the connection point N ₅ ,
Furthermore, it is connected to a semiconductor region (well region) SR ₆ at a connection point N ₇ . The data line D connects to the semiconductor regions SR 1 and SR ₁ at the connection points N ₃ and N ₄ , respectively.
Connected to SR ₄ .

The circuit diagram of the above memory cell M-CELL is shown in the 22nd page.
As shown in the figure. This memory cell is a flip-flop that cross-couples the input and output of a pair of inverter circuits consisting of series-connected load resistors R ₁ and R ₂ and driving MISFETs (insulated gate field effect transistors) Q ₁ and Q ₂ . It consists of a pair of transmission gate MISFETs Q ₃ and Q ₄ . Flip-flops are used as a means of storing information.
The transmission gate is used as an addressing means for controlling the transmission of information between the flip-flop and the complementary data line pair D.
Its operation is controlled by an address signal applied to word W connected to row decoder R-DCR.

FIG. 21 shows the memory cell M- shown in FIG.
This figure shows a layout pattern of one memory array M-ARY arranged in plural numbers in a CEL or IC chip.

One M-ARY, indicated by the dashed double-dashed line, is defined by the above-mentioned well region, and within that M-ARY there is a 1-bit M-CEL (A-B- CD) are arranged horizontally, ie, in the word line direction, 32 pieces, and vertically, ie, in the data line direction, 128 pieces.

And those M-CELs are arranged as follows.

First, the 1-bit M-CEL shown in Figure 20
Based on the layout pattern of M-CEL1 to M-CEL4 as shown in FIG.
The blocks that form the basis of the ARY configuration are configured. In this basic block, M-CEL2, which is horizontally adjacent to M-CEL1, is connected to its M-CEL1.
arranged line-symmetrically with CEL1, while M-CEL1
M-CEL3 that is vertically adjacent to
-Arranged in a state rotated 180 degrees with respect to CEL1. The M-CEL4 adjacent to the M-CEL3 in the lateral direction is arranged in line symmetry with the M-CEL3.

These basic blocks are successively arranged vertically and horizontally to form one M-ARY. That is, as shown in Fig. 21, there are 16 basic blocks in the horizontal direction, and the concave and convex parts of the basic blocks adjacent to each other in the vertical direction are sandwiched between them.
64 pieces are arranged.

Ground potential supply lines V _ss -L shown in FIG. 20 are arranged on both sides of the M-ARY. Also, M
On both sides outside -ARY, a power supply voltage supply line V _cc -LINE made of a third conductor layer is arranged parallel to the ground potential supply line Vss-L. This power supply voltage supply line _Vcc -LINE is connected to the power supply voltage supply line Vcc-L shown in FIG. ₂₀ at a connection point N0.

S-RAM according to the embodiment of the present invention described above
In the memory cell shown in _FIG .
_A ^peak _{region 9P} ( _P The ion implant layer 9 is formed to have a ⁺ type region). Therefore, P
Peak region 9P with higher impurity concentration than type well 3
According to N ⁺ type area 26 as a storage node,
13, 27 and the P-type well 3 are formed with the substrate 1.
A potential barrier can be formed between the high impurity concentration region 9P and the PN junction. This potential barrier prevents electrons generated by alpha rays from diffusing into the storage node.

Moreover, at this time, the high impurity concentration region is surrounded by the thick field insulating film 8 of the memory cell.
It is formed so as to cover the entire bottom of the MISFET formation region ( _X1 region), or as described later, it is an N ⁺ type region that acts at least as a storage node (the region constituting the storage capacitor C _S in FIG. 22).
By forming the memory cell so that it covers the bottom of the
The rate at which the source and drain portions (storage nodes) of the MISFET portion reach can be significantly reduced. Of course, in the present invention, since the memory cell is formed within the P-type well, the potential barrier formed by the PN junction formed between the P-type well 3 and the substrate 1 also prevents electrons from entering the well due to α rays. This reduces the influx.

Furthermore, according to the present invention, the N ⁺ type storage node, that is, the source and drain regions 2 forming part of the storage capacitor C _S shown in FIG.
Since the P-type well region adjacent to 6, 13, and 27 is made to have a high impurity concentration by the ion implant layer 9, the capacitance value of the storage node capacitor formed by the N ⁺ type source and drain regions can be increased. Can be done. Due to this increase in capacitance,
It is possible to further reduce the adverse effects caused by noise charges caused by α rays.

In the above embodiment, the impurity implant layer 9 is formed after the field insulating film is formed. may be formed. The former is preferable because it allows for a deeper implant. Also,
Although the above embodiment shows an example in which a P-type impurity implant layer is formed, an N-type impurity implant layer may also be formed, and in this case, the same effect as the above-mentioned P-type impurity implant layer can be obtained. be able to.

In the manufacturing method according to the present invention, the impurity implant layer 9 that acts as an α-ray prevention region is formed using the pre-formed thick field insulating film 8 surrounding the memory cell formation region as a mask. No special mask formation is required. This simplifies the process.

Furthermore, in the manufacturing method according to the present invention, the ion implant layer 9 for preventing alpha rays is formed after the thick field oxide film 8 for isolating the element forming regions is formed in advance, so that the formation of the thick field oxide film is prevented. The ion implant layer 9 can be formed without requiring a long heat treatment step, which is sometimes required.
Therefore, deformation (re-diffusion) of the profile of the ion implant layer due to the oxidation heat treatment process can be prevented, and at the same time, a sufficient soft error prevention effect can be obtained.
Adverse effects on MISFET element characteristics can be prevented.

In the above-mentioned embodiment, an impurity implant layer was formed on the entire surface of the element formation region _X1 of the memory cell, but in that case, from the viewpoint of switching speed, etc., a photoresist mask was used to remove unrelated nodes such as peripheral circuits and data lines. It is preferable to take care not to implant impurities indiscriminately. This is the second
This will be explained based on Figure 3. Figure 23 shows the S-RAM of the present invention that prevents soft errors caused by alpha rays.
This is a simplified cross-sectional view of a modification of the device. As shown in FIG. 23, ion implant regions 9 can be selectively formed to cover the bottoms of N ⁺ type regions 26, 13, and 27 that act as storage nodes. This makes it possible to avoid implanting impurities into nodes unrelated to storage nodes, such as data lines. That is, in the M-CEL circuit diagram shown in FIG.
For MISFE Q ₂ and transmission gate
It is preferable to implant ions only into the storage node N ₂ connecting to MISFET Q ₄ to avoid implanting ions into unrelated nodes. However, for ease of mask alignment and stability of V _t control, ions may be implanted into some of the adjacent nodes.

[Brief explanation of the drawing]

The drawings show embodiments of the invention, and include FIGS. 1 to 16.
17 is a plan view of the memory cell shown in FIG. 4, FIG. 18 is a plan view of the memory cell shown in FIG. 11, 19 is a plan view of the memory cell shown in FIG. 16, FIG. 20 is a schematic layout pattern diagram of the memory cell, FIG. 21 is a layout pattern diagram of the memory array corresponding to FIG. 20,
FIG. 22 is an equivalent circuit diagram of a memory cell, and FIG. 23 is a sectional view showing another embodiment of the present invention. 8...Field insulating film, 25-28...N ⁺
Region, 9... impurity implant layer.

Claims (1)

[Claims] 1. A semiconductor substrate having a plurality of memory cells formed in a well region defined by a PN junction, each of which is connected in series to a pair of high-resistance polycrystalline silicon bodies. In a semiconductor memory device that is a static memory cell comprising a pair of driving insulated gate field effect transistors whose gates and drains are cross-coupled to each other, A semiconductor characterized in that an implant layer of an impurity having the same conductivity type as the well region is formed in a well region below the semiconductor region of a driving insulated gate field effect transistor so as to cover the bottom surface of the semiconductor region. Storage device. 2 having a plurality of memory cells formed in a first conductivity type well region defined by a PN junction of a semiconductor substrate, each of the memory cells being connected in series to a pair of high resistance polycrystalline silicon bodies, In a method of manufacturing a semiconductor memory device which is a static memory cell comprising a pair of driving insulated gate field effect transistors whose gates and drains are cross-coupled to each other,
After forming a well region demarcated by a PN junction and forming a field insulating film within the well, the well region in which the semiconductor region of the storage node is to be formed is formed using at least a portion of the field insulating film as a mask. An implant layer having a higher impurity concentration than that of the well region is formed by ion-implanting impurities of a first conductivity type into the well region, and thereafter, the implant layer of the driving insulated gate field effect transistor is A method of manufacturing a semiconductor memory device, comprising forming a semiconductor region of a storage node above the implant layer in the well.