JPH0666444B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a static random access semiconductor memory, which has a problem of radiation resistance as the memory cell density becomes higher. The present invention relates to a method of manufacturing a semiconductor device having an improved memory cell structure for preventing a decrease in strength.

[Conventional technology]

Conventionally, for example, an equivalent circuit of a static random access memory cell portion having an NMOS structure is as shown in FIG. 4, and its layout pattern is as shown in FIG. The sectional structure of a part of the portion indicated by EE 'in FIG. 5 was as shown in FIG. In addition,
It was as shown in FIG. 5 and FIG. The fifth
In Fig. 6 and Fig. 6, V _CC line and load resistance R
_The polycrystalline silicon pattern portion of the second layer forming ₁ and R ₂ , that is, the region surrounded by the broken line in FIG. 4 is not shown.

In FIGS. 5 and 6, a pair of N-channel insulated gate field effect transistors (hereinafter referred to as FETs) Q ₁ and Q ₂ forming a flip-flop are provided on the main surface side of the P ⁻ type silicon substrate 1. Source regions 2 and 4 and drain region 3
And N ⁺ type diffusion region (5 in FIG. 5, N ⁺ (S), N ⁺
Noted as (D). ) Are formed respectively.
The drain region 3 of the FETQ ₁ is connected to one end side of a polycrystalline silicon wiring layer 7 serving as a polycrystalline silicon gate electrode of the FETQ ₂ via a direct contact 6 shown by a dashed diagonal line, and at the same time, this polycrystalline silicon wiring is connected. The load resistor shown by R ₁ in FIG. 4 made of the second-layer polycrystalline silicon layer is connected through an interlayer contact 10 shown by a diagonal line of a thick line descending to the right and provided on one end of the layer 7, This makes FE
TQ ₁ and resistor R ₁ form a first inverter.
Further, one end side of the polycrystalline silicon gate electrode 9 of the FET Q ₁ is connected to the drain region 5 of the FET Q ₂ through a direct contact 12 shown by a dashed diagonal line, and at the same time, the other end of the polycrystalline silicon gate electrode 9 is connected. through an interlayer contact 11 shown by a thick diagonal line downhill provided, the load resistance shown by R ₂ is connected to a fourth diagram of a second layer polycrystal silicon layer, whereby the FETs Q _{2 Second} with resistance R 2
Inverter is configured. The resistors R ₁ and R ₂ are connected to the power supply V _CC by the second-layer polycrystalline silicon wiring (however, not shown in FIGS. 5 and 6).

Further, a pair of transfer gate FETs Q ₃ and Q _{4 using} the first-layer polycrystalline silicon wiring 13 as each polycrystalline silicon gate electrode 13 ′ are provided. FETQ ₃ is FE
It has a drain region 3 common to TQ ₁ and an N ⁺ type diffusion region 16 connected to the data line D by an aluminum wiring 21 extending in the vertical direction of FIG. For FETQ ₄ as well, the drain region 5 of FETQ ₂ is
Data is provided by the polycrystalline silicon gate electrode 9 connected through the direct contact 12 and the drain region 18 connected through the direct contact 8 and the aluminum wiring 20 extending in the vertical direction of FIG. Each having an N ⁺ type diffusion region 17 connected to the line. Further, the source regions 2 and 4 of the FETs Q ₁ and Q ₂ have a fifth region via the contact 19 with the N ⁺ type diffusion layer region 23 as a common wiring layer.
It is connected to the ground potential by an aluminum wiring 22 extending in the vertical direction of the figure.

Further, in FIG. 6, 24 is a field oxide film, 25 is a gate oxide film, 26 is an N ⁺ type diffusion region formed inside the substrate of the direct contact portion through the first-layer polycrystalline silicon layer, Numeral 27 is a polycrystalline silicon layer of the first layer and a second layer
A silicon oxide film formed by a vapor phase epitaxy method for insulation from a second polycrystalline silicon layer (not shown), and 28 is a second polycrystalline silicon wiring layer (not shown) and an aluminum wiring layer. This is a phosphorous glass layer formed by a vapor phase growth method for insulation.

[Problems to be solved by the invention]

In the structure of the conventional semiconductor memory described above, the capacitance values of the nodes A and B of the memory cell in FIG. 4 are connected to the drain region and this drain region which are determined by the planar layout pattern dimensions of FETQ ₁ and FETQ ₂ , respectively. It consists of the diffusion layer capacitance of the N ⁺ type diffusion layer region, the capacitance between the gate electrode and the silicon substrate, and various interlayer capacitances. However, in the layout pattern structure as shown in Fig. 5, when the gate oxide film thickness is about 400Å The ratio of the diffusion layer capacity to the node capacity is about 60%, which is dominant.

By the way, with the recent increase in capacity and density of semiconductor memories, the size of memory cells is becoming smaller and smaller, and the node capacitance is also becoming smaller due to the size reduction. However, if the node capacitance becomes too small, there is a problem that the data stored in the memory cell is inverted due to electron hole bears generated in the substrate due to the incidence of radiation such as α-rays. It was an obstacle to the change.

That is, a pair of FETQs that form a flip-flop circuit.
_When an α-ray in the vicinity of the drain region of the FET that was turned off among ₁ and Q ₂ was incident, the electron-hole pair generated in the P ⁻ type silicon substrate reached the drain depletion layer edge by diffusion. Electrons are trapped in the N ⁺ type drain region, neutralize the positively charged drain to lower the drain potential, and at the same time, the potential of the gate of the FET on the side connected to that drain. To lower the FET to turn it off, and as a result, the data is inverted.

In order to prevent this, the capacitance value of the nodes A and B connected to the drain part of the memory cell part is increased so that the electrons generated by the incidence of α rays are trapped in the drain on the high potential side. Even if the drain charge is neutralized and the potential drops to some extent, the nodal capacitance value must be set so as not to cause data inversion.
However, since the node capacity is greatly influenced by the cell size, it is impossible to simply reduce the size.

Therefore, an object of the present invention is to solve the above problems and to provide a method of manufacturing a semiconductor device having a semiconductor memory which is excellent in radiation resistance even if the memory cell area is reduced.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a groove in a semiconductor substrate of one conductivity type, a step of forming a polycrystalline silicon wiring of the opposite conductivity type so as to at least fill the groove, and a step of forming a transistor of a memory cell. A step of forming a drain region so as to be located in the vicinity of the groove; and a heat treatment of at least the polycrystalline silicon wiring to form an impurity diffusion region of the opposite conductivity type around the groove and connect it to the drain region. And a process.

[Action]

Next, the operation of the present invention will be described with reference to FIG. 1 showing an embodiment thereof.

The planar layout pattern structure of the semiconductor memory of the present invention is equivalent to the conventional one, and the present invention is different from the prior art in that a pair of FETs for forming the flip-flop circuit shown in FIG. This is the structure of the drain connection part, that is, the output node part of the flip-flop circuit.
As shown in FIG. 1, this structure has a groove inside the semiconductor substrate of the direct contact portion for cross-connecting the gate and the drain with each other, and the groove is of the same conductivity type as the drain region and the same substrate. It comprises providing an impurity diffusion region.

This increases the junction area of the diffusion layer connected to the drain region and increases the capacitance of the diffusion layer.Therefore, even if the cell size is reduced, it is saved in the memory by the electrohorn pair generated by the incidence of radiation such as α rays. The node capacity of the cell can be secured so that the existing data is not inverted.

Therefore, the use of the memory cell structure according to the present invention is more effective than ever before in reducing the cell area, and makes it possible to easily realize a large-capacity memory.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing an essential part of a semiconductor device manufactured according to an embodiment of the present invention, and corresponds to the conventional example shown in FIG. 6 (a sectional view taken along the line EE 'in FIG. 5). .

In FIG. 1, 101 is a P ⁻ type silicon substrate, 102 is a field oxide film formed on this substrate by a selective oxidation method,
103 is a gate oxide film, 110 is a first layer of polycrystalline silicon gate electrode formed by phosphorus-doped vapor phase epitaxy, 11
Reference numeral 1 is a polycrystalline silicon wiring layer formed at the same time as this polycrystalline silicon gate electrode, and 106 is the first layer formed in a direct contact portion provided in the drain region and buried in a groove portion 106 deeper than the drain region. eyes polysilicon wiring layer of phosphorus-doped, 112 N ⁺ -type impurity diffusion region serving as a drain region, N ⁺ -type impurity diffusion region serving as the drain region and a source region formed at the same time 113,
Reference numeral 114 denotes an N ⁺ -type impurity diffusion region formed by diffusion from the first-layer phosphorus-doped polycrystalline silicon wiring layer 106 ′ buried in the groove 106, and 115 denotes the first-layer polycrystalline silicon wiring. Oxide film by vapor phase epitaxy for insulation between the first layer and the second-layer polycrystalline silicon wiring layer (not shown), and 116 is the second-layer polycrystalline silicon wiring layer (not shown) A phosphorous glass layer by vapor deposition for insulation from the aluminum wiring layer, and 117 an aluminum wiring layer.

What is important in the structure of this embodiment is that a pair of output nodes of the flip-flop circuit used in the present invention are formed.
It is said that the drain region of the FET has an N ⁺ -type impurity diffusion region of the same conductivity type as this drain region and deeper than the depth of this drain region. Therefore, even when the cell size is reduced, it is possible to prevent the reduction of the node capacitance of the flip-flop circuit that constitutes the memory cell, so it is saved in the memory by the electron hole pair generated by the incidence of radiation such as α rays. It is possible to prevent the inversion of the current data.

Next, the manufacturing method of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, a P ⁻ type semiconductor substrate 101 is formed.
After forming a thick field oxide film 102 on the one main surface side by a known selective oxidation method, a gate oxide film 103 made of a thin oxide film is formed by a thermal oxidation method, and then a photoresist 104 is formed.
Is applied to the entire surface to pattern the direct contact portion 105. The pattern size of the direct contact portion is preferably about twice the film thickness of the first-layer polycrystalline silicon layer formed below.

Next, as shown in FIG. 2B, the gate oxide film of the direct contact portion 105 is removed by etching using the photoresist 104 as a mask by a well-known photoetching method, and then the direct contact portion is masked with the photoresist 104. A well-known reactive ion etching technique is used for the semiconductor substrate 105 to form a groove portion having a depth sufficiently deeper than the diffusion layer depth of the source / drain regions, for example, about 3 μm.
After forming 106, a phosphorus-doped polycrystalline silicon layer 107 of the first layer is deposited on the entire surface, and then a photoresist is applied on the entire surface to pattern the silicon gate electrode portion and the silicon wiring layer portion. Photoresist 108 and 109 are provided respectively.

Next, as shown in FIG. 2C, the photoresists 108 and 109 are used as masks by a well-known photoetching method.
The polycrystalline silicon gate electrode 110 and the polycrystalline silicon wiring layer 10 are formed by the well-known reactive ion etching technique.
6 ′, 111 is formed, and then polycrystalline silicon gate electrode 110 is formed.
Arsenic is ion-implanted using the field oxide film 102 as a mask, and then high-temperature heat treatment is performed to form N ⁺ -type impurity diffusion regions 112 and 113 to serve as drain and source regions, and at the same time, N ⁺ -type impurity diffusion regions are also provided around the trench 106. Form 114. Here, N ⁺ type impurity diffusion region 112 serving as the drain region and polycrystalline silicon wiring layer 111 are connected by N ⁺ type impurity diffusion region 114 formed around groove 106.

After that, a silicon oxide film 115 is deposited on the entire surface by vapor phase epitaxy, and then a second-layer polycrystalline silicon wiring layer (not shown) is patterned. The structure shown in FIG. 1 is obtained by depositing it on the entire surface by a phase growth method, forming a contact opening by a well-known photoetching technique, and forming an aluminum wiring layer 117.

The above embodiment can be further modified based on the technical idea of the present invention. For example, the memory cell layout pattern shown in FIG. 5 can be variously changed according to the design criteria of the process, and the conductivity type of the semiconductor region and the type of impurities used may be changed. Of course, it can be applied to CMOS static cells.

Further, in consideration of the purpose of increasing the capacity of the drain region in the present invention, after forming a deep groove portion in the direct contact portion as shown in FIG. 3, a photoresist used as an etching mask for forming the groove is formed. It is possible to increase the capacitance of the bottom surface of the groove by directly using the impurity of the same conductivity type as that of the semiconductor substrate and introducing the impurity into the groove bottom by ion implantation to increase the impurity concentration.

〔The invention's effect〕

As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, in a semiconductor memory having a flip-flop type cell as a unit cell, an impurity diffusion region having a conductivity type opposite to that of a substrate serving as an output node of a flip-flop circuit is reduced. Since a part of them is formed in the groove provided in the semiconductor substrate, the diffusion capacity at the output node of the flip-flop circuit is increased, which is likely to occur when the size of the memory cell is reduced. This has the effect of preventing inversion of memory data.

[Brief description of drawings]

FIG. 1 is a sectional view showing an essential part of a semiconductor memory of the present invention, FIGS. 2 (a) to 2 (c) are process sectional views for explaining a manufacturing method of an embodiment of the present invention, and FIG. Process sectional views of another embodiment of the present invention, FIGS. 4, 5, and 6 are respectively a circuit diagram, a plan view, and a fifth diagram showing an example of a conventional semiconductor memory.
It is the EE 'sectional view taken on the line of FIG. 101 …… P ^- type silicon substrate, 102 …… Field oxide film,
103 ... Gate oxide film, 104 ... Photoresist, 105 ...
… Direct contact part, 106 …… Groove part, 106 ′ …… Polycrystalline silicon wiring layer, 107 …… Polycrystalline silicon layer, 108,1
09 …… photoresist, 110 …… polycrystalline silicon gate electrode, 111 …… polycrystalline silicon wiring layer, 112,113,114 ……
N ⁺ type impurity diffusion region, 115 …… Silicon oxide film, 116 ……
Phosphorus glass layer, 117 ... Aluminum wiring layer, 118 ... Ion implantation layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-59-54260 (JP, A) JP-A-51-130178 (JP, A) JP-A-60-261167 (JP, A)

Claims (1)

[Claims] 1. A step of forming a groove on a semiconductor substrate of one conductivity type to be a node of an SRAM, a step of forming a polycrystalline silicon wiring of the opposite conductivity type so as to at least fill the groove, and a memory cell. Forming a drain region of the transistor in the vicinity of the groove, and heat treating at least the polycrystalline silicon wiring to form the impurity diffusion region of the opposite conductivity type around the groove. A method for manufacturing an SRAM, comprising the step of connecting to an SRAM.