CA1228425A - Dynamic ram cell with mos trench capacitor in cmos - Google Patents

Abstract

DYNAMIC RAM CELL WITH MOS TRENCH CAPACITOR IN CMOS

Abstract of the Disclosure This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the sub-strate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.

Description

DICK RAM CELIA WITH MOW TRENCH CAPACITOR It CMOS

DESCRIPTION

Technical Field This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRUM cell wherein at least a portion of the substrate is heavily doped and forms the counter electrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the sub striate. The jell itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.

ok BACKGROUND OF TAO INVENTION

The recent literature has emphasized "one-device"
memory cell arrangements where higher and higher degrees of integration are being sought. This is achieved in most cases by juxtaposing access tray-sisters and storage capacitors to achieve cell area reduction while at the same time increasing the storage capacitance. In the prior art, capacitance is increased by decreasing oxide thickness, increase in the surface capacitor area or forming trench capacitors in semiconductor substrates.

In CA apply no. 481,154, filed May 16~ 19~5, a TRAM cell is shown wherein a trench capacitor extends into a heavily doped substrate which acts as the counter-electrode of -the capacitor. In addition, an FRET
access transistor is disposed adjacent the trench capacitor and has its source/drain directly connected to the electrode of the trench capacitor disposed in the trench. In the embodiment shown, the access transistor is electrically isolated from other similar cells and from the highly doped substrate by insulation. The application doesn't address the fabrication of such DRAM cells in the CMOS environment wherein the access transistor of the cell is formed within a well disposed in a semiconductor region of opposite conductivity type.
To the extent that the structure of the present application incorporates such a well and further, incorporates a trench capacitor which penetrates or .

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etudes through the well to a heavily doped portion of the substrate, the present application distinguishes over the structure of the above mentioned co-pending application.

An article entitled "Novel High Density, Stacked Capacitor ISSUE I by M. Coinage et at, Proceedings of the Thea Conference on Solid State Devices, Tokyo, 1978; Japanese Journal of Applied Physics, Supplement 18-1, pp. 35-42 describes a Dynamic Random Access Memory (DRAM) cell using a capacitor stacked on top of an associated access transistor.
The structure is of interest because the source of the access transistor is directly connected to one electrode of the capacitor. There is, however, no mention of a trench capacitor or any indication that a trench capacitor may be used in conjunction with an access transistor which is disposed in an n or p-well.

An article entitled "A Corrugated Capacitor Cell (COO) for Megabit Dynamic MOW Memories" by H. Tsunami et at, IEEE Electron Device Letters, Vol. EDDY, No.
Al April 1983, pp. 90-91, shows a one-device memory cell which is characterized by an etched-moat storage capacitor which extends into the substrate.
Structurally, the storage capacitor is disposed alongside an access transistor. The moat is ins-fated and filled with polysilicon to form one plate of the capacitor. Because a depletion region is formed in the semiconductor substrate around the moat, when a positive potential is applied to the polysilicon capacitor electrode, a minimum spacing between moats is required to prevent punch-through.
This fact militates against denser packing of devices. Also, in order to form an inversion region in the substrate which acts as a storage electrode, the substrate must be p -conductivity type, suggesting that the authors contemplate neither the use of a substrate as a common counter electrode nor the penetration of a well by a trench into a highly doped region to obtain the bulk of their capacitance. In the structure of the present application, at least a portion of the substrate must be highly doped to provide a counter electrode for all the DRAM cells formed on a chip. No short circuiting of the capacitors occurs because the storage electrode is disposed in the trench and insulated from the counter electrode. In addition, from a structural point of view, there is no direct connection in the reference between a source/drain diffusion and the polycrystalline material disposed within the moat and no access transistor disposed in a well.

An article entitled "A Sub micron CMOS Megabit Level Dynamic RUM Technology Using Doped Face Trench Capacitor Cell" by K. Minegishi et at, Idyll 83, December 1983, pp. 319-322 discusses RAM cells in the CMOS environment and shows a trench the wall of which is heavily doped to form an extended source/drain region for an associated access transistor. A polycrystalline electrode is disposed in insulated spaced relationship with the substrate within the trench which acts as the counter electrode of the capacitor. In this article, the substrate doesn't act as a counter electrode inasmuch as a highly doped substrate would degrade the performance of associated transistors. In any event, the capacitor doesn't penetrate a well region and there is no direct connection between the source of the access device and the electrode in the capacitor trench.

US. Patent 4,3g7,075 filed July 3, 1980 shows a one-device memory cell where enhanced capacitance is obtained by extending the drain diffusion into a well etched in the semiconductor substrate. There is no separate capacitor element and the capacitance enhancement is a direct result of increasing the drain p-n junction area.

US. Patent 4,327,476 filed November 28, 1980 shows a one-device memory cell which incorporates a capacitor electrode disposed in a groove or trench The electrode is formed alongside a source/drain region and in insulated spaced relationship with the substrate. There is no interconnection between the capacitor electrode in the trench and the source/drain region. The reference doesn't show the use of a well or a trench which penetrates into a highly doped substrate portion.

An article in the IBM Technical Disclosure Bulletin entitled "Very Dense One-Device Memory Cell" by C.
G. Jambotkar, Vol. 25, No. I July 1982, p. 593, shows a one-device memory cell whereirl the drain diffusion is formed around the periphery of a trench. The inside of the trench is covered with insulation and the remaining void may be filled with polyamide, polysilicon or Sue. While a trench is formed for the cell shown, no separate capacitor is formed therein. The structure shown does no more than lengthen the drain diffusion to thereby increase the junction capacitance.

From all the foregoing, it should be clear that none of the above cited references provide a memory cell wherein both the access transistor and its associated trench capacitor are formed in a well disposed in an opposite conductivity type substrate.
As a result, prior art structures incorporating a well are limited as to the amount of capacitance which can be obtained because it was not perceived that the trench could penetrate through the well and achieve most of the capacitive effect in the heavily doped counter electrode portion of the substrate.
Thus, none of the references cited show the combine-lion of the access transistor and trench capacitor disposed in a well wherein the trench capacitor extends from the well or penetrates through the well to a highly doped substrate and wherein the source of the access transistor is directly connected to the electrode disposed inside the trench.

It is, therefore, a principal object of the present invention to provide a "one-device" DRAM cell wherein both an access transistor and its associated trench capacitor are formed in a well in a semi con-doctor substrate.

Another object is to provide a DROP cell wherein the depth of the trench capacitor is greater than the depth of a well in which an associated transistor is formed.

Another object is to provide a DRAM cell wherein a trench capacitor extends from a well into a highly doped substrate wherein the greatest portion of the capacitance of the cell is obtained.

Still another object is to provide a DRAM cell wherein the capacitance obtainable is greater than that obtained using prior art approaches.

Yet another object is to provide a DRY cell which is not subject to punch-through between adjacent capacitor trenches and is less subject to alpha particle induced soft errors inherent in memory cells which use relatively high resistivity substrates.

Yet another object is to provide a DRAM cell which is less susceptible to soft errors due to minority carrier injection from peripheral circuits.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a Dynamic Random Access (DRAM cell which utilizes an FRET access transistor and a storage capacitor both of which are formed in a well in a semiconductor substrate. The well is of opposite conductivity type to that of the substrate and includes the source, drain and channel Jo S

regions of the access transistor. Also included is a trench which extends through the well into a heavily doped substrate region which acts as the counter electrode of the storage capacitor. The electrode of the storage capacitor is disposed in insulated, spaced relationship with the substrate and may be made of heavily doped polycrystalline silicon. The electrode is connected by means of a bridge region to the source of the access transistor. A polysilicon gate disposed over the channel region completes the basic structure of the DRAM cell. The well formed in the substrate may be either p or n- conductivity type. Where the jell is of one conductivity type, the substrate is of heavily doped opposite conductivity type and includes a more lightly doped region of like conductivity in which the well is disposed. The lightly doped region provides a transition from the heavily doped portion of the substrate of one conductivity type to the opposite conductivity type of the well to reduce the likelihood of breakdown at the junction between the regions. The heavily doped portion of the substrate, in addition to acting as the counter electrode of the trench capacitor, makes the resulting memory cell less susceptible to soft errors due to alpha particle impingement.

In the cell of the present invention, the well is biased to a fixed potential arid the access transistor polysilicon gate forms part of a word line to which a plurality of DRAM cells of an array are connected. Similarly, the source/drain of the FRET access transistor is connected to a bit line to which a plurality of drains of other DRAM cells in an array are connected. By applying appropriate word and bit line potentials to the access transistor, binary information may be written into and read from the storage capacitor.

The DRAM cell of the present invention may be implemented using either channel and n-channel access transistors. The conductivity type of the source and drain regions governs the conductivity type of the polycrystalline silicon used as the capacitor electrode.

A technique for fabricating the structure of the GRAM cell of the present invention is also disclosed. The process used does not depart greatly from processes used to fabricate Complementary Metal Oxide Semiconductor (CMOS) devices. One significant departure is that, after formation of a well in a lightly doped portion of the substrate, a trench is formed by reactive ion etching which extends from the surface of the jell, through the well and into the heavily doped portion of the substrate. There-after, the trench is lined with insulating material and filled with polycrystalline material. Then, using a second layer of polycrystalline silicon, a bridge region is formed which interconnects the electrode in the trench with the source region of the access transistor. A portion of the source region is formed when a portion of the bridge region out-diffuses Dupont during a subsequent annealing step. The resulting structure has good surface topology and is not subject to minimum spacing requirements of prior art trench capacitors and is less subject to soft error occurrences found in prior art DRAM cells.

These and other objects, features and advantages of the present application will be apparent from the following more particular description of a preferred embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially schematic, cross-sectional view of a Dynamic Random Access Memory (DRAM) cell which shows an access transistor disposed alongside a trench capacitor. The source of the access transistor is directly connected to an electrode within the trench. The latter extends through an n-well and a lightly doped p -region of the substrate into a heavily doped progeny ox the substrate. The substrate acts as a counter electrode of the trench capacitor while the electrode disposed within the trench acts as the other electrode of the trench capacitor. A bias voltage source is shown connected to the n-well and the substrate is connected to ground potential.

FIG. 2 is a partial plan view of the DRAM cell of FIG. 1 showing -the relationship of the access transistor to the trench capacitor. In addition, a second DRAM cell layout is shown to indicate how area savings are obtained by switching the trench capacitor from one side of the cell to the other for each succeeding cell.

if FIG. 3 is a cross-sectional view of the structure of FIG. l at an intermediate stage in its fabrication process showing a trench penetrations through a well and a lightly doped portion of a semiconductor substrate into a heavily doped portion of the substrate. The trench itself is shown filled with polycrystalline silicon.

FIG. 4 is a cross-sectional view of the structure of FIG. 3 at a later stage in its fabrication process.
FIG. 4 shows a bridge region interconnecting the electrode of the trench capacitor and the source region of the access transistor. A masking nitride layer is also shown which masks the substrate surface during an oxidation step which augments the recessed oxide regions.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In what follows, access transistor 2 will be Corey-terraced as having source and drain regions. For purposes of description, the drain region is that region which is connected to the bit line of a memory array. Also, the electrode of the trench capacitor 3 is that electrode on which charge is stored via access transistor 2 while the counter-electrode is that electrode on which charge is induced.

Referring to FIG. 1, there is shown a partially schematic, cross-sectional view of a Dynamic Random Access Memory (DRAM) cell l which includes a field effect access transistor 2 and a trench capacitor 3 both of which are formed in a semiconductor substrate 4 preferably of silicon. Access transistor 2 is formed in an n-well 5 and includes source region 6 and drain region 7 of heavily doped p -conductivity type. N-well 5 is disposed in a lightly doped p -conductivity type portion 8 of substrate 4. A recessed oxide (ROW) region 9 isolate memory cell 1 from other similar memory cells formed on substrate 4. In FIG. 1, trench capacitor 3 is formed from a trench 10 which extends from the surface of substrate 4 through n-well 5 and lightly doped substrate portion 8 into a heavily doped p -conductivity type portion 11 of substrate 4. A plug 12 of heavily doped p -conductivity type polycrystalline silicon is disposed in trench 10 and insulated from substrate 4 by means of a layer 13 of insulation. Layer 13 may be a single layer of silicon dioxide or preferably may be a composite triple layer made up of layers of silicon dioxide, silicon nitride and silicon dioxide. Source region 6 and plug 12 are electrically and physically interconnected by means of a bridge region 14 of heavily doped p -conductivity type polycrystalline silicon. Region 14 may be made of any conductive material provided it is compatible with the process being utilized. A gate electrode 15 of heavily doped n -conductivity polycrystalline silicon is shown disposed over and insulated from the channel region between source region 6 and drain region 7 by a thin gate oxide 16. Gate electrode 15 is connected via interconnection 17 to other gate electrodes of an array of DRAM cells 1 and is otherwise identified in FIG. l as Will.

s In FIG. 1, a heavily doped n -conductivity polyp crystalline silicon element 18 is shown disposed over plug 12 and insulated from it by oxide.
Element 18 forms a connection to the gate electrodes of adjacent DRAM cells 1 and results in a considerable saving in memory cell area because the area over trench capacitor 3 can be utilized without any degradation in device characteristics. Element 18 is connected via interconnection 19 to other gaze electrodes of the array of DRY cells 1 and is otherwise identified in FIG. 1 as WYLIE. Drain region 7 acts as the bit line for a plurality of DRY cells 1 which are all connected to one of the bit lines of an array of DRY cells 1. Drain region 7 is connected to other device drains via interconnection 20 otherwise identified in FIG. 1 as BY. While not specifically shown in FIG. 1, interconnection 20 it normally formed from metallization such as aluminum.

FIG. 1 shows a voltage source 21, otherwise identi-fled therein as V, connected to n-well 5 to provide a bias to it. Substrate 4 is shown connected to ground via interconnection 22. Also, pulsed voltage sources 23,24 are shown in FIG. 1 connected to interconnections 17,21, respectively. These sources, when activated, write binary information into trench capacitor 3. The activation of source 17 reads binary information from trench capacitor 3.
Specific voltages will be discussed below when the operation of DROP cell 1 is discussed in some detail.

1 'I
At this point, it should be noted that trench capacitor 3 penetrates through the p-n junction between n-well 5 and the lightly doped, p -conductivity type portion 8 and, as a result, the capacitance obtainable is not limited like it is in prior art arrangements where the capacitance obtainable is limited by the thickness of the epitaxial layer.

Referring now to FIG. 2, there is shown a plan view of DROP cell 1 shown in FIG. 1. In the layout drawing of FIG. 2, both the relationship of trench capacitor 3 to access transistor 2 and the relation-ship of DRAM cell 1 to an adjacent similar DRY cell 1 are shown. To achieve area conservation, trench capacitor 3 is first disposed adjacent the right-hand side of lower DROP cell 1 in FIX. 2. For the uppermost of the two DRY cells 1 shown in FIG.

2, trench capacitor 3 is disposed adjacent the left-hand side of cell 1 and in line with the interconnection 17. The area over this trench capacitor 3 is covered with oxide. In this way, WYLIE
or interconnection 17 is connected to gate electrode 15 of the lowermost DRAM cell 1 and extends over trench capacitor 3 of the uppermost DRAM cell 1 ion FIG. 2. In a similar way, WYLIE is connected to gate electrode 15 of the uppermost DRAM cell 1 and extends over trench capacitor 3 of the lowermost DRAM cell 1. By repeating the pattern for pairs of DRAM cells 1 as shown in FIG. 1, considerable savings in area can be obtained.

Referring no to FIG. 3, there is shown a cross-sectional view of -the structure of FIG. 1 at an intermediate stage in its fabrication process after Noel 5, ROW regions 9 and trench capacitor 3 have been created. The fabrication of Do cell 1 is begun by depositing an epitaxial layer of p -conductivity type silicon from Solon doped with boron on p -conductivity type portion 11 to form portion 8 of silicon substrate 4 in which access transistor 2 and trench capacitor 3 are to be formed. The doping level in portion 8 is 2X1015 atoms cm 3 while that in portion 11 is lxl019atoms cm After depositing substrate portion 8, a layer of oxide is thermally grown on its surface. A layer of photo resist is deposited on the oxide layer and is patterned using well-known techniques to form an opening through which ions will be implanted to Norm n-well 5. In order to obtain a retrograde doping profile in n-well 5, a deep ion implantation step followed by a shallow ion implantation are carried out. The deep ion implantation step provides a high conductivity region near the bottom of n-well 5 which eliminates noise problems which might arise if n-well 5 remained highly resistive. Either arsenic or phosphorus is ion implanted in a well-known way to a depth which does not penetrate through portion 8 of substrate 4. The latter is then annealed to activate the implanted species. The implanted Dupont has a concentration of 1017 atoms cm 3 near the bottom of the implant while it is 2X1015 atoms cm near the surface of n-well 5. After the surface is thermally oxidized, a nitride layer is deposited everywhere. A layer of photo resist is then deposited and patterned in a well-~.nown way to permit the etching of openings in the nitride and oxide fevers to expose portions of the surface of substrate 4 where ROW regions 9 are to be formed.
Enchants such as H3~04 and buffered HO are used to etch the nitride and oxide, respectively. Using a thermal oxidation step, after stripping the photo-resist, ROW regions 9 are formed which isolate Drowsily 1 electrically from other similar cells formed on substrate 4.

As a prelude to the formation of trench 10 in substrate 4, 2 photo resist layer is deposited arid patterned over the nitride layer. Substrate 4 is then subjected to a Reactive Ion itching (RYE) step whereby the unmasked portion of substrate 4 is removed down to a desired depth. In the process, unmasked portions of nitride, oxide and substrate portions 8, 11 are removed in that order until trench 10 is formed. Then, in a preferred approach, layer 13 is formed on the surface of trench lo using alternating layers of oxide, nitride and oxide. The first oxide layer is a layer of thermally grown oxide which forms only on the surface of trench lo since a nitride layer still masks the surface of substrate 4. Subsequently, a layer of nitride is deposited everywhere by chemical vapor deposition on the surface of the thermally grown oxide, on the nitride layer between ROW regions 9 and on ROW
-regions 9. Then, substrate 4 is subjected to a thermal oxidation step which forms a thermally grown oxide in any pinholes which might be present in the previously deposited nitride layer. The multi layer approach, in addition to eliminating pinholes in the resulting layer, prevents out-diffusion of Dupont from plug 12 which is to be formed from heavily doped p -polycrystalline silicon because the nitride layer is an effective diffusion barrier.

A layer of heavily doped polycrysta11ine silicon is then deposited using the chemical vapor deposition of silicon from Solon doped Whitehall boron to render the resulting layer p -conductivity type. The layer is deposited in a thickness sufficient to fill trench 10. Substrate 4 is then subjected to an RYE
planarization step to remove the polycrystalline layer everywhere down to the top of trench 10. The nitride layer deposited during the formation of trench insulation layer 13 and the nitride layer between the ROW regions 9 act as etch stops during the RYE planarization step using a well-known optical end-point detect technique. At this point, DRAM cell 1 has the structure shown in cross section in FIG. 3.

FIG. 4 shows a cross-sectional view of the device of FIG. l at another intermediate stage in its fabric-lion after a thin, heavily doped p -conductivity type layer has been deposited and patterned to form bridge region 14 over insulation layer 13 between source region 6 of access transistor 2 and plug 12.

The structure of FIG. 4 is obtained by first adding a nitride layer 25 on top of the oxide and nitride layers which were formed during the formation of Lowry on the inside Ox trench 10. Layers 16, 25 are then covered with a layer of photo resist. The latter is patterned and developed in a well-known manner exposing a portion of nitride layer 25.
Then, using RYE, perchers of nitride layer 25 and oxide layer 16 are removed exposing a portion of substrate 4 in which a portion of source region 6 is to be formed, the top of plug 12 and ROW regions 9.
A thin layer of heavily doped p -conductivity type polycrystalline silicon is deposited from boron doped Solon end patterned using well-known photo lithographic and etching techniques to form bridge region 14 which interconnects source region 6 and the top of plug 12 which are spaced from each other by a portion of insulation layer 13. The patterning of the polycrystalline layer leaves a surface portion of substrate 4 exposed. Using well-known ion implantation techniques, a very shallow boron implant is made in the exposed portion of substrate 4 forming a portion of source region 6.
The remaining portion of source region 6 is formed by out-diffusion of Dupont from bridge region 14 during an annealing step which activates the shallow boron implant. It should be noted that the out-diffused portion of source region 6 is butted against insulator layer 13 resulting in cell area reduction.

At this point, using nitride layer 25 as a mask, an oxide layer is thermally grown and forms insulation over the exposed portion of substrate I, bridge region 14 and any remaining exposed surface of plug 12. At the same time, FOX region 9 undergoes further growth thereby increasing its thickness from that provided in the initial ROW growth step.
Because it was recognized that a step would be taken later on in the process which was tantamount to another ROW growth step, the initial REX growth stew was limited to produce rather thin ROW region. As a result, RYE etching of trench 10 through ROW region 9 was simplified and ROW bird's beak formation was reduced.

After the growth of the last mentioned oxide layer, nitride layer 25 is removed by wet etching. A layer of heavily doped n -conductivity type polycrystal-line silicon is deposited and patterned using conventional photo lithographic and etching tech-15 piques to Norm gate electrode 15 and element 18,19 which connects to the gate electrodes of adjacent cells as shown in FIG. 2. At this point, substrate 4 is subjected to a boron ion implantation step which forms self-aligned drain region 7 in substrate 4 using a ROW region 9 and gate electrode 15 as an implantation mask. The Dupont concentrations in both drain region 7 and source region 6 are lx102 atoms cm 3 and 1x1019 atoms cm 3, respectively.
After implanting drain region 7, substrate 4 is subjected to a thermal oxide growth step to insulate gate electrode 15, element 18 and the surface of substrate 4 in which drain region 7 was implanted.
Metallization is then applied after a deposited photo resist layer is exposed, patterned and developed. The structure resulting from the foregoing process steps is shown in FIG. 1.

I

At this point, it should be appreciated that, while only a single DRAM cell 1 has been shown in FIG. 1, a plurality of DRAM cells 1 are normally formed in n-well 5 and fabricated simultaneously therein in the same manner as described hereinabove. It should also be appreciated that, while an n-well 5 has been shown in FIG. 1, a p-well may just as easily be used. Then, of course, the conductivity types of source and drain regions 6,7, respectively, and substrate portions 8,11 should be changed to n-conductivity type.

The DRY cell described above is compatible with epita~ial CMOS technology. As previously indicated, higher packing density is achievable because of the elimination of punch-through current between trenches and low soft error rates are obtained.
Also, stored charge is disturbed much less in the present cell. Finally, the resulting structure has a relatively flat surface topology.

In operation, DRAM cell 1 has potentials of either zero or five volts applied to drain 7 of access transistor 2 from pulsed source 24. At the same time either zero or five volts is being applied to drain 7, zero volts is applied to gate electrode 15 rendering access transistor 2 conductive Thus, with substrate 4 grounded, a binary "ill may be written into storage capacitor 3 by applying five volts to drain 7 and zero volts to gate electrode 15 charging electrode or plug 12 to a potential of five volts. A binary "0" may be written into storage capacitor 3 by applying zero volts to both drain 7 I

and Nate electrode 15 charging electrode 12 to a potential equal to the absolute value of the thresh hold. Both binary states may be read by applying zero volts to gate electrode 15.

As previously indicated, the conductivity types shown in DROP cell 1 may be charged to opposite conductivity type without departing from the spirit of the present invention. Thus, with substrate 4 grounded, a binary "1" may be written into storage lo capacitor 3 by applying five volts to both drain 7 and gate electrode 15 charging electrode 12 to a potential or five volts minus the threshold voltage of access transistor 2. A binary "O" may be written into storage capacitor 3 by applying zero volts to drain 7 and jive volts to gate electrode 15 charging electrode 12 to approximately zero volts. Both binary states may be read by applying five volts to gate electrode 15.

Claims (37)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A dynamic random access memory cell comprising a substrate at least a portion of which is highly conductive, a well region disposed in said substrate, at least one access device disposed in said well region, and at least one storage means extending from the surface of said well into said substrate.

2. A dynamic random access memory cell according to Claim 1 further including means for inter-connecting said at least one access device and said at least one storage means.

3. A dynamic random access memory cell according to Claim 1 further including means connected to said well region for applying a bias connected to said well region.

4. A dynamic random access memory cell according to Claim 1 further including means connected to said at least one access device for transfer-ring binary information to and from said at least one storage means.

5. A dynamic random access memory cell according to Claim 1 wherein said substrate is made of semiconductor material at least a portion of which it heavily doped.

6. A dynamic random access memory cell according to Claim 1 wherein said well region is a region of semiconductor material.

7. A dynamic random access memory cell according to Claim 1 wherein said at least one access device is a field effect transistor.

8. A dynamic random access memory cell according to Claim 1 wherein said at least one storage means is an electrode disposed in insulated spaced relationship with said substrate.

9. A dynamic random access memory cell according to Claim 1 wherein said substrate includes a heavily doped portion and a lightly doped portion disposed over said heavily doped portion.

10. A dynamic random access memory cell according to Claim 2 further including means connected to said well region for applying a bias to said well region.

11. A dynamic random access memory cell according to Claim 2 further including means connected to said at least one access device for transfer-ring binary information to and from said at least one storage means.

12. A dynamic random access memory cell according to Claim 3 wherein said means for applying a bias is a voltage source.

13. A dynamic random access memory cell according to Claim 4 wherein said means for transferring binary information includes a pair of pulsed voltage sources connected to said at least one access device.

14. A dynamic random access memory cell according to Claim 5 wherein said semiconductor material is silicon of n-conductivity or p-conductivity type.

15. A dynamic random access memory cell according to Claim 6 wherein said semiconductor material is silicon of p-conductivity or n-conductivity type.

16. A dynamic random access memory cell according to Claim 8 wherein said electrode is made of heavily doped polycrystalline silicon.

17. A dynamic random access memory cell according to Claim 9 wherein said well region is disposed in said lightly doped portion of said substrate.

18. A dynamic random access memory cell according to Claim 10 further including means connected to said at least one access device for trans-ferring binary information to and from said at least one storage means.

19. A dynamic random access memory cell according to Claim 17 wherein said storage means extends from the surface of said well, through said lightly doped portion of said substrate into said heavily doped portion of said substrate.

20. A dynamic random access memory cell comprising a counterelectrode at least a portion of which is highly conductive, a well region disposed in said counterelectrode, at least one access device disposed in said well region, at least one trench extending from the surface of said well region through said well region into said counterelectrode, and,

Claim 20 Cont'd at least one storage electrode disposed in insulated spaced relationship with and in said at least one trench.

21. A dynamic random access memory cell according to Claim 20 further including means for inter-connecting said at least one storage electrode and said at least one access device.

22. A dynamic random access memory cell according to Claim 21 further including means connected to said well region for applying a bias to said well region.

23. A dynamic random access memory cell according to Claim 22 further including means connected to said at least one access device for trans-ferring binary information to and from said at least one storage electrode.

24. A dynamic random access memory cell according to Claim 23 wherein said counterelectrode is a semiconductor substrate at least a portion or which is heavily doped.

25. A dynamic random access memory cell according to Claim 24 wherein said well region is a region of semiconductor material.

26. A dynamic random access memory cell according to Claim 25 wherein said at least one access device is a field effect transistor.

27. A dynamic random access memory cell according to Claim 26 wherein said at least one storage electrode is made of heavily doped, poly-crystalline semiconductor material.

28. A dynamic random access memory cell according to Claim 27 wherein said means for intercon-necting is a region of polycrystalline semicon-ductor material.

29. A dynamic random access memory cell according to Claim 28 wherein said semiconductor material is silicon.

30. A dynamic random access memory cell comprising a semiconductor substrate having a lightly doped region of one conductivity type overlying a heavily doped region of the same conductivity type, a well of second conductivity type disposed in said lightly doped region, at least one access transistor disposed in said well, at least one trench extending from the surface of said well through said well and said lightly doped region into said heavily doped region, and, at least one storage electrode disposed in insulated spaced relationship with and in said at least one trench.

31. A dynamic random access memory cell according to Claim 30 further including means for inter-connecting said at least one storage electrode and said at least one access transistor.

32. A dynamic random access memory cell according to Claim 31 further including means connected to said well for applying a bias to said well.

33. A dynamic random access memory cell according to Claim 32 further including means connected to said at least one access transistor for transferring binary information to and from said at least one storage electrode.

34. A dynamic random access memory cell according to Claim 33 wherein said at least one access transistor is a field effect transistor.

35. A dynamic random access memory cell according to Claim 34 wherein said at least one storage electrode is made of heavily doped, poly-crystalline semiconductor material.

36. A dynamic random access memory cell according to Claim 35 wherein said means for interconnecting is a region of polycrystalline semiconductor material.

37. A dynamic random access memory cell according to Claim 36 wherein said semiconductor material is silicon.