KR900000635B1 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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KR900000635B1
KR900000635B1 KR1019850008857A KR850008857A KR900000635B1 KR 900000635 B1 KR900000635 B1 KR 900000635B1 KR 1019850008857 A KR1019850008857 A KR 1019850008857A KR 850008857 A KR850008857 A KR 850008857A KR 900000635 B1 KR900000635 B1 KR 900000635B1
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capacitor
insulating film
gate electrode
trench
substrate
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KR860005447A (en
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시즈오 사다와
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가부시끼가이샤 도오시바
사바 교오이찌
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Abstract

The semiconductor device with capacitor for alpha particle protection comprises; a field isolation layer (12) formed on a first type substrate (11), a gate electrode (15), and regions (16,17) of the second type adjacent the gate electrode. A trench (19) in the substrate contains a condenser. The trench is formed in the field isolation layer (12) and in the substrate under the layer. The condenser has more than one trench. A first electrode on the condenser insulator layer (20) or a second electrode on the condenser gate insulation layer may be coupled to one of the second type regions.

Description

반도체 기억장치Semiconductor memory

제1도는 종래의 DRAM의 단면도.1 is a cross-sectional view of a conventional DRAM.

제2도 내지 제7도는 본 발명의 실시예에서 DRAM을 얻기 위한 제조공정을 나타낸 단면도.2 to 7 are sectional views showing the manufacturing process for obtaining DRAM in the embodiment of the present invention.

제8도는 상기 DRAM의 평면도.8 is a plan view of the DRAM.

제9도는 제7도 및 제8도에 나타난 등가회로도.9 is an equivalent circuit diagram shown in FIGS. 7 and 8. FIG.

제10도는 제7도의 일부단면도.10 is a partial cross-sectional view of FIG.

제11도는 제7도의 일부평면도.11 is a partial plan view of FIG.

제12도는 본 발명의 다른 실시예의 단면도이다.12 is a cross-sectional view of another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 11 : P형 실리콘 기판 1, 12 : 셀사이의 분리절연막1, 11: P-type silicon substrate 1, 12: Separation insulating film between cells

2, 13 : 게이트산화막 4, 15 : 전달게이트 전극2, 13 gate oxide film 4, 15 transfer gate electrode

5: 캐패시터게이트 산화막 6 : 캐패시터게이트 전극5: capacitor gate oxide film 6: capacitor gate electrode

7, 8, 16, 17 : N+형 확산층 9, 19 : 도랑7, 8, 16, 17: N + type diffusion layer 9, 19: ditch

14 : 제1다결정실리콘막 18, 20 : 열산화막14: first polysilicon film 18, 20: thermal oxide film

21 : 게이트전극 22 : 캐패시터게이트 절연막21 gate electrode 22 capacitor gate insulating film

23 : 개공부 23 : 캐패시터게이트 전극23: opening 23: capacitor gate electrode

25 : CVD산화막 26 : 접촉구멍25 CVD oxide film 26 contact hole

27 : Al전극27: Al electrode

본 발명은 반도체 기억장치에 관한 것으로, 특히 개량된 다이나믹 RAM의 메모리셀 캐패시터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a memory cell capacitor of an improved dynamic RAM.

최근에 이르러 다이나믹 램덤엑세스메모리(이하 DRAM이라고 칭함) 는 1층마다의 집적도가 향상되어 지고 있음에 따라 더욱더 메모리셀의 캐패시터 면적이 작아지고 있는바, 그러나 α선에 의한 소프트에러를 방지하기 위해서는 최소한 메모리셀의 캐패시터용량으로서 50∼60fF 값이 필요하게 된다.In recent years, as the density of dynamic random access memory (hereinafter referred to as DRAM) has been improved for each layer, the capacitor area of the memory cell has become smaller. However, in order to prevent soft errors caused by? As a capacitor capacity of the memory cell, a value of 50 to 60 fF is required.

이 때문에 제1도에 도시되어 있듯이 반도체 기판에 도랑을 설치하므로서 캐피시터 용량을 증대시키는 시도가 있었다.For this reason, as shown in FIG. 1, there has been an attempt to increase the capacitor capacity by providing a trench in the semiconductor substrate.

즉, 제1도에 있어서 예컨대 P형 실리콘 기판(1)의 표면에는 셀사이의 분리절연막(2)이 형성되어 있고, 셀사이의 분리절연막(2)에 둘러쌓인 기판(1)의 소자 영역위에는 게이트 산화막(3)을 매개한 전달 게이트전극(4)이 형성되어져 있다. 또 소자영역의 일부에는 도랑이 형성되고, 도랑의 내면을 포함한 기판(1)표면의 일부에는 캐패시터게이트산화막(5)이 형성되며, 다시 캐피시터게이트산화막(5)위에는 캐패시터게이트 적극(6)이 형성된다.That is, in FIG. 1, for example, the isolation insulating film 2 between cells is formed on the surface of the P-type silicon substrate 1, and on the element region of the substrate 1 surrounded by the isolation insulating film 2 between cells. The transfer gate electrode 4 via the gate oxide film 3 is formed. A trench is formed in a part of the device region, a capacitor gate oxide film 5 is formed on a part of the surface of the substrate 1 including the inner surface of the trench, and a capacitor gate positive electrode 6 is formed on the capacitor gate oxide film 5 again. .

상기 캐패시터게이트 전극(6)은 셀사이의 분리절연막(2) 위에서 연장되고, 다수의 메모리셀에 걸쳐 형성되며, 다시 전달게이트 전극(4)의 양측기판(1) 표면에는 소오스, 드레인으로 구성된 N+형 확산층(7)(8)이 형성된다.The capacitor gate electrode 6 extends over the isolation insulating film 2 between the cells, is formed over a plurality of memory cells, and is formed on the surfaces of both substrates 1 of the transfer gate electrode 4 by N +. Type diffusion layers 7 and 8 are formed.

제1도에 도시된 DRAM은 도랑의 내면을 캐패시터의 일부가 되도록 하므로서 효과적으로 패캐시터 용량을 증가시킬수가 있게 된다.The DRAM shown in FIG. 1 makes it possible to effectively increase the capacitor capacity by making the inner surface of the trench part of the capacitor.

그런데, 다시 DRAM의 집적도를 향상시키고, 그위에 캐패시터용량을 일정치 이상으로 유지되며, 소프트에러를 방지하기 위해서는 예컨대 도량의 깊이를 깊게 할 필요가 발생된다.By the way, in order to improve the density of DRAM again, the capacitor capacity is kept above a certain value, and the depth of the quantity is needed to be deepened, for example, in order to prevent a soft error.

예컨대 도량의 개공부(開孔部)를 a㎛×a㎛의 정방형패턴으로, 깊이를h㎛로 해서 도랑의 표면적을 계산하면 (4ah＋a2)로 된다. 이 경우 1개의 도랑에 대해서의 용량을 유지시키면서 개공부의 면적을 미세화 시켜가면 h를 크게 할 필요가 있게 된다.For example, the surface area of the trench is calculated as (4ah + a 2 ) when the aperture of the measurement is a square pattern of a μm × a μm and the depth is h μm. In this case, when the area of the opening is made fine while maintaining the capacity for one trench, h needs to be increased.

그러나, 도랑의 깊이를 깊게되도록 하면 도랑내의 세정문제등이 커지게 되므로 양산기술적으로는 상당히 곤란한 점이 따르게 된다.However, if the depth of the trench is deepened, the problem of cleaning in the trench increases, which is quite difficult technically in mass production.

한편, 캐패시터게이트산화막의 막두께를 얇게 하므로서 캐패시터 용량을 일정치 이상으로 유지시켜지게 되는 것을 고려한다면, 캐패시터게이트산화막의 막두께는 도랑의 엣지에서의 전계집중에 의한 턴널전류등이 리이크특성의 열화를 방지하는 필요로부터 그 하한에 한계가 있게 되므로 지나치게 얇게 할수는 없게 된다.On the other hand, considering that the capacitor capacity is kept above a certain value by thinning the film thickness of the capacitor gate oxide film, the film thickness of the capacitor gate oxide film has a leakage characteristic such as a tunnel current due to electric field concentration at the edge of the trench. Since the lower limit is limited from the need to prevent deterioration, it cannot be made too thin.

본 발명은 상기한 점을 감안하여 발명한 것으로서, 소프트에러에 대한 내성(耐性)이 높고 집적도를 향상시킬 수 있는 반도체 기억장치를 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object thereof is to provide a semiconductor memory device which is highly resistant to soft errors and capable of improving the degree of integration.

상기 목적을 달성시키기 위해서 본발명의 반도체 기억장치는 제1도전형의 반도체기판 표면에 형성되어지는 셀사이의 분리절연막과, 해당 셀사이의 분리절연막에 둘러쌓인 기판위에서 게이트 절연막을 매개하여 형성되는 게이트 전극, 해당 게이트 전극의 양측기판표면에 형성되는 제2도전형의 확산층, 상기 셀사이의 분리 절연막 및 그 하부기판에 걸펴 형성되는 도랑, 해당도랑에 면하는 기판표면에 형성된는 절연막, 해당도랑의 내면을 포함함 셀사이의 분리절연막위에 캐패시터절연막을 개재시켜 형성되는 셀플레이트(cell plate)의 게이트전극 및, 캐패시터게이트 전극으로 구성되는 캐패시터부를 구비한 것을 특징으로 하는 것이다.In order to achieve the above object, the semiconductor memory device of the present invention is formed through a separation insulating film between cells formed on the surface of a semiconductor substrate of the first conductive type and a gate insulating film on a substrate surrounded by the insulating insulating film between the cells. A gate electrode, a second conductive diffusion layer formed on both substrate surfaces of the gate electrode, a dividing insulating film between the cells and a trench formed over the lower substrate, and an insulating film formed on the substrate surface facing the trench. It includes a gate electrode of a cell plate formed by interposing a capacitor insulating film on the isolation insulating film between cells including the inner surface, and a capacitor portion consisting of a capacitor gate electrode.

이하 본 발명의 실시예를 제2도 내지 제8도를 참조하고 제조방법을 병기해서 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

우선 제2도에 도시된 것처럼 예컨데 P형 실리콘 기판(11) 표면에 선택산화법에 의해 셀사이의 분리절연막(12)을 형성하고, 셀사이의 분리적연막에 둘러쌓인 기판(11)의 소자영역표면에 전달트랜지스터의 게이트산화막(13)을 형성한다.First, as shown in FIG. 2, for example, the isolation insulating film 12 between cells is formed on the surface of the P-type silicon substrate 11 by selective oxidation, and the device region of the substrate 11 surrounded by the separate insulating film between cells is formed. The gate oxide film 13 of the transfer transistor is formed on the surface.

계속해서 전면에 전달게이트 전극으로 되는 제1다결정 실리콘막(14)을 퇴적하고, 이어서 제3도에 도시된 것처럼 사진식각법에 의해 제1다결정 실리콘막(14)을 패터닝해서 전달게이트 전극(워드선 :15)을 형성하며, 이로부터 전달 게이트전극(15)을 마스크로서 노출된 게이트산화막(13)을 에칭한 후, 예컨대 비소를 이온주입하는 것에 의해 소오스, 드레인로 구성되는 N+형 확산층(16)(17)을 형성한다.Subsequently, a first polycrystalline silicon film 14 serving as a transfer gate electrode is deposited on the entire surface, and then the first polycrystalline silicon film 14 is patterned by photolithography as shown in FIG. A line 15 is formed, from which the gate oxide film 13 exposed using the transfer gate electrode 15 as a mask is etched, and then an N + type diffusion layer 16 composed of a source and a drain, for example, by ion implantation of arsenic. (17).

계속해서 열산화를 행하며 노출된 기판(11) 및 전달게이트 전극(15)의 표면에다 열산화막(18)을 형성하고, 이어서 제4도에 도시된 것처럼 일부를 선택적으로 에칭해서 다시 셀사이의 분리절연막(12)하의 기판(11) 일부도 에칭되어 도랑(19)을 형성한다. 계속해서 제5도 도시된 것처럼 열산화를 행하여 도랑(19) 내에서 노출된 기판(11) 표면에다 막두께가 500Å정도의 열산화막(20)을 형성하고, 이어서 전면에 제2다결정 실리콘막을 퇴적한 후 사진식각법에 의해 그 일부를 선택적으로 에칭하며, 상기 에칭에 의해 일부가 셀사이의 분리절연막(12) 및 열산화막(20)에 따라 도랑(19) 내에 매설되므로 다른 부분이 셀사이의 분리절연막(12) 위를 다수 메모리셀에 걸쳐 넓은 셀플레이트의 게이트전극(21)을 형성한다.Subsequently, thermal oxidation is performed to form a thermal oxide film 18 on the exposed substrate 11 and the transfer gate electrode 15, and then selectively etch a portion of the cell as shown in FIG. A portion of the substrate 11 under the insulating film 12 is also etched to form the trench 19. Subsequently, as shown in FIG. 5, thermal oxidation is performed to form a thermal oxide film 20 having a thickness of about 500 kPa on the exposed surface of the substrate 11 in the trench 19, and then a second polycrystalline silicon film is deposited on the entire surface. After that, a part of the part is selectively etched by photolithography, and part of the part is buried in the trench 19 according to the isolation insulating film 12 and the thermal oxide film 20 between the cells, and the other part is interposed between the cells. A gate electrode 21 of a wide cell plate is formed over the isolation insulating film 12 over a plurality of memory cells.

계속해어 열산화를 행하여 셀플레이트의 게이트전극(21)의 표면에 캐패시터케이트 절연막(22)을 형성한다.Subsequently, thermal oxidation is performed to form a capacitor insulating film 22 on the surface of the gate electrode 21 of the cell plate.

다음으로 제6도에 도시된 것처럼 사진식각법에 의해 N+형 확산층(17) 위의 열산화막(18)에 개공부(23)을 형성하고, 계속해서 전면에 제3다결정실리콘막을 퇴적시킨 후 패터닝해서 캐패시터게이트 전극(24)을 형성하며, 상기 캐패시터게이트 전극(24)은 셀플레이트의 게이트전극(21) 위에 캐패시터게이트 절연막(22)을 매개하여 형성시켜 N+형 확산층(17)과 접속되어 있다.Next, as shown in FIG. 6, an opening 23 is formed in the thermal oxide film 18 on the N + type diffusion layer 17 by photolithography, and then a third polysilicon film is deposited on the entire surface, followed by patterning. The capacitor gate electrode 24 is formed, and the capacitor gate electrode 24 is formed on the gate electrode 21 of the cell plate via the capacitor gate insulating film 22 and connected to the N + type diffusion layer 17.

계속해서 제7도 내지 제8도에 도시되어 있는 것처럼 전면에 CVD산화막(25)을 퇴적한후 N+형 확산층(16)위에 비트선용 접촉구멍(Comtact hole : 26)을 개공하고, 이어서 전극면에 Al막을 증착한후 패터닝해서 비트선으로 되는 Al전극(27)을 형성하여 다이나믹메모리셀을 제조한다. 또 제7도는 제8도의 F-F'선에 따른 확대단면도로서, 제8도는 Al전극(비트선 : 27)이 생략되어 있다.Subsequently, after depositing the CVD oxide film 25 on the entire surface as shown in FIGS. 7 to 8, a bit line contact hole 26 is opened on the N + type diffusion layer 16, and then on the electrode surface. An Al film is deposited and then patterned to form an Al electrode 27 which becomes a bit line to manufacture a dynamic memory cell. FIG. 7 is an enlarged cross-sectional view taken along the line F-F 'of FIG. 8, and in FIG. 8, the Al electrode (bit line 27) is omitted.

제7도 및 제8도에 도시된 다이나믹 RAM의 메모리셀로서 캐패시터부는 일부가 셀사이의 분리절연막(12)과 그밑의 기판(11) 내에 형성된 열산화막(20)에 따르도록 도랑(R) 내에 매설되고, 다른 부분이 셀사이의 분리절연막(12) 위를 다수 메모리셀에 걸쳐 넓은 셀플레이타의 게이트전극(21), 셀플레이타의 게이트전극(21)표면에 형성되는 캐패시터게이트 절연막(22) 및 캐패시터게이트전염막(22) 위에 형성되어 기판(1)의 일부(상기 실시예에서는 N+형 확산층(17))와 접속된 캐패시터게이트 전극(24)으로 구성된다.The capacitor portion of the dynamic RAM shown in FIGS. 7 and 8 as a capacitor part is formed in the trench R so that a part of the capacitor portion follows the thermal insulating film 20 formed in the isolation insulating film 12 between the cells and the substrate 11 below. A capacitor gate insulating film 22 formed on the surface of the gate electrode 21 of the wide cell plate, the gate electrode 21 of the cell plateta, and the other part buried, and the other portion over the isolation insulating film 12 between the cells; A capacitor gate electrode 24 is formed on the capacitor gate transfer film 22 and connected to a part of the substrate 1 (in the embodiment, the N + type diffusion layer 17).

제9도는 제7도 및 제8도에 나타난 등가회로도를 나타낸다. 도면중 부호 CA는 P형 실리콘 기판(11)과 N+형 확산층(17) 사이에, 부호 CB 는 셀플레이트의 게이트전극(21)과 N+형 확산층(17) 사이에, 부호 CC는 캐패시터게이트 전극(24)과 셀플레이트의 게이트전극(21) 사이에 각각 형성되는 용량이다. 셀플레이트의 게이트전극(21)은 예컨대 0.5V의 고정전위로 접속된다.9 shows an equivalent circuit diagram shown in FIGS. 7 and 8. In the figure, reference numeral CA denotes between the P-type silicon substrate 11 and the N + type diffusion layer 17, reference numeral CB denotes between the gate electrode 21 of the cell plate and the N + type diffusion layer 17, and reference numeral CC denotes a capacitor gate electrode ( 24 is a capacitor formed between the gate electrode 21 of the cell plate. The gate electrode 21 of the cell plate is connected at a fixed potential of, for example, 0.5V.

상기 DRAM은 셀사이의 분리절연막(12) 및 그 밑의 기판(11)에 걸쳐 형성된 도량(19)의 형상을 이용하는 것에 의해 실효적인 캐패시터의 표면적을 증가시키고, 캐패시터부의 대부분은 절연막(셀사이의 분리절연막(12)과 열산화막(20) 및 CVD 산화막(25))으로 둘러쌓여 있다. 이때문에 α선에 의해 발생되는 기판(11) 중의 소수 캐리어가 미치는 영향을 극히 적게할 수 있고, 소프트에러에 대한 내성이 높아진다.The DRAM increases the surface area of the effective capacitor by using the shape of the conductive film 19 formed over the isolation insulating film 12 between the cells and the substrate 11 underneath, and most of the capacitor portion is formed by an insulating film (between the cells). It is surrounded by a separation insulating film 12, a thermal oxide film 20 and a CVD oxide film 25. For this reason, the influence of the minority carrier in the board | substrate 11 generate | occur | produced by (alpha) line can be minimized, and the tolerance to a soft error becomes high.

이 결과 캐패스턴스 값을 센스증폭기 등의 머신을 고려하는 만큼 결정할 수 있고, 캐패시터용량을 적게할 수가 없다. 따라서, 캐패시터의 표면적을 감소시켜 집전도를 향상시키면서 캐패시터게이트 전극(22)의 막두께를 두껍게하여 리이크 특성을 개선시킨 것이다.As a result, the capacitance value can be determined by considering a machine such as a sense amplifier, and the capacitor capacity cannot be reduced. Therefore, while reducing the surface area of the capacitor to improve current collection, the thickness of the capacitor gate electrode 22 is increased to improve the leakage characteristics.

예를 들어 1메모리셀의 크기를 2㎛×5㎛로 가정하면 종래의 구조에 있어서 1메모리셀의 캐패시터의 평면적은 5.5μ㎡정도이고, 여기서 캐패시터게이트 산화막의 두께를 100Å로 하면 메모리용량은 19fF로 되어 충분한 센스증폭기를 확보할 수 없다.For example, assuming that the size of one memory cell is 2 μm × 5 μm, in the conventional structure, the planar area of the capacitor of one memory cell is about 5.5 μm 2, and when the thickness of the capacitor gate oxide is 100 μs, the memory capacity is 19fF. It is impossible to secure a sufficient sense amplifier.

그러나 제7도에 나타난 본 발명에 있어서 제10도 및 제11도에 도시된 것처럼 캐패시터 전극의 개구폭(W)을 0.75㎛로 하면 개구 면적은 0.75㎛×0.75㎛로 되고, 그 깊이(D)를 3㎛로 해서 각 부분의 막두께를 각각 필드산화막(12)의 두께를 4000Å, 열산화막,(20)의 막두께를 500Å, 셀플레이트의 게이트전극(21)의 막두께를 0.2㎛로 하면 도랑 캐패시터측면의 캐패시터면적 증대분은 0.75㎛×3㎛×4=9㎛2로 되어 전표면적은 14.52㎛2로 돈다.However, in the present invention shown in FIG. 7, when the opening width W of the capacitor electrode is 0.75 mu m, as shown in FIGS. 10 and 11, the opening area becomes 0.75 mu m x 0.75 mu m, and the depth D When the thickness of each portion is set to 3 mu m, the thickness of the field oxide film 12 is 4000 mu m, the thermal oxide film 20 is 500 mu m, and the thickness of the gate electrode 21 of the cell plate is 0.2 mu m. The increase in the capacitor area on the side of the trench capacitor is 0.75 µm x 3 µm x 4 = 9 µm 2 , and the total surface area is 14.52 µm 2 .

이것의 메모리 용량은 50fF로 되므로 충분한 센스증폭기를 향상시킬 수 있다.Since its memory capacity is 50fF, a sufficient sense amplifier can be improved.

이상의 설명에서는 캐패시터게이트 절연막(22)을 열산화막으로 형성하지만 질화실리콘막과 같은 절연막을 사용할 수도 있고, SiO2막과 SiN막의 이중막으로서도 바람직하다.In the above description, the capacitor gate insulating film 22 is formed of a thermal oxide film, but an insulating film such as a silicon nitride film may be used, and it is also preferable as a double film of the SiO 2 film and the SiN film.

이때문에 두께를 얇게 할 수 있으므로 부가용량을 크게할 수 있다.For this reason, since the thickness can be made thin, the additional capacity can be increased.

또한, 상기 DRAM에서는 인접하는 캐패시터끼리의 사이에 종래의 DRAM과 다른 기판을 매개하지 않기 대문에 상호 영향이 적어지게 된다. 이때문에 가공의 여유를 예상한 만큼 패턴설계를 할 수 있으므로 집적도를 향상시킬 수가 있다.In addition, in the DRAM, the mutual influence is less because the adjacent capacitors do not intervene with the conventional DRAM and other substrates. For this reason, pattern design can be carried out as much as the machining allowance is anticipated, and the density can be improved.

상기 DRAM에서는 셀사이의 분리절연막(12)밑의 기판(11)에 걸쳐 형성되는 도랑(19)의 깊이를 깊게 하는 것에 의해 캐패시터용량을 그 깊이에 따라 크게할 수가 있다.In the DRAM, the capacitor capacity can be increased according to the depth by increasing the depth of the trench 19 formed over the substrate 11 under the isolation insulating film 12 between cells.

이 결과 상기한 바와 같이 캐패시터의 표면적을 감소시켜 집적도를 향상시키고, 캐패시터게이트 전극(22)의 막두께를 두껍게 해서 리이크 특성을 개선하는 효과를 보다 1층 높게 할수 있다.As a result, as described above, the surface area of the capacitor can be reduced to improve the degree of integration, and the film thickness of the capacitor gate electrode 22 can be increased to increase the effect of improving the leakage characteristic by one layer.

상기 실시예에서는 전달게이트 전극(워드선 : 15)을 제1층 다결정실리콘막으로, 셀플레이트의 게이트전극(21)을 제2층 다결정실리콘막으로, 캐패시터게이트 전극(24)을 제3층 다결정실리콘막으로 각각 형성되지만, 셀플레이트의 게이트전극을 제2층 다결정실리콘막으로, 전달게이트 전극을 제3층 다결정실리콘막으로 각각 형성시켜도 좋다.In the above embodiment, the transfer gate electrode (word line) 15 is the first layer polycrystalline silicon film, the gate electrode 21 of the cell plate is the second layer polycrystalline silicon film, and the capacitor gate electrode 24 is the third layer polycrystalline. Although each is formed of a silicon film, the gate electrode of the cell plate may be formed of the second layer polycrystalline silicon film, and the transfer gate electrode may be formed of the third layer polycrystalline silicon film, respectively.

상기 실시예에서는 셀사이의 분리절연막위에 형성되는 캐패시터부에 대해서는 캐패시터 게이트 산화막의 하층 다결정실리콘막을 셀플리에트의 게이트전극, 상층의 다결정 실리콘막을 캐패시터게이트 전극으로서 각각 이용하지만, 제12도에 도시된 것처럼 하층의 다결정 실리콘막으로 캐패시터 게이트전극, 상층의 다결정 실리콘막을 셀플레이트의 게이트전극으로도 좋다.In the above embodiment, the lower polycrystalline silicon film of the capacitor gate oxide film is used as the gate electrode of the cell plate and the upper polycrystalline silicon film is used as the capacitor gate electrode for the capacitor portion formed on the isolation insulating film between the cells. Similarly, a capacitor gate electrode may be used as the lower polycrystalline silicon film and a polycrystalline silicon film may be used as the gate electrode of the cell plate.

상기한 바와 같이 본 발명의 반도체 기억장치에 의하면 캐패시터부의 대부분에 절연막으로 둘러쌓여 있는 것으로 소프트에러에 대한 내성이 높게 된다. 또 인접한 캐패시터끼리의 사이는 반도체기판을 매개하지 않으므로 상호 영향이 적고, 가공 여유가 예상한 만큼 좋기 때문에 집적도를 향상시킬 수가 있다. 셀 사리의 분리절연막 밑의 기판에 걸쳐 형성된 도랑의 길이를 깊게하는 것에 의해 캐패시터용량을 그깊이에 따라 크게 할 수 있는 장점이 있다.As described above, according to the semiconductor memory device of the present invention, since most of the capacitor portion is surrounded by an insulating film, resistance to soft errors is high. In addition, since the adjacent capacitors do not mediate the semiconductor substrate, the mutual influence is small and the processing margin is as good as expected, so that the degree of integration can be improved. By deepening the length of the trench formed over the substrate under the isolation insulating film of the cell, there is an advantage that the capacitor capacity can be increased according to the depth.

Claims (4)

제1도전형의 반도체기판(11) 표면에 형성되는 셀사이의 분리절연막(12)과, 해당 셀사이의 분리절연막(12)에 둘러쌓인 기판위에 게이트절연막(13)을 매개하여 형성되는 게이트전극(15), 해당 게이트전극(15)의 양측 기판표면에 형성되는 제2도전형의 확산층(16)(17) 및, 해당 확산층에 인접된 캐패시터부로 구성되고 있는 반도체 기억장치에 있어서, 상기 셀사이의 분리절연막(12) 및 그 하부의 기판에 걸쳐 형성되는 도랑(19)과, 해당 도랑에 면하는 기판표면에 형성되는 절연막, 해당 도랑의 내면을 포함한 셀사이의 분리절연막 위에 캐패시터게이트 절연막(22)을 개재하여 형성되는 셀플레이트의 게이트전극(21 또는 24) 및, 캐패시터게이트전극(21 또는 24)로 구성되는 캐패시터부를 구비함을 특징으로하는 반도체기억장치.A gate electrode formed through the gate insulating film 13 on the isolation insulating film 12 between the cells formed on the surface of the semiconductor substrate 11 of the first conductive type and the substrate surrounded by the isolation insulating film 12 between the cells. (15), a semiconductor memory device comprising a second conductive diffusion layer (16) (17) formed on both substrate surfaces of the gate electrode (15), and a capacitor portion adjacent to the diffusion layer. A capacitor gate insulating film 22 on the isolation insulating film 12 between the isolation insulating film 12 and the trench 19 formed over the lower substrate, the insulating film formed on the substrate surface facing the trench, and the cell including the inner surface of the trench. And a capacitor portion comprising a gate electrode (21 or 24) of a cell plate formed through a) and a capacitor gate electrode (21 or 24). 제1항에 있어서, 1개의 메모리셀의 캐패시터부에다 적어도 1개의 도랑이 포함되도록 셀사이의 분리절연막 및 그 하부의 기판에 걸쳐 도랑을 형성시킨 것을 특징으로하는 반도체 기억장치.2. The semiconductor memory device according to claim 1, wherein a trench is formed over the isolation insulating film between the cells and the substrate underneath so that at least one trench is included in the capacitor portion of one memory cell. 제1항에 있어서, 상기 캐패시터전극(24)을 상기 셀플레이트의 게이트전극(21) 상부에 캐패시터게이트절연막(22)을 매개하여 형성시킨 것을 특징으로하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein the capacitor electrode (24) is formed on the gate electrode (21) of the cell plate via a capacitor gate insulating film (22). 제1항에 있어서, 상기 셀플레이트의 게이트전극(24)의 상기 캐패시터게이트전극(21)의 상부에 캐패시터게이트 절연막(22)을 매개하여 형성된 것을 특징으로하는 반도체 기억장치.2. The semiconductor memory device according to claim 1, wherein a capacitor gate insulating film (22) is formed on top of said capacitor gate electrode (21) of the gate electrode (24) of said cell plate.
KR1019850008857A 1984-12-12 1985-11-27 Semiconductor memory device KR900000635B1 (en)

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JP59-262207 1984-12-12
JP59262207A JPS61140168A (en) 1984-12-12 1984-12-12 Semiconductor memory device

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KR860005447A KR860005447A (en) 1986-07-23
KR900000635B1 true KR900000635B1 (en) 1990-02-01

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JP2767104B2 (en) * 1987-03-30 1998-06-18 三菱電機株式会社 Method for manufacturing semiconductor device
JP2621181B2 (en) * 1987-06-12 1997-06-18 日本電気株式会社 MIS type semiconductor memory device
JPH0262073A (en) * 1988-08-26 1990-03-01 Mitsubishi Electric Corp Semiconductor memory device
JP2819520B2 (en) * 1991-05-07 1998-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション DRAM cell
JPH05175452A (en) * 1991-12-25 1993-07-13 Mitsubishi Electric Corp Semiconductor storage device and its manufacture
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