JPS60128658A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce distance between groove-shaped capacitors and to improve device capability to withstand errors in software by a method wherein a device is constituted of grooves extending from the surface of a semiconductor layer to the inside thereof, regions diffused with impurities of the first and second conductivity types, and electrodes extending from the inside at least to the vicinity of the openings with the intermediary of a capacitor-insulating film. CONSTITUTION:A part of each of activation regions 23a, 23b and both ends of an activation region 23c are respectively provided with groove-shaped capacitors 24a-24d. The groove-shaped capacitors 24a, 24b are positioned adjacent to each other. A p type diffused region 26a doped to be a diffused layer of the first conductivity type is formed in an Si substrate 21. In the p type diffused region 26a inside a groove 25a, an n type diffused region 27a of the second conductivity type is formed to be shallower than the p type diffused region 26a. In a groove- shaped capacitor 24a designed as such, an electrode 29 serves as the first capacitor electrode and the n type diffused region 27a as the second capacitor electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the structure of a trench type capacitor as a memory portion is improved.

[Technical background of the invention and its problems]

Semiconductor storage devices, including dynamic memory,
The storage capacity has increased four times in about three years due to advances in microfabrication technology. With the increase in memory capacity, the area of memory cells is rapidly decreasing (although the storage capacitor value of memory cells is increasing from rough 1 to S/N for error prevention and lens amplifier sensing). In order to secure the ratio, it is necessary to maintain a large value of several tens of F.

By the way, in order to increase the capacitor value per unit area compared to the past, the MO3 structure insulating film that constitutes the storage capacitor has been made thinner, and the insulating film material has been changed from silicon oxide film to silicon nitride film. There is. However, since these storage capacitors utilize the surface of a semiconductor substrate to form a MOS fM structure, there is a natural limit to obtaining a large capacitor value as the cell area becomes smaller.

For this reason, recently, H. S. unaml et al.
C(!11 (CCC) for Megabit
Dynamic MO3Memories'', I
international E 1cctrlcDev
ices MeetingTecl+n1cal Di
gest, lecture number 26.9.1) I), 806-8
On 08 Dec 1982, a MOS memory having a trench type capacitor with the structure shown in FIG. 1 was announced. That is, 1 in FIG. 1 is, for example, a p-type silicon substrate, and a deep (for example, about 3 to 5 μm) groove portion 2 is provided extending from the surface of this substrate 1 to the inside. A capacitor electrode 3 made of $1 layer polycrystalline silicon is provided around the bottom part of the trench 2 with a capacitor insulating film 4 interposed therebetween. This capacitor insulating film 4 (Si 02 /Si 3 N4
It consists of a three-layer film of /Si02)'1. Such a substrate 1, a groove 2, a capacitor insulating film 4, and a capacitor electrode 3
The groove is configured such that ca1<shita5. Also,
The silicon substrate 1 adjacent to the groove-shaped cap 5-
N+ type source and drain regions 6.7 electrically isolated from each other are provided on the surface of the substrate. On top of this, a gate electrode 9 made of a second layer of polycrystalline silicon is provided via a gate oxide film 8 (X).
A transfer transistor 10 is configured by the LI electrode 8 and the gate electrode 9. Furthermore, the source region 6 is the insulation 1! of the trench capacitor 5-. 4 I, and the drain region 7 is connected to a bit line (not shown). Note that 9' in the figure is the electrode of the adjacent memory cell.

However, as described in the literature, the MOS memory shown in FIG. However, there was a drawback that the distance between the trench capacitors between memory cells could not be shortened, making it impossible to realize high-density memory cells. That is, it is generally required that the drain junction capacity of a transfer transistor constituting a memory cell be reduced in order to reduce the human line capacitance. For this reason, it is necessary to lower 11Mlff of the p-type silicon substrate, but this spreads a depletion layer in the substrate near the MOS IM capacitor, making it easy to cause the pan-de-through phenomenon. Such a bump-through phenomenon can generally be prevented by implanting impurity ions from near the surface of the silicon substrate. However, a trench capacitor made by forming a deep trench 2 in a silicon substrate 1 as shown in FIG.
In the case of large capacitors, it is difficult to implant impurity ions deep into the silicon substrate 1, so a punch-through problem occurs between the bottoms of adjacent trench capacitors.
The major drawback was that it could not be prevented.

Therefore, in the conventional structure, it is necessary to leave a long distance between the trench capacitors between memory cells, making it extremely difficult to realize a high density memory cell.

In addition, in the structure shown in FIG. 1, the depletion layer is extended by the trench capacitor 5- deep in the silicon substrate 1, and the charge generated by the incidence of α rays is likely to be collected by the funneling phenomenon, so it is said to be vulnerable to soft errors. There were drawbacks.

[Purpose of the invention]

The present invention provides a semiconductor layer 1 which is equipped with a trench capacitor having a large capacitor value per unit area, can significantly shorten the distance between the trench capacitors, and has excellent soft error resistance.
1! The aim is to provide equipment.

[Summary of the invention]

The present invention includes a semiconductor layer of a first conductivity type, a groove provided from the surface to the inside of the conductor layer, and a semiconductor layer with a higher i degree than the semiconductor layer provided in the semiconductor layer on the inner surface of the groove. a first conductivity type impurity diffusion region, a second conductivity type impurity diffusion region provided in the impurity diffusion region on the inner surface of the trench and having a junction depth shallower than the diffusion region; and an electrode provided through a capacitor insulating film, wherein the electrode is a first :1-dopasitor electrode, and the impurity diffusion region of the second conductivity type is a second capacitor electrode. It is characterized by being equipped with an IT-type key 17 pacita. In these (M construction)
The impurity diffusion region of the first conductivity type suppresses the extension of the depletion layer in the deep part of the trench capacitor, thereby preventing the punch-through phenomenon between adjacent trench capacitors, thereby enabling high-density memory cells, and A similar effect of the first conductivity type impurity diffusion region improves soft error resistance, and furthermore, the junction capacitance between the first conductivity type impurity diffusion region and the second conductivity type impurity diffusion region improves the soft error resistance per unit area. A semiconductor memory device with increased capacitor value can be obtained.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a plan view showing a part of the dynamic Ivl OS memory, and FIG. 3 is a cross-sectional view corresponding to III-nu in FIG. 2. 21 in the figure is a p-type silicon substrate containing, for example, an acceptor impurity (boron, etc.) of 2×10 2 /cm 3 . A field oxide film 22 is provided on the silicon substrate 21, and a plurality of island-shaped active regions (memory cell regions) 238 to 23c are formed on the silicon substrate 21, separated by the field oxide film 22. There is. Groove type capacitors 24a to 24d are provided in a portion of these active regions 23a, 23b and at both ends of the active region 23C, respectively, and the groove type capacitors 24a, 24b are arranged adjacent to each other. As shown in FIG. 3, the trench capacitor 24a includes a trench 25a having a depth of, for example, 3 μnL, extending from the surface of the silicon substrate 21 to the inside thereof. The silicon substrate 21 on the inner surface of the groove 25a has a first groove.
An n-type diffusion region 26a is formed as a conductive type impurity diffusion region. The n-type diffusion region 26a has a depth of, for example, 0°4 μm, and has a concentration higher than that of the substrate 21, for example, 2×10”/cm3. , an n-type diffusion region M27a as a second conductivity type impurity diffusion region shallower than the n-type diffusion region 26a is formed.The n-type diffusion region 27a has a depth of 0.2 μmη and a concentration of, for example, 1.
X 10”/cm3.

An extending portion 28a is formed on the side surface of the day-shaped diffusion region 27a on the side opposite to the trench capacitor 24b.

An electrode 29 made of a first layer of polycrystalline silicon is provided from inside the groove 25a to at least around the opening of the groove 25a via a silicon oxide film 30a having a thickness of, for example, 200 mm as an insulating film for the capacitor. There is. In such a trench capacitor 24a, the electrode 29 functions as a first capacitor electrode, and the n-type diffusion region 27a functions as a second capacitor electrode. Note that the electrode 29 serves as a common electrode for each of the groove capacitors 24a to 241). On the other hand, the trench capacitor 24b is composed of a trench 25b, an n-type diffusion region 26b, an n-type diffusion region 27b1, an electrode 29, and a silicon oxide film 3ob. Although the trench type capacitor 24C124d is not shown in detail, it has a similar structure to the trench capacitors 24a, 2'4b.

Here, Fig. 4(a) shows a method for manufacturing a trench type capacitor.
This will be briefly explained with reference to (C). First, a field oxide film 22 is selectively formed on a p-type silicon substrate 21, and island-shaped active regions 23a and 23b (23c is not shown) are formed. An oxide film 31 having a thickness of approximately 1,000 wafers is formed. Subsequently, a photoresist is applied and a resist pattern (not shown) is formed on the portion of the oxide film 31 where the groove is to be formed by photolithography, and then the silicon substrate 21 is etched by reactive ion etching using the resist pattern as a mask. For example, grooves 25a, 25 with a depth of 3 μm are formed by selective etching.
b (as shown in FIG. 4(a)). After that, the resist pattern was peeled off.

Next, the oxide film 31 corresponding to part of the source region of the transfer 1 to transistor is selectively removed by photolithography, and then a silicon oxide film (or polycrystalline silicon The boron-doped silicon oxide film 32 is deposited by the CVD method.
is used as a diffusion source to thermally diffuse boron into the p-type silicon substrate 21 on the inner surface of the grooves 25a and 25b to form n-type diffusion regions 26a and 2.
6b (as shown in FIG. 4(b)). Subsequently, the boron-doped silicon oxide film 32 is removed, and the entire surface is covered with a phosphorous-doped silicon oxide film (or an arsenic 1-doped silicon film).
Polycrystalline silicon doped with phosphorus or arsenic Il'J)33
After depositing by CVD method, phosphorus is deposited in the p-type diffusion region 26a, using the phosphorus-doped silicon oxide film 33 as a diffusion source.
26b and the same diffusion region 26. n-type expansion regions 27a, 27b and extension portions 28a, 2 in a, 26b, respectively.
8b (as shown in FIG. 4(C)). After this, although not shown, the phosphorus-doped silicon oxide film is removed, the oxide film is also removed, and a thermal oxidation treatment is performed again to form a silicon oxide film on the exposed substrate surface including the inner surface of the groove. A one-layer polycrystalline silicon film is deposited and patterned to form an electrode from inside the trench to at least around the opening thereof, and using this electrode as a mask, the silicon oxide film is selectively etched to form a capacitor. Form a silicon oxide film.

Furthermore, a transfer transistor 348 is provided in each active region 23a to 23c adjacent to each trench type capacitor 24a to 24d.
~34d is formed. Transfer i transistor 34a
is an active region 23a adjacent to the trench type capacitor unit
N-type source and drain regions 35a and 36a provided electrically isolated from each other on the surface of the active region 23a, which includes at least these source and drain regions 35'a and 36a, are covered with goo 1 to oxide films. 37a, and an electrode 38a.

The n+ type source region 35a is connected to the trench capacitor 24.
It is connected to the extending portion 28a of the n-type diffusion region 27a that constitutes a. On the other hand, the transfer transistor 34b is n
+ type source and drain regions 35b, 36b, gate 1.
It is composed of an oxide film 37b and a goo electrode 38b, and the goo source region 35b is connected to the trench type capacitor 24.
It is connected to the extending portion 28b of the n-type diffusion region 27b constituting the region b. Further, the transfer transistor 34. C1
34 Furthermore, like each of the transfer transistors 34a and 3/1b, it is composed of a source, a train region, an oxide film on the gate 1 (all of which are not shown), and gate 1 electrodes 38c and 38d. Note that the transfer transistor 348.3
The gate electrodes 38a, 38b of the trench type capacitors 24c, 24d cross over the electrodes 29 of the trench type capacitors 24c, 24d via an oxide film (not shown), and the gate electrodes 38a, 38b of the transfer transistors 34c, 34d
Goo 1 to electrodes 38c and 38d are the groove capacitor 2
The electrodes 4a and 271 and above are crossed through oxide films 39a and 39b. Furthermore, each trench type capacitor 24
゜9-24d and each of the transfer transistors 348-3
An interlayer insulating film 4'Oh is formed on the silicon substrate 21 including 4d.
(A bit line 41.41 made of A1 is coated and on the interlayer insulating film 4o is connected to each gate electrode 38.
It is provided in a direction perpendicular to a to 38d. One of the pins 41 is connected to the transfer transistors 34a and 34b.
Contact holes 4 are formed in drain regions 36'a and 36b of
2a and 42b, respectively. The other pin I-line 41' is connected to the transfer 1 to transistors 34C and 34.
d to a common drain region (not shown) through a contact hole 42G. These pi-lf
! A protective insulating film 43 is coated on the interlayer insulating film 40 including 41 and 41-.

Therefore, according to the semiconductor memory device of the present invention, approximately 2×10 Since the n-type diffusion regions 26a and 26b having an impurity concentration of 0.5 cm are formed, the extension of the depletion layer to the silicon substrate 21 around the trench capacitors 24a and 24b is reduced by the presence of the p-type diffusion regions 26a and 26b. In fact, when the potential of the storage node is n
When there is a frost difference of 5 cm with respect to the type silicon substrate 21, p-type expansion Il! <Regions 26a, 26b and n-type diffusion regions 27a, 2
The width of the depletion layer extending between 7b was approximately 0.2 μmη.

As a result, the distance (A
Even if the n-type diffusion regions 26a and 26b are brought close to the 0°6 μm opening where they overlap, the pan death-through phenomenon between them can be prevented.In addition, in the groove-type -1-dopasita shown in FIG. A punch-through phenomenon already occurred when the distance between the trench capacitors was about 2 μm.This is an improvement of more than three times in terms of distance.Furthermore, in the present invention, the junction capacitance of the line to pin 1 does not increase at all.Therefore, By preventing the punch-through phenomenon between trench capacitors, high-density memory cells can be realized.

In addition, in the trench capacitor (for example, 24a), the n-type diffusion region 26a can suppress the extension of the depletion layer toward the substrate 21, and since the p-type diffusion region 26a acts as a potential barrier, It is possible to prevent carriers from gathering in the n-type diffusion region 27a of the trench capacitor 24a due to the funneling phenomenon, and
- A semiconductor memory device with excellent error resistance can be realized.

Furthermore, in the present invention, the n-type diffusion region 26a and the n-type diffusion region 2
7a, the trench type capacitor 24p has a high capacitance value per unit area. This makes it possible to achieve higher density memory cells. In fact, it has been found that the pn junction capacitance reaches approximately 30% of the capacitance value.

Note that in the above embodiment, a silicon oxide film is used as the capacitor insulating film, but the present invention is not limited to this. for example,
A composite film in which a silicon oxide film and a silicon nitride film are sandwiched in a sandwich manner, a silicon nitride film, or a second film of silicon oxide and tantalum oxide may be used.

In the above embodiment, an n-type silicon substrate was used as the semiconductor layer, but an n-type silicon substrate may also be used. in this case,
The first conductivity type impurity expansion 11 has a region of 11 type, and the second conductivity type impurity expansion 11! Expansion r4'! area (, jp type, transfer 1-
The transistor consists of a pzitunnel MOS I transistor.

In the above embodiment, explanation was given using 108 meters to digital as an example, but the same applies to static and 1OS meters.
Applicable to m. In this case, for example, a flip-flop type hill bistable 82 may be provided with a groove-type chip puncture at the front.

[Effect of Light] As detailed above, the present invention has J: it l; J'!
The capacitor value per contact point is 11!5, and the distance between the capacitor and the puncture is significantly shortened without causing a bump-through phenomenon. This makes it possible to increase the density of
The performance can be improved, and H-C has high density and high reliability.
'/Serikyuki one-piece device can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional dynamic MOS memory, FIG. 2 is a plan view of a dynamic MOS memory according to a fourth embodiment of the present invention, and FIG. - Figures (a) to (C) are cross-sectional views taken along the line -■, showing steps for forming the trench type capacitor of this embodiment. 21... N-type silicon substrate, 22... Field oxide film, 23a to 23C... Active region (memory cell),
24a to 24d...Trench capacitor, 25a
, 25b...groove portion, 26a, 26b...1) type diffusion region (first conductivity type impurity diffusion region), 27a, 27b
...11 type diffusion region (second conductivity type impurity diffusion region)
, 28a, 28b... Extension portion, 29... Electrode made of first layer polycrystalline silicon, 30a, 30b... Silicon oxide film (insulating film for capacitor), 32... Boron-doped silicon oxide film, 33... Phosphorus-doped silicon oxide film, 34a to 34d... Transfer transistor, 35a
, 35 b-n++ source region, 3.6a, 36b...
・N+ type drain regions 38a to 38d...Group 1 to electrode made of second layer polycrystalline silicon, 41.41...
bit line. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) A semiconductor layer of a first conductivity type, a trench provided extending from the surface of this semiconductor layer to the west, and a first conductivity type semiconductor layer with a higher concentration than the semiconductor layer provided in the semiconductor layer on the inner surface of the trench. A conductivity type impurity diffusion region and the diffusion region J provided in the impurity diffusion region on the inner surface of the trench: a second conductivity type impurity diffusion region 11 with a shallow junction depth; and an electrode provided through a capacitor insulating film, the electrode being a first capacitor electrode, and the second conductivity type impurity diffusion region being a second °1-dopasitor electrode. A semiconductor memory device characterized by having a trench-type capacitor of a 14V structure. (2) The semiconductor memory device according to claim 1, wherein the first conductivity type and second conductivity type impurity diffusion regions of the trench capacitor are formed by a double diffusion method. (3) The source and drain regions of the second conductivity type provided electrically isolated from each other on the surface of the semiconductor layer of the first conductivity type, and a gooey layer on the semiconductor layer portion including at least between these source and train regions. ~Equipped with a transfer transistor consisting of a gate electrode provided through an insulating film, one of the source and drain regions is connected to the second conductivity type impurity diffusion region of the trench capacitor, and the other is connected to the bit line. A semiconductor memory device according to claim 1, characterized in that: