JPS6223153A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To produce the capacitance of a memory capacitor largely while inhibiting the extension of a depletion layer in an silicon substrate by forming a P-N junction region around a trench formed into the memory capacitor by P-type and N-type impurities. CONSTITUTION:An inter-element isolation thick oxide film 2 is shaped into an silicon substrate 1, and the ions of phosphorus 3 and boron 4 are implanted near the surface of the silicon substrate 1 in a memory capacitor corresponding section to form a P-N junction. A trench 9 is shaped into the silicon substrate 1 while using an silicon oxide film 10 and a photo-resist film 11 as masks. The photo-resist film 11 is removed, phosphorus 3' and boron 4' are diffused into the silicon substrate 1 through a thermal diffusion, a P-N junction region is shaped around the trench 9, the silicon oxide film 10 employed as the mask is removed, a thin insulating film 5 for a capacitor is formed, and a cell plate 6 by polycrystalline silicon is shaped, thus acquiring memory capacitor structure.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to integrated circuits, especially MOS dynamic RA.
The present invention relates to a semiconductor memory device with an improved memory capacitor of M.

[Conventional technology]

Conventionally, in a memory capacitor of a MOS dynamic RAM, a thin insulating film is formed between a flat silicon substrate and an electrode to accumulate signal charges.

However, as the number of integrated devices increases, the area of memory cells is reduced and the capacitance of memory capacitors is reduced, resulting in problems such as soft errors.

As a countermeasure to this problem, as a means of increasing the memory capacitor capacity without increasing the memory cell area, a trench/inch capacitor structure has been proposed that increases the memory capacitor capacity by forming deep grooves in the silicon substrate and increasing the surface area. It has been. The prior art will be further explained below with reference to the drawings.

FIG. 2 shows a cross-sectional view of a conventional flat capacitor. In this figure, 1 indicates a silicon substrate, and 2 indicates a thick oxide film for isolation between elements. The memory capacitor utilizes a thin insulating film 5 between the silicon substrate 1 and the cell plate. In addition, 7 is the source domain diffusion layer of the transistor (MOS),
8 is a gate electrode.

In order to increase the capacitance of a memory capacitor, a method of forming a PN junction region by ion-implanting, for example, phosphorus 3 and horn 4 into the silicon substrate 1 in the capacitor region is also commonly used.

FIG. 3 shows an equivalent circuit of a memory cell portion of a MOS dynamic RAM. The signal transmitted from the bit line BL is word IIi! The switching transistor FET is turned on by boosting WL, and signal charges are accumulated in the memory capacitor. The memory capacitor capacity is the sum of the capacitor C0X formed by the thin insulating film 5 and the capacitor Cj formed by the PN junction.

On the other hand, FIG. 4 is a sectional view showing a conventional trench capacitor structure. Forming deep trenches 9 in the silicon substrate 1 increases the surface area. however,
Electrons generated by α particles diffuse in the silicon substrate 1, but trenches 9 formed deep in the silicon substrate 1
A wide depletion layer is formed around the silicon substrate 1, and the distance is close to the electrons generated in the silicon substrate 1, so that a large amount of electrons can be easily collected. Therefore, the signal stored in the capacitor is inverted, causing malfunction. So-called soft errors are more likely to occur.

[Problem that the invention seeks to solve]

In the case of the trench capacitor structure refined as described above, since the capacitor is formed in the silicon substrate 1, it is easily affected by soft errors due to α particles, and there is a problem that it is not a sufficient countermeasure.

This invention was made to solve these problems, and to increase capacity.

An object of the present invention is to provide a semiconductor memory device that can significantly improve soft errors.

[Means for solving problems]

In the semiconductor memory device according to the present invention, a PN junction region is formed around a trench formed in a memory capacitor using impurities of P and Nff1.

[Effect]

In this invention, since a PN junction region is formed around the trench formed in the memory capacitor, the capacitance of the memory capacitor can be increased and the spread of the depletion layer into the silicon substrate can be suppressed.

〔Example〕

FIGS. 1A to 1C are cross-sectional views showing a memory capacitor according to the present invention in the order of steps. First, after a thick oxide film 2 for element isolation is formed in the silicon substrate 1, near the surface of the silicon substrate 1 in the area corresponding to the memory capacitor,
P by ion implantation of phosphorus 3 and boron 4
Form an N junction.

After that, the silicon oxide film 10 and the silicon oxide film 1
1 as a mask, a trench 9 is formed in the silicon substrate 1 by a known RIE technique (FIG. 1(a)). Next K,
7 After removing the otonist film 11, phosphorus 3' and boron 4' are diffused into the silicon substrate 1 by thermal diffusion to form a KPN junction region around the trench 9 (see FIG. 1).
b)). At this time.

Since the area other than the edge 9 is covered with the silicon oxide film 10, the phosphorus 3' and boron 4' do not diffuse into the silicon substrate 1. Thereafter, after removing the silicon oxide film 10 used as a mask, a thin insulating film 5 for the capacitor is formed, and a cell V-toro made of polycrystalline silicon is formed to obtain a one-memo capacitor structure (first Figure (C)).

Since the memory capacitor structure thus obtained has a PN junction region formed around the trench 9, the capacitor Cj shown in FIG. 3 is obtained, and a larger memory capacitor capacity can be ensured.

Furthermore, since the PN junction suppresses the width of the depletion layer from expanding around the trench 9, the structure is such that it is difficult to collect electrons generated in the silicon substrate 1. As a result,
The error rate can be significantly improved.

In the above embodiments, phosphorus and poron were used as the PN junction forming impurities, but any P-type and N-type impurities may be used.For example, as the P-type impurity,
AA#Ga besides Poron.

Examples of Nfi impurities include In e Ti, etc.
Needless to say, other than phosphorus, As, Sb, Bi, etc. can be mentioned.

Further, the same effect can be obtained by using an NP junction instead of a PN junction.

〔Effect of the invention〕

As explained above, in this invention, since a PN or NP junction region is formed by P-type impurity and N-type impurity around the trenches formed in the memory capacitor, not only can the capacitance of the memory capacitor be increased, but also This has the advantage that the spread of the depletion layer in the silicon substrate can be suppressed, and the occurrence of soft errors can be significantly improved.

[Brief explanation of the drawing]

Figures 1 (1) to (c) are cross-sectional views of a punch capacitor showing the main steps of an embodiment of the present invention, Figure 2 is a cross-sectional view of a conventional flat capacitor structure, and Figure 3 is a cross-sectional view of a conventional flat capacitor structure. FIG. 4 is a cross-sectional view showing the structure of a conventional ton/inch capacitor. In the figure, 1 is a silicon substrate, 2 is a thick oxide film for element isolation, 3.3' is phosphorus, 4 and 4' are poron, 5 is a thin insulating film, 6 is a cell V-), and T is a source electrode. 9 is a trench, 10 is a silicon oxide film, and 11 is a photo/sist film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a semiconductor memory device having a memory capacitor, a trench is formed in the silicon substrate or well of the memory capacitor portion, and a PN layer containing P-type impurities and N-type impurities is formed at a required depth from the surface of the trench.
A semiconductor memory device characterized in that a junction or NP junction is formed and a cell plate is further provided on the surface of the trench with a thin insulating film interposed therebetween.