JPS59184555A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the lower limit of the impressed voltage onto a cell plate electrode by a method wherein the inner surface layer of a groove formed on the main surface of a semiconductor substrate is put in the conductivity type different from that of said substrate, and a capacitor wherein an insulation film and an electrode layer are formed is provided on the inner surface of the groove. CONSTITUTION:A groove is formed by etching an Si substrate 1, and an N type layer 13, the insulation film 14 for the capacitor and an electrode layer 15 are formed. Thus, the capacitor is formed by utilizing the groove, and a conductive layer of the conductivity type different from that of the Si substrate is provided on the surface of said substrate at the capacitor region, therefore the capacitor whose capacitance is large and which unnecessitates the voltage impression on the capacitor electrode can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (First Industrial Field) The present invention relates to a semiconductor integrated circuit device 2 including all capacitors formed on a groove (c) surface, and a method for manufacturing the same.

(Prior Art) Conventionally, as shown in FIG. 1 as a cross section of a cell capacitor of a semiconductor integrated circuit device, a silicon oxide film 22 and a cell root electrode are never bonded on the surface of a p-type silicon base. 3 all-laminated structures were used. The MO8 field effect red transistor adjacent to the cell capacitor is composed of n-type scattering layers 4 and 5, a gate oxide film 62, and a gate electrode 7. In order to increase the capacitance of the cell capacitor in the above structure, there are a method of increasing the area of the cell capacitor, a method 7j of thinning the silicon oxide film 2, and the like. However, increasing the cell capacitor area completely impedes high-density integration of devices.

Further, since the dielectric breakdown voltage of the silicon oxide film decreases due to the thinning of the silicon oxide film, an upper limit is imposed on the voltage applied to the cell plate electrode. On the other hand, in the structure of the cell capacitor described above, even if the potential of the n-diffused layer 5 reaches a high level, a voltage must be applied to the cell gate electrode that is sufficiently inverted to be below the cell root. In order to make effective use of the brute force, give the self-rate voltage enough time. In the range between the upper and lower limits of the 11L river that corresponds to the above cell rate, the thinning of the silicon oxide film makes the VC narrower, making it difficult to design the device in the conventional capacitor structure.

(Objective of the Invention) In order to overcome these drawbacks, the invention is to utilize the opening of the groove formed on the optical surface of the silicon substrate. In addition to increasing the effective capacitor area to 7JII, a layer of conductivity type different from that of the VC silicon substrate is formed on the surface of the silicon substrate directly mounted on which the cell capacitor is formed, and on the inner surface of the VC silicon substrate.
The object of the present invention is to provide a semiconductor integrated circuit device that eliminates the primary tray under the n voltage applied to the cell plate electrode by inverting the voltage under the rate electrode, and a method for manufacturing the same. be.

(Structure of the Invention) In order to achieve the above object, the present invention provides that the inner surface layer of the fL groove formed on the main surface of a conductivity type semiconductor substrate has a conductivity type km-L different from the conductivity type of the semiconductor substrate. and an insulating film and an electrode layer are formed on the inner optical surface of the groove, 11. The gist of the invention is a semiconductor integrated circuit device characterized in that a capacitor is provided.

Furthermore, the present invention includes a step of forming a groove on a predetermined chain acid on the main surface of a semiconductor substrate of a conductivity type, a step of forming a whole conductive layer different from the conductivity type of the semiconductor substrate on the inner surface of the groove, and a step of forming the conductive layer on a predetermined chain acid on the main surface of a semiconductor substrate. 2. A method for manufacturing a semiconductor integrated circuit device characterized by comprising the step of forming a capacitor by laminating an insulating film and an electrode layer in this order.

Specifically, the present invention applies to a semiconductor integrated circuit device having two capacitors in the tray type b! ;1. In doing so, the feature is that all conductive layers of different electrical types are formed between the substrate of the semiconductor device and the insulating layer for forming the capacitor. I can buy things.

Next, an example of an uninvented IM will be explained.

This embodiment is just one example, and without departing from the spirit of non-invention, it is possible for the lumberjack to make all kinds of changes and improvements every day.

(Example 1) A case will be described in which the present invention is applied to a p-type silicon substrate to form a capacitor.

The 'f'c field for the nfb silicon substrate is changed to an n-type layer and a tp-type layer, which will be described below. Figure 2 shows the substrate concentration 11
) Etching mask 9 used as a mask when etching the silicon substrate formed on the p-type silicon substrate 1 of ``72 to 10''I:rn' A cross-sectional view of the etched state of the resist 10 tray mask that has been completely patterned It is. As the etching mask 9, a silicon oxide film formed by converting the silicon substrate into kfl, or
Chemical vapor deposition method (CV) using silane P and oxygen
A silicon oxide film deposited by I) method is used. Etching of the silicon oxide film using 5 masks (4) is performed by reactive ion etching (hereinafter abbreviated as RIE) in an atmosphere of CF4 gas and hydrogen gas added.

After the resist was incinerated and removed by one oxygen lasma, the third
As shown in the figure, a silicon substrate 1 is etched using an etching mask 9 to form a groove 11. Etching of a silicon substrate is carried out using, for example, RI using CBrFsw under the conditions of a pressure of 14 mtorr and an i% frequency output of ioo w.
Do it at E'. When etching is carried out under the above RIE conditions using a silicon oxide film as an etching mask, the etching rate ratio between the silicon substrate and the silicon oxide film is about 4. Therefore, the thickness of the silicon oxide film used as an etching mask must be one-fourth or more of the depth of the carbonitride groove. The groove to be formed has a total width of 0.5 μm, for example.
The depth shall be 1.5 μm.

Next, after removing the silicon oxide film used as the etching mask 9 with a buffered hydrofluoric acid solution, as shown in FIG.
Phosphorus-doped silicon oxide film 12i is deposited and heat treated
N# layer 13i on silicon substrate light [II] containing groove inner surface ligation
be related to CVI at a temperature of about 400°C using phosphorus-doped silicon pupil membrane Hasilan, phosphine P and bleaching material)
Formed by law. Flow rate ratio of silane and phosphine i50
As phosphorus-doped silicon oxide film 'k Kishi Ao 0.3μm
After deposition, heat treatment 1-ri at 1000°C for 1 hour in nitrogen atmosphere and subsequent surface mu approximately 9 x 10"cm'
+'m, an n-type layer with a depth of about 0.27jm is obtained.

Here, we have explained the use of phosphorus diffusion from a phosphorus-doped silicon oxide film to form the n-type layer, but vapor phase diffusion sound using phosphine or antimony may also be used.

After removing 12 IJ-doped silicon oxide films of the n-type layer shown in FIG. 4 with a buffered hydrofluoric acid solution, 14 insulating films for capacitors are formed as shown in FIG. 5. As the insulating film 14, for example, a silicon oxide film is used. The silicon oxide film has a temperature of 900 to 1000 in a dry oxygen atmosphere.
For example, it is formed to a thickness of 150°C. At a phosphorus surface concentration of 1010 m-1 or less, the dependence of the oxidation rate on the phosphorus concentration is almost negligible, so oxidation can be carried out under the same conditions as for low-concentration silicon substrates and for drying plates.

Here, is a silicon oxide film used as an insulating film? I used it, but
A silicon nitride film, a tantalum oxide film, a laminated film of a silicon oxide film and a silicon nitride film or a tantalum oxide film, etc. may be used.

Next, polycrystalline silicon is deposited on the insulating film 14, and then polycrystalline silicon is deposited using a patterned resist as a mask to form an electrode layer 15i as shown in FIG. In order to fill the trench by depositing polycrystalline silicon once, the thickness of the polycrystalline silicon needs to be larger than half the trench width. Further, polycrystalline silicon VC needs to be doped with impurities. For example, methods for doping phosphorus as an impurity include (r) cooling phosphorus when depositing polycrystalline silicon to form phosphorus-doped polycrystalline silicon; There is a method (7) of adding impurities by vapor phase diffusion of phosphorus or ion implantation of phosphorus after depositing polycrystalline silicon without using silane or phosphine. CV of ~800℃
Lindorf polycrystalline silicon r is deposited using the D method. Also,
(In Loff's method, the heat temperature for the shiran sound is 600 to 800.
℃ocVDff: After 7y of polycrystalline silicon deposition at 800-1100℃ in a poczs atmosphere.
A heat treatment session is carried out, and a phosphorus diffusion process is carried out. In the case of ion implantation, the acceleration voltage is 80 to 120 KeV, the implantation amount is 1
All ion implantation was carried out under the conditions of 0''~1016cm-'', and the sound material was heat-treated at 800~1000℃ in a nitrogen atmosphere.
Increases the conductivity of polycrystalline silicon.

In both cases of (a) and (b) above, impurity-cooled polycrystalline silicon is used as a resist tf mask, for example, CCt
Etch with tFx plasma to form electrodes 15 as described above.

Next, as shown in FIG. 7, 16 contact holes are formed in the insulating film 14 by a normal etching process, and a contact electrode 17i to the n-type layer is formed.

(8) Through the above steps, a capacitor consisting of the L9n type layer 13, the insulating film 14 and the capacitor electrode 15 is completed.

(Embodiment 2) A method of applying the present invention to an MO8 type dynamic memory cell using a p-type silicon substrate will be described.

In FIG. 8, silicon oxide tH222 is formed in a 1111vI4 area 21 corresponding to the amount of elements provided on a p-type silicon substrate 1, and then a cell capacitor oxide area 25 is formed on a patterned resist 24 coating mask on a pad silicon oxide film 23. This is a cross-sectional view of an n-type layer 26 formed by implanting n-type impurities, such as ions of phosphorus or phosphorus.

Next, after removing the resist, a silicon nitride film 279 and a silicon oxide film 28 are formed as a core layer in this order by the CVD method, and then the resist 2'Q is patterned in a box shape in the ninth field.
- Etch the mask using the above silicon oxide #28 ony silicon nitride film 27 x CF'a and 7c RIE using hydrogen.

Here, the silicon nitride film 27 is formed in the following steps as indicated by rl,
This is to avoid etching of the surface of the silicon oxide gland 22 during the over-etching of the silicon oxide film 2B.

In the next VC1 example 1, a silicon oxide film 2 is applied to the comb trap 9.
For example, if a silicon substrate 1iRIEVC process 9 is inserted into the 82 mask and shown in Figure 1θ, the width is 0.5 μm and the depth is 1.5 μm. r Shadow formation.

Next, as shown in FIG. 11, an n-type layer 30 is formed by depositing Lindorff silicon oxide@12 and heat treating as shown in FIG.

Here, υ-shaped bz is formed by ion implantation as shown in FIG.
The n-type layer 26r was formed by phosphorus diffusion from the phosphorus silicon branch film and was integrated with the n-type layer, forming an n-type layer (material) in the mold region of the cell cabbage containing the groove.

Next, the Lindorff silicon oxide film 12. Remove silicon nitride gland 27↓ and Yohibad silicon oxide film 23, trap 5
, As shown in Example 1, the cell capacitor coating 1
For example, as shown in FIG. 12, 15 cell plate electrodes are formed using polycrystalline silicon having a thickness of 6150 λV and further bonded to V<-s.

Next, the insulating film 14 that is not covered with the cell plate electrode is
After removing it with a buffer solution, 31 oxide films are formed on the silicon substrate by thermal oxidation, and as shown in Figure 13, 32 oxide films are formed, and an n-type layer for the source and drain is formed. Form 33 pieces.

In forming the silicon oxide film, polycrystalline silicon is also oxidized at the same time, so that a silicon oxide film 34 is formed. As the gate electrode serving as the word line, polycrystalline silicon doped with phosphorus, arsenic, or boron, or a high melting point metal such as molybdenum or tantalum can be used. The n-type layer for the source Jakuyohi train has arsenic ion acceleration pressure of 80 ~
100Key, implantation amount 10" ~ 5 x 10"
Ion implantation can be done when rice is grown at cm-2. Even if ion implantation of phosphorous is performed instead of arsenic, δ cannot be maintained.

Next, as an example of an interlayer loquat film audience, what about a phosphorus-doped silicon oxide film? As shown in FIG. 14, a contact hole 36 is formed on the n-type layer to make contact with a wiring electrode 37 that will become a bit line.

As described above, a memory cell consisting of a pH-transistor structure is completed, and FIG. 15 shows a half-view of the completed memory cell. A Takamori IC groove is formed. Fig. 14 shows the cutting recess of AA'. In Example 2, μ is 9 in Selchabashita! : One trap is formed in the city, or the range T that enters the south area of the cell capacitor: Defective groove lπμ shape can be changed. As an example, the three members of Yang Zeng Ai Yohi Kiyone) were sent out, 'tj rl, Figure 16.
Badly lost.

(Effects of the Invention) As explained above, the VC and fL of the present invention utilizes all the grooves to form a tray-shaped capacitor, and the conductivity type of the silicon substrate is By providing different conductive layers, the capacitor capacitance can be increased, and the capacitor insulating film can be formed without applying a voltage to the capacitor electrode. For example, in the canopy capacitor of the second embodiment described above, a capacitor capacity approximately twice as large as that of a conventional capacitor without a groove formed with the same width can be realized. Note that this capacitance can be increased as the depth of the groove increases. In addition, since the voltage application is unsatisfactory, the capacitor insulating film may be damaged. Can be effectively dodged. For seven reasons, if memory cells are formed using undeveloped technology, the integration density will be one step ahead*! 7. K can improve pregnancy.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional memory cell, FIGS. 2 to 7 are cross-sectional views of the steps shown in Example 1, and FIGS. 8 to 14 are cross-sectional views of the steps shown in Example f'l12. Figure, No. 15
17A to 17D show plan views of memory cells. ■・・・・・・・・・・・・P-type silicon substrate,
2...Insulating film 3...
・・・・・・・・・Cell plate electrode 4.5・・・・
...Source, drain n-type j so6...
・・・・・・・・・Gate insulating film, 7・・・・・・・・・
・・・・・・Gate electrode 8・・・・・・・・・・・・・・・
・・Inversion layer 9・・・・・・・・・・・Etsunung mask 10・・・・・・・・・・・・・Resist 1
１・・・・・・・・・・・・Groove 12・・・・・・
......Rintono silicon oxide film 13...
・・・・・・・・・・・・N-type layer 14・・・・・・・
......Zettai k1. Membrane 15・・・・・・・・・
・・・・・・Kamegashiso 16・・・・・・・・・・・・・・・
・Contact hole 17...Contact'..., hood 21......
Cumulative dirt floor separation chain acid 22......Silicon oxide film 23...Bat silicon [E[24...]・・・・・・・・・・・・
Resist 25... Cell capacitor region 26... N-type layer 27... ...Silicon nitride film 2
8・・・・・・・・・・・・・・・ Silicon oxide film 29
・・・・・・・・・・・・Resist 30 ・・・
・・・・・・・・・・・・ N type 7 so 31・・・・・・
......Kate oxide film 32...
......Gate electrode 33...
...N-type layer 34...Silicon oxide film 35...Interlayer insulating film 36...・・・・・・・・・・・・Contact hole 37・・・・・・・・・・・・・・・Wiring electrode patent applicant Nippon Telegraph and Telecommunications Corporation Figure 10 Figure 14 Figure 16 Line 17Wi

Claims (1)

[Claims] (The inner surface of the groove formed on the main surface of the semiconductor substrate of υ conductivity type is different from the conductivity type of the semiconductor substrate!L, 7Dλ). A semiconductor integrated circuit device characterized in that a capacitor is provided in which a capacitor is formed on the same side. (2) fft determination of the main surface of a conductive type semiconductor substrate. A step of forming a conductive layer on the inner surface of the groove, a step of forming a conductive layer having a conductivity type different from that of the semiconductor substrate, and laminating the two-layer VC insulating film and electrode layer in this order. A method of manufacturing a semiconductor integrated circuit device characterized by a process of forming a capacitor and a process of forming a capacitor.