JPS6197975A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6197975A
JPS6197975A JP59219673A JP21967384A JPS6197975A JP S6197975 A JPS6197975 A JP S6197975A JP 59219673 A JP59219673 A JP 59219673A JP 21967384 A JP21967384 A JP 21967384A JP S6197975 A JPS6197975 A JP S6197975A
Authority
JP
Japan
Prior art keywords
molybdenum
film
melting point
films
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59219673A
Other languages
Japanese (ja)
Inventor
Kenichi Kurihara
健一 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP59219673A priority Critical patent/JPS6197975A/en
Publication of JPS6197975A publication Critical patent/JPS6197975A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To prevent high-melting point films from being diffused in the gate insulating films and to contrive to improve the gate withstand voltage by a method wherein, after a high-melting point metal film is deposited on the whole surface of the substrate using the gate electrode as the high-melting point metal silicide film, the high-melting point metal films on the side walls of the gate electrode are removed. CONSTITUTION:A gate oxide film 28 is formed, and after that, oxygen ions are implanted in the whole surface of the substrate. Subsequently, a heat treatment is performed in an atmosphere of oxygen, a molybdenum silicide film 29 is formed and an oxide film 30 is formed on the periphery thereof. After this, phosphorus ions are implanted through the silicon oxide film 30, and a source 31 and a drain 32 are formed. Subsequently, an oxide film 33 is made to remain on the sidewalls only of the molybdenum silicide pattern 29 using an anisotropic etching method. Then, a molybdenum film 34 is deposited on the whole surface. Then, unreacted molybdenum films on the sidewalls of the molybdenum silicide pattern and those on field oxide films 22 are removed using a reactive ion etching method, and molybdenum silicide patterns 35 and molybdenum silicide films 36 are respectively separated.

Description

【発明の詳細な説明】 21b列技1じと訪 本発明は、半導体の製造方法に関し、特に高融点金属の
硅化物からなる電極を備えた半導体装置の製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor, and more particularly to a method of manufacturing a semiconductor device having an electrode made of silicide, a high melting point metal.

従来技術 MO8半導体装置においては、ゲート電極及びソース、
ドレイン領域の低抵抗化をはかるため、高融点金属硅化
物が使用されるようになってきている。この場合、ゲー
ト電極の特性を保持するためにモリブデンシリサイド層
の下地として多結晶シリコンを敷き、モリブデンシリサ
イド層−多結晶シリコンの2M構造で、ゲート電極を形
成しているが、熱処暑時にモリブデンシリサイド中のモ
リブデンが多結晶シリコン層中を突き抜けて、ゲート酸
化膜にまで拡散してしまい、これによってゲート耐圧の
劣化を招く欠点がある。
In a conventional MO8 semiconductor device, a gate electrode and a source,
In order to lower the resistance of the drain region, high-melting point metal silicides have come to be used. In this case, in order to maintain the characteristics of the gate electrode, polycrystalline silicon is laid down as the base of the molybdenum silicide layer, and the gate electrode is formed with a 2M structure of molybdenum silicide layer and polycrystalline silicon. The molybdenum inside penetrates through the polycrystalline silicon layer and diffuses into the gate oxide film, which has the disadvantage of causing deterioration of gate breakdown voltage.

目   的 本発明の目的は、ゲート絶縁膜への金属の拡散を防止し
てゲート耐圧を向上させることができ、しかも簡単なプ
ロセスで高融点金属をソース、ドレイン電極とゲート電
極に備えたLDD構造の半導体装置の製造方法を提供す
ることにある。
Purpose An object of the present invention is to provide an LDD structure that can prevent diffusion of metal into the gate insulating film and improve the gate withstand voltage, and in which the source, drain electrode, and gate electrode are provided with a high-melting point metal using a simple process. An object of the present invention is to provide a method for manufacturing a semiconductor device.

構成 以下1本発明の一実施例であるMO8型半導体装置を第
1図(a)〜(h)を参照して説明する。
Structure An MO8 type semiconductor device which is an embodiment of the present invention will be described below with reference to FIGS. 1(a) to 1(h).

まず、P型シリコン基板21の表面に選択酸化法により
フィールド酸化膜22を形成した後、このフィールド酸
化膜22によって囲まれた素子領域表面に厚さ400人
の熱酸化膜23を形成した。
First, a field oxide film 22 was formed on the surface of a P-type silicon substrate 21 by selective oxidation, and then a thermal oxide film 23 with a thickness of 400 mm was formed on the surface of the element region surrounded by this field oxide film 22.

次に厚さ3000人の多結晶シリコン膜24を堆積し、
更に多結晶シリコン膜24上にスパッタ法により厚さ2
000人のモリブデン膜25を堆積した(第1図a)。
Next, a polycrystalline silicon film 24 with a thickness of 3000 μm is deposited.
Furthermore, a layer with a thickness of 2 is deposited on the polycrystalline silicon film 24 by sputtering.
1,000 molybdenum films 25 were deposited (FIG. 1a).

次いで、図示しないホトレジストパターンをマスクとし
て、これらモリブデン膜25.及び多結晶シリコン膜2
4を反応性イオンエツチングによりモリブデン膜パター
ン26、及び多結晶シリコンパターン27を形成した。
Next, using a photoresist pattern (not shown) as a mask, these molybdenum films 25. and polycrystalline silicon film 2
4 was subjected to reactive ion etching to form a molybdenum film pattern 26 and a polycrystalline silicon pattern 27.

続いて、これらパターンをマスクとしてHFを含むNH
4F溶液を用いて前記熱酸化膜23をエツチングしてゲ
ート酸化膜28を形成した(第1回目)。
Next, using these patterns as a mask, NH containing HF is
The thermal oxide film 23 was etched using a 4F solution to form a gate oxide film 28 (first time).

この後、基板全面に酸素イオンを30 K e V 1
0”CXl注入した。第1回目では、酸素イオンは、フ
ィールド領域上、ソース、ドレイン領域上に注入され、
並びにモリブデン膜25上から、多結晶シリコン膜24
中に注入されるように注入した。
After this, oxygen ions were applied to the entire surface of the substrate at 30 K e V 1.
0"CXl implant. In the first round, oxygen ions were implanted over the field region, source and drain regions,
Also, from above the molybdenum film 25, the polycrystalline silicon film 24
It was injected so that it was injected inside.

この場合、酸素イオンの注入量のドーズ量のピークは、
多結晶シリコンとモリブデンの界面付近にあるように注
入する。なお、多結晶シリコン中の酸素は、全体に亘っ
て一様に酸素を含有することが好ましい。次の、第2回
目では、酸素イオンは。
In this case, the peak dose of oxygen ion implantation is
Inject near the interface between polycrystalline silicon and molybdenum. Note that it is preferable that the polycrystalline silicon contains oxygen uniformly throughout. Next, in the second time, oxygen ions.

モリブデン膜及び多結晶シリコン膜の側壁のみ注入した
。また、酸素イオンは基板全面とゲート電極側壁に同時
に注入してもよい、(第1図C)続いて、800℃の酸
素雰囲気中で熱処理を行い、モリブデンと多結晶シリコ
ンとを反応させてモリブデンシリサイド29を形成させ
た。この熱処理によって、ソース、ドレイン領域上及び
モリブデンシリサイドの周辺に酸化膜30を形成した。
Only the side walls of the molybdenum film and polycrystalline silicon film were implanted. In addition, oxygen ions may be implanted into the entire surface of the substrate and the side walls of the gate electrode at the same time (Fig. 1C). Subsequently, heat treatment is performed in an oxygen atmosphere at 800°C to cause the molybdenum and polycrystalline silicon to react, thereby forming molybdenum. Silicide 29 was formed. Through this heat treatment, an oxide film 30 was formed on the source and drain regions and around the molybdenum silicide.

この後、このモリブデンシリサイド膜29をマスクとじ
て、リンをドーズ量lX101LEI!、加速エネルギ
ー25 K e Vでソース、ドレイン領域の基板内へ
酸化シリコン膜30を通して注入し、ソース31、ドレ
イン32を形成した(第1図d)。
After that, this molybdenum silicide film 29 is used as a mask, and phosphorus is applied at a dose of lX101LEI! , an acceleration energy of 25 K e V was implanted into the substrate in the source and drain regions through the silicon oxide film 30 to form a source 31 and a drain 32 (FIG. 1d).

続いて、異方性エツチングを用いてソース、ドレイン上
、及びモリブデンシリサイドの上面をエツチングして表
面を露出させると共に、モリブデンシリサイドパターン
の側壁にのみ酸化膜33を残存させた(第1図e)。
Next, using anisotropic etching, the top surface of the source and drain and the top surface of the molybdenum silicide were etched to expose the surface, and the oxide film 33 was left only on the sidewalls of the molybdenum silicide pattern (Fig. 1e). .

次いで、全面に厚さ500人のモリブデン膜3・1を堆
積した。このモリブデン膜34のパターンをマスクとし
て、前記ソース、ドレイン領域に砒素をドーズ量5 X
 10”cxl、加速!ネルギー60KeVで注入した
。続いて、600℃の窒素雰囲気中で30分間熱処理を
行い、モリブデンと単結晶シリコンとの間、及びモリブ
デンとモリブデンシリサイドとの間に反応を行わせて、
ソース、ドレイン領域31.32表面にソース、ドレイ
ン電極となるモリブデンシリサイドを、またモリブデン
シリサイド29上にモリブデン含有量の高いモリブデン
シリサイド膜を夫々形成した(第1図f)。
Next, a molybdenum film 3.1 with a thickness of 500 mm was deposited on the entire surface. Using the pattern of this molybdenum film 34 as a mask, arsenic was applied to the source and drain regions at a dose of 5X.
The implantation was carried out at 10"cxl and an acceleration energy of 60KeV. Subsequently, heat treatment was performed for 30 minutes in a nitrogen atmosphere at 600°C to cause reactions between molybdenum and single crystal silicon and between molybdenum and molybdenum silicide. hand,
Molybdenum silicide to serve as source and drain electrodes was formed on the surfaces of the source and drain regions 31 and 32, and a molybdenum silicide film with a high molybdenum content was formed on the molybdenum silicide 29 (FIG. 1f).

次に、反応性イオンエツチングを用いてモリブデンシリ
サイドの側壁、及びフィールド酸化膜22上の未反応の
モリブデン膜を除去して、前記モリブデンシリサイドパ
ターン35とモリブデンシリサイド36とを分離した(
第1図g)。
Next, the side walls of the molybdenum silicide and the unreacted molybdenum film on the field oxide film 22 were removed using reactive ion etching to separate the molybdenum silicide pattern 35 and the molybdenum silicide 36 (
Figure 1g).

続いて、全面にCVD酸化膜37を堆積した後、コンタ
クトホール38を開孔し、更に全面にAJ膜を蒸着した
後、パターニングしてA1配線39を形成し、MO3型
半導体装置を作成した。
Subsequently, a CVD oxide film 37 was deposited on the entire surface, a contact hole 38 was opened, and an AJ film was further deposited on the entire surface, followed by patterning to form an A1 wiring 39, thereby producing an MO3 type semiconductor device.

以上説明した実施例において、モリブデンシリサイドの
代りにタングステン、チタン、タンタルなどの高融点金
属、あるいはそのシリサイドにも適用できる。
In the embodiments described above, high melting point metals such as tungsten, titanium, tantalum, etc., or their silicides can be used instead of molybdenum silicide.

また、多結晶シリコンの抵抗値を下げるため、リンを酸
素イオン注入時の前、又は後であるいは予めドープさせ
ておいてもよい。
Further, in order to lower the resistance value of polycrystalline silicon, phosphorus may be doped before or after oxygen ion implantation, or in advance.

効果 第2図fの工程で堆積するモリブデンシリサイド上部は
、モリブデン含有量が高いが、多結晶シリコン、及びモ
リブデン膜中に予め酸素イオンが注入されており、しか
も、酸素含有量の分布は、多結晶シリコンとモリブデン
との界面を中心に広がっているため、高いモリブデン含
有量であってもゲート酸化膜中にモリブデン金属が入る
のを防止できると共に、モリブデンシリサイドの側壁に
酸化膜が形成されやすく、ゲート電極とソース、ドレイ
ン電極との分離が容易にでき、しかもその後の熱処理で
側壁の酸化膜厚をより厚くできるので、より有効なLD
D構造を形成できる。さらに、酸素イオン注入工程でソ
ース、ドレイン上に酸化膜が形成されるため、これを利
用してソース、ドレイン用に不純物を注入できる。しか
も、これら効果を同一工程で得ることができる。
Effect The upper part of the molybdenum silicide deposited in the step shown in Figure 2 f has a high molybdenum content, but oxygen ions have been implanted into the polycrystalline silicon and molybdenum film in advance, and the distribution of oxygen content is Since it spreads around the interface between crystalline silicon and molybdenum, it can prevent molybdenum metal from entering the gate oxide film even if the molybdenum content is high, and it also prevents the formation of an oxide film on the sidewalls of molybdenum silicide. The gate electrode can be easily separated from the source and drain electrodes, and the thickness of the oxide film on the sidewalls can be made thicker through subsequent heat treatment, making the LD more effective.
A D structure can be formed. Furthermore, since an oxide film is formed on the source and drain in the oxygen ion implantation process, impurities can be implanted for the source and drain using this. Moreover, these effects can be obtained in the same process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(h)は、本発明の一実施例における高
融点金属シリサイドを用いたMO3型半導体装置の製造
方法を示す断面図である。 21一基板 24−多結晶シリコン膜 25.34−モリブテン膜 29−モリブデンシリサイドゲート電極3o−酸化膜 31.32−ソース、トレイン
FIGS. 1(a) to 1(h) are cross-sectional views showing a method of manufacturing an MO3 type semiconductor device using refractory metal silicide in one embodiment of the present invention. 21 - Substrate 24 - Polycrystalline silicon film 25. 34 - Molybdenum film 29 - Molybdenum silicide gate electrode 3o - Oxide film 31. 32 - Source, train

Claims (3)

【特許請求の範囲】[Claims] (1)多結晶シリコン膜と高融点金属との積層構造によ
ってゲート電極を形成し、該ゲート電極全面に酸素イオ
ンを注入した後、熱処理してゲート電極を高融点金属の
シリサイドとし、その後、基板全面に高融点金属を堆積
した後、該ゲート電極の側壁の高融点金属を除去したこ
とを特徴とする半導体装置の製造方法。
(1) A gate electrode is formed with a laminated structure of a polycrystalline silicon film and a high melting point metal, oxygen ions are implanted into the entire surface of the gate electrode, the gate electrode is made into a high melting point metal silicide by heat treatment, and then the substrate is 1. A method of manufacturing a semiconductor device, characterized in that after depositing a high melting point metal on the entire surface, the high melting point metal on the side walls of the gate electrode is removed.
(2)前記酸素イオン注入は、多結晶シリコン膜と高融
点金属との界面にそのドーズ量のピークがくるようにし
たことを特徴とする、特許請求の範囲第1項記載の半導
体装置の製造方法。
(2) Manufacture of the semiconductor device according to claim 1, wherein the oxygen ion implantation is performed so that the peak dose thereof is at the interface between the polycrystalline silicon film and the high melting point metal. Method.
(3)前記酸素イオン注入は、少なくとも2回行ない、
そのうちの少なくとも1回は、ゲート電極の側壁に行な
うことを特徴とする、特許請求の範囲第1項記載の半導
体装置の製造方法。
(3) the oxygen ion implantation is performed at least twice;
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the steps is performed on a side wall of a gate electrode.
JP59219673A 1984-10-19 1984-10-19 Manufacture of semiconductor device Pending JPS6197975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59219673A JPS6197975A (en) 1984-10-19 1984-10-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59219673A JPS6197975A (en) 1984-10-19 1984-10-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6197975A true JPS6197975A (en) 1986-05-16

Family

ID=16739179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59219673A Pending JPS6197975A (en) 1984-10-19 1984-10-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6197975A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US11001705B2 (en) 2015-12-25 2021-05-11 Toyobo Co., Ltd. Polyester resin composition, light-reflector component containing same, light reflector, and method for producing polyester resin composition
US11001706B2 (en) 2017-02-02 2021-05-11 Toyobo Co., Ltd. Polyester resin composition, and light reflector component and light reflector including polyester resin composition
US11713392B2 (en) 2017-02-02 2023-08-01 Toyobo Co., Ltd. Polyester resin composition, and light reflector component and light reflector including polyester resin composition

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
US11001705B2 (en) 2015-12-25 2021-05-11 Toyobo Co., Ltd. Polyester resin composition, light-reflector component containing same, light reflector, and method for producing polyester resin composition
US11001706B2 (en) 2017-02-02 2021-05-11 Toyobo Co., Ltd. Polyester resin composition, and light reflector component and light reflector including polyester resin composition
US11713392B2 (en) 2017-02-02 2023-08-01 Toyobo Co., Ltd. Polyester resin composition, and light reflector component and light reflector including polyester resin composition

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