JPS6276773A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the characteristics of a formed ROM by selectively removing an insulating film coated with a gate electrode before leading electrodes from source and drain, an implanting impurity ions to a channel region through the exposed gate, thereby shortening the steps after the ROM pattern is modified. CONSTITUTION:An oxide film 22 is formed on an Si substrate 21, a nitride film 23 is patterned, with the film as a mask an impurity 24 is ionized. With the film 23 as a mask an oxide film 25 is formed, the film 23 is removed, channel impurity 26 is implanted to a channel region forming region, a polycrystalline Si film 27 is formed, etched in a predetermined shape to form a gate electrode, with the electrode as a mask source drain region 28 is formed. The entire surface is coated with a protective film 29, and heat treated. A mask 30 is formed, an impurity 31 is ion implanted through the films 27, 22, the film 29 is formed, and impurity ions 31 are activated. A hole 33 is formed in the contact leading portion of the film 29, a covered with a metal layer 31, patterned to form metal wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for manufacturing a MO3O3 cubic conductor memory device using a polycrystalline silicon gate.

[Technical day before the invention and its problems] In the MO8 type semiconductor device, the read-only method (
When manufacturing a mask ROM (mask ROM), storage information is provided by implanting impurities into the channel region of a preselected MOS transistor.

FIG. 4 shows cross-sectional views of the cables for each process to explain the manufacturing process Δ when manufacturing a MOS transistor for ROM using a conventional manufacturing method.

First, using a silicon substrate 11 as shown in FIG. 4(a), an active region surrounded by a field oxide film 12 is formed on the surface of the silicon Y and L plates using a well-known manufacturing technique.
In this active region, a gate oxide film 13, a polycrystalline silicon gate electrode 14, and a source/drain impurity diffusion layer 15 are provided.
form.

Next, as shown in FIG. 4(b), a mask 16 for ROM ion implantation is formed so that only the gate region is exposed, and impurities are implanted through the polycrystalline silicon gate electrode 14 and gate oxide film 13 by ion implantation. The ions are introduced into the channel region to form an ion implantation layer 17.

Thereafter, as shown in FIG. 4(C), the surface of the silicon substrate 11 is covered with an insulating film 18 such as an oxide film, and a heat treatment process is performed.

Then, as shown in FIG. 4(d), a process for taking out the electrodes from the source/drain impurity diffusion layer 15 is performed to complete wiring using metal Ff 120 such as aluminum.

It is convenient for the design that the storage information of ROM is determined as late as possible in the process, but in this manufacturing method, as shown in Fig. 4 (
Since the ion implantation process shown in b) is relatively long, it takes a long time to change the ROM ion mask 16 and obtain a semiconductor device with the ROM pattern desired by the user. There are drawbacks.

In order to overcome this drawback, there is a method in which a mask process for ROM ion implantation is performed after an electrode extraction process.

FIG. 5 is a cross-sectional view of an element for explaining an example of such a conventional manufacturing method. In the case of this method, Figure 4 (
After wiring with the metal layer 20 for taking out the electrodes as shown in d), one mask after ROM ion implantation is formed in the same manner as in FIG. 4(b) so that the gate region is exposed.
Insulating film 1 covering polycrystalline silicon gate electrode 14
8 and remove it, and then remove the gate electrode 14.
Then, impurity ions are implanted into the channel region 17 through the gate oxide film 13.

However, when using this manufacturing method, the metal RV
Since the ion implantation for ROM formation is performed after the formation of the metal layer 20, the annealing temperature cannot be raised to a temperature higher than the melting point of the metal layer 20 in the so-called annealing step after the ion implantation, and sufficient heat treatment cannot be performed. Have difficulty. Therefore, there is a problem that the electrical activation of the implanted impurity is insufficient, resulting in deterioration of the characteristics of the formed ROMf7).

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device in which the steps after changing the ROM backbone are short and the ROM formed has good characteristics.

[Summary of the invention]

To achieve the above object, according to the present invention, a method for manufacturing a semiconductor device includes a step of ion-implanting impurities into a densitane region that exists between a source and a drain and is controlled by a gate electrode made of polycrystalline silicon. , a step of selectively removing the insulating film covering the gate electrode to expose the gate before the step of taking out the electrodes from the source/drain, and a step of ionizing impurities into the chi (cinel region) through the exposed goo. It is characterized by comprising a step of injection.

[Embodiments of the Invention] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of an element according to manufacturing steps for explaining an embodiment of the present invention. FIGS. 1(a) to 1(C) show a process of forming using selective oxidation technology.

First, a gate oxide film 11A is formed on the surface of the silicon substrate 21.
22 is formed, an oxidation-resistant film such as a nitride film 23 is patterned and formed in a predetermined region, and impurities 24 are ionized in the element isolation region using the nitride film 23 as a mask.

Then, as shown in FIG. 1(b), selective oxidation is performed using the oxide film 23 as a mask to form a thick oxide film 25 in the element isolation region.
form. After that, the nitride film 23 is removed to form a polystructure as shown in FIG. 1(C).

Next, as shown in FIG. 1(()), a channel impurity 26 is implanted into the region where the DENEL region is to be formed, and then the entire surface is covered with polycrystalline silicon as shown in FIG. 1(e). Formed in 1927.

Next, as shown in FIGS. 1(f) and (q), this polycrystalline silicon film 27 is etched into a predetermined shape to form a gate electrode (east), and a groove 1 formed by this polycrystalline silicon 27 is etched.
~ Using the electrode as a mask, impurities are implanted in a self-aligned manner to form source/drain regions [28].

After that, FJ l! The structure shown in FIG. 1(h) is obtained by applying a predetermined heat treatment.

The protection 'IA 29 is an oxide film or phosphorus silicate glass (BPSG) doped with phosphorus and boron.
and laminates thereof are commonly used. In addition, protective film 2
The source/drain region 28 expands in the depth direction and the lateral direction due to the heat treatment after the deposition of the source/drain region 9 .

Next, as shown in FIG. 1(i), a mask 30 for ROM ion implantation that exposes only the gate region is formed on the surface of the silicon substrate 21 to protect the ROM ion implantation location.
After selectively removing the fJ film 29, impurities 31 for ROM formation are added to the polycrystalline silicon 27 and gate oxide film 22.
Ion implantation is performed through the ion implantation method.

Next, as shown in FIG. 1(j), a protective film 32 is formed on the layers 1 to 1F, and heat treatment 11! ! The impurity 31in introduced into the channel region is activated.

(Later, in order to take out the electrodes from the source/drain region 28, an opening 53 is formed in the contact 1-takeout part of the lρ film 29 using a well-known processing technique, and a metal layer 34 is deposited on the electrode in a predetermined position. Heat the buttering and complete the metal wiring.

As a result, a structure as shown in FIG. 1(k) is obtained by 11J.

If the manufacturing process as explained above is used, the ion implantation process for forming the ROM is after the conventional manufacturing process shown in FIG. 4, so that r< OM? The period from mask production to device completion can be shortened.

Furthermore, since ion implantation for ROM is performed before forming the metal layer for taking out the electrodes, annealing after t1 can be sufficiently performed at a high temperature, and the implanted ions can be sufficiently activated.

FIG. 2 is a plan view of an element according to steps showing another embodiment of the present invention. The same parts as in FIG. 1 are given the same numbers. First, after forming a structure as shown in Figure 1(h),
As shown in FIG. 2(a), the protective film 29 is etched using a mask that selectively removes the contacts for taking out the electrodes and the ion contact area for the ROM at the same time, and the opening shown in the figure is Form 35.

Note that this etching is reactive ion etching (RIE).
). ROM in this state
When ion implantation is performed for ion implantation, as shown in FIG.
is injected.

This impurity 34 is the same as the source/drain diffusion layer 28.
If it is an impurity that provides a-electrometry, the impurity concentration in the contact 1~ portion will be high.

After the implantation of the impurity 34, a heat treatment is performed to activate the implanted impurity, and then an electrode is taken out from the metal layer 3ε3 as shown in FIG. 2(C).
As shown in Figure (d), three protective films are applied to the entire surface to complete the device.

In the case of this embodiment, the ion implantation for ROM and the PEPI culm of contacts 1 to 1 are performed at the same time, which were conventionally performed in two separate steps, so the process is shortened, the manufacturing period is shortened, and the product cost is reduced. It is possible to reduce the

Further, since the concentration of the diffusion layer in the contact portion is increased by the ion implantation, the contact resistance is reduced and device characteristics are improved. Reducing the contact resistance tends to reduce the contact area of the device, and therefore has the advantage that the entire device can be miniaturized.

Furthermore, since the polycrystalline silicon in the gate region is not oxidized after ROM ion implantation is performed, the thickness of the polycrystalline silicon is kept constant. In other words, in conventional manufacturing methods, the ion-implanted layer was oxidized;
There is a drawback that the thickness of polycrystalline silicon decreases due to oxidation, and the resistance of polycrystalline silicon increases, but in the case of this example, the resistance of the 11-product silicon increases. There isn't.

FIG. 3 is a step-by-step sectional view showing still another embodiment.

In the case of this embodiment, as in the case of FIG. 2, ion implantation for ROM is carried out at the same time as the PEP process for a part of contact 1 (step 11).

Thereafter, thermal oxidation is performed in an oxygen atmosphere to activate the implanted impurity ions and simultaneously oxidize the exposed surfaces of silicon a3 and polycrystalline silicon 27, forming oxide films 40 and 41, respectively. This state is shown in Figure 3 (
Shown in a).

Thereafter, the oxide film 40 covering the contact portion is removed to form a contact hole. There is no need to use a special mask when forming the contacts 1 to holes. This is because polycrystalline silicon oxidizes faster than single-crystalline silicon, so the oxide film 4 on polycrystalline silicon 27
1 is formed thicker than the oxide film 40 in the contact 1 to hole portions.

Therefore, even if the oxide film 35 in the contact hole portion is removed, it is possible to leave the oxide film 36 (with a predetermined thickness) on the polycrystalline silicon 27. In this way, as shown in FIG. As shown in b), only the mouth valve is formed between the source/drain regions 28 and the !ζ structure is formed.

Then, as shown in Figure 0!3 (C), a metal layer 33 is deposited on this opening and wiring is carried out to complete the device. In the case of the embodiment shown in FIG.
In addition to the advantages of reducing the number of PEP processes by one and lowering the contact resistance as in the case of the embodiment shown in the figure, the oxide film remains on the gate when the metal film 33 is deposited. There is an advantage that wiring can be provided on the gate.

[Effects of the Invention] As described above in detail based on the embodiments, according to the present invention, the ion implantation process for ROM is performed later than in the conventional manufacturing method, so the manufacturing period after manufacturing the ROM mask is reduced. is shortened.

In addition, since the impurities introduced by ion implantation for ROM can be sufficiently activated by annealing,
A device with good ROM characteristics can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an element according to manufacturing steps for explaining one embodiment of the present invention, and FIGS. 2 and 3 are sectional views of an element according to manufacturing steps for explaining other embodiments of the present invention. Figure 4 J3 and Figure 5 illustrate the conventional manufacturing method.
It is a cross-sectional view of the L section. 21... Silicon substrate, 27... Polycrystalline silicon,
28... Source/drain region, 29... Protective film,
30...Microphone for ion implantation for ROM, 33.38°42...Metal layer. Applicant's representative France 1) --- Male V
\of'
\-No Ward Figure 1 Figure 2 Figure 5

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a step of ion-implanting an impurity into a channel region that exists between a source and a drain and is controlled by a gate electrode made of polycrystalline silicon. The insulating film covering the electrode is
A semiconductor characterized by comprising the steps of selectively removing the gate to expose the gate before the step of taking out the electrode from the drain, and implanting impurity ions into the channel region through the exposed gate. Method of manufacturing the device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing the gate electrode simultaneously exposes the source and drain regions.