JPH0231468A - Manufacture of floating gate type semiconductor memory device - Google Patents
Manufacture of floating gate type semiconductor memory deviceInfo
- Publication number
- JPH0231468A JPH0231468A JP63182203A JP18220388A JPH0231468A JP H0231468 A JPH0231468 A JP H0231468A JP 63182203 A JP63182203 A JP 63182203A JP 18220388 A JP18220388 A JP 18220388A JP H0231468 A JPH0231468 A JP H0231468A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- polycrystalline silicon
- floating gate
- control gate
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007667 floating Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は浮遊ゲート型半導体記憶装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a floating gate type semiconductor memory device.
従来、制御ゲート電極と浮遊ゲート電極を有する不揮発
性半導体記憶装置の製造方法においては、多結晶シリコ
ンで形成された浮遊ゲート電極には電気伝導を良くする
ため高濃度の不純物添加を熱拡散で行なっていた。前記
熱拡散により形成された多結晶シリコン表面のガラス層
を除去した後、高濃度不純物による熱酸化時の増速酸化
を利用し、浮遊ゲート電極と制御ゲート電極との間の絶
縁膜を厚く形成していた。Conventionally, in the manufacturing method of a nonvolatile semiconductor memory device having a control gate electrode and a floating gate electrode, a high concentration of impurity is added to the floating gate electrode formed of polycrystalline silicon by thermal diffusion to improve electrical conduction. was. After removing the glass layer on the surface of the polycrystalline silicon formed by the thermal diffusion, a thick insulating film is formed between the floating gate electrode and the control gate electrode using accelerated oxidation during thermal oxidation using high concentration impurities. Was.
上述した従来の浮遊ゲート型半導体記憶装置の製造方法
では、浮遊ゲート電極を構成する高濃度不純物を添加し
た多結晶シリコンを熱酸化した場合、酸化膜が厚くなり
、浮遊ゲート電極と制御ゲート電極との間の耐圧を高く
できた。しかし動作電圧を低くするために浮遊ゲート電
極と制御ゲート電極との間の酸化膜を薄くしていくと、
高濃度不純物のために浮遊ゲート電極と制御ゲート電極
との間の漏れ電流が増大するという欠点があった。In the conventional manufacturing method of the floating gate type semiconductor memory device described above, when the polycrystalline silicon doped with high concentration of impurities that forms the floating gate electrode is thermally oxidized, the oxide film becomes thick and the floating gate electrode and the control gate electrode are separated. We were able to increase the pressure resistance between the two. However, if the oxide film between the floating gate electrode and the control gate electrode is made thinner in order to lower the operating voltage,
A drawback is that the leakage current between the floating gate electrode and the control gate electrode increases due to the high concentration of impurities.
本発明の浮遊ゲート型半導体記憶装置の製造方法は、半
導体基板上に設けられた浮遊ゲート酸化膜上に多結晶シ
リコン膜を被着する工程と、熱酸化により前記多結晶シ
リコン膜の結晶粒径の肥大化処理を行なう工程と、酸化
膜を除去したのち熱酸化を行なって制御ゲート酸化膜を
形成する工程とを含む手段により前記多結晶シリコン膜
から浮遊ゲート電極を形成するというものである。The method for manufacturing a floating gate type semiconductor memory device of the present invention includes the steps of depositing a polycrystalline silicon film on a floating gate oxide film provided on a semiconductor substrate, and thermally oxidizing the crystal grain size of the polycrystalline silicon film. A floating gate electrode is formed from the polycrystalline silicon film by means including a step of enlarging the polycrystalline silicon film, and a step of removing the oxide film and then performing thermal oxidation to form a control gate oxide film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めに工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、Ｐ型シリコン半導体
基板上にＳ ｉ０２膜（図示せず）とＳｉ３Ｎ４膜（図
示せず）の２層を選択的に形成し、露出した基板表面を
熱酸化して、５ｉ０２からなるフィールド酸化膜２を形
成する０次に、フィールド酸化膜形成のための前述した
Ｓｉ３Ｎ４膜と５ｉ０２膜を除去し、例えば９００℃で
湿式酸化を行ない、厚さ４０ｎｍの浮遊ゲート酸化膜３
を形成する０次に、しきい値電圧制御のためのボロンイ
オンをエネルギー５０ｋｅＶ、ドーズ量６Ｘ １０ ”
ｃｔａ−”で打ち込んだ後、全面に第１の多結晶シリコ
ン膜４を化学気相成長により厚さ２５０ｎｍ堆積させる
０次に、第１の多結晶シリコン膜４を選択的にバターニ
ングすることによって、浮遊ゲート電極形成のための第
１次整形加工を行ない、チャネル部上外の寸法を規定す
る０次に、１１５０℃で乾式酸化を行ない第１の多結晶
シリコン膜４の結晶粒径の肥大化処理を行なう、この熱
酸化により形成された酸化膜を除去した後、９００℃で
湿式酸化を行ない厚さ３５ｎｍの制御ゲート酸化膜５を
第１の多結晶シリコン膜４上に形成する。その後、第１
図（ｂ）に示すように、全面に第２の多結晶シリコン膜
６を化学気相成長により厚さ４００ｎｍ堆積させ、リン
を熱拡散により飽和濃度まで添加し伝導性を良くする。First, as shown in FIG. 1(a), two layers, an Si02 film (not shown) and a Si3N4 film (not shown), are selectively formed on a P-type silicon semiconductor substrate, and the exposed substrate surface is Next, the aforementioned Si3N4 film and 5i02 film for forming the field oxide film are removed, and wet oxidation is performed at, for example, 900° C. to form a field oxide film 2 of 5i02. floating gate oxide film 3
Next, boron ions for threshold voltage control were irradiated with an energy of 50 keV and a dose of 6X 10''.
After implanting with "cta-", a first polycrystalline silicon film 4 is deposited to a thickness of 250 nm on the entire surface by chemical vapor deposition.Next, the first polycrystalline silicon film 4 is selectively buttered. , a first shaping process is performed to form a floating gate electrode, and then a dry oxidation process is performed at 1150°C to increase the crystal grain size of the first polycrystalline silicon film 4. After removing the oxide film formed by this thermal oxidation treatment, wet oxidation is performed at 900° C. to form a control gate oxide film 5 with a thickness of 35 nm on the first polycrystalline silicon film 4. , 1st
As shown in Figure (b), a second polycrystalline silicon film 6 is deposited over the entire surface to a thickness of 400 nm by chemical vapor deposition, and phosphorus is added to the saturation concentration by thermal diffusion to improve conductivity.
第２の多結晶シリコン膜６の上にフォトレジスト膜を塗
布し、パターニングを行ないフォトレジストマスク７を
形成する。次に、第９図（Ｃ）に示すように、反応性イ
オンエツチングにより第２の多結晶シリコン膜６を整形
加工し、制御ゲート電極６′を形成する。続けて反応性
イオンエツチングにより制御ゲート酸化膜５と第１の多
結晶シリコン膜４をエツチングすることにより浮遊ゲー
ト電極の第２次整形加工を行ない、浮遊ゲート電極４′
を制御ゲート電極６′と自己盤−合的に形成する。次に
、フォトレジストマスク７を除去し浮遊ゲート電極４′
の露出した側面部に絶縁膜を形成するために９００℃で
乾式酸化を行ない、厚さ２０ｎｍの側面酸化膜８を形成
し、制御ゲート電極６′をマスクにヒ素イオンをエネル
ギー７０ｋｅＶ、ドーズ量Ｉ Ｘ １０１６ｃｍ−２で
打ち込んだ後、酸素と不活性ガスの混合雰囲気中で１０
００℃、４０分の熱処理を行ない、ｎ＋型のソース領域
９およびドレイン領域１０を形成する。さらに、第１図
（ｄ）に示すように、リンガラスからなる眉間絶縁膜１
１を堆積させ、コンタクト孔１２−１．−１２−２を開
孔した後、制御ゲート電極配線（図示せず）、ソース電
極配線１３およびドレイン電極１４を形成する。A photoresist film is applied on the second polycrystalline silicon film 6 and patterned to form a photoresist mask 7. Next, as shown in FIG. 9C, the second polycrystalline silicon film 6 is shaped by reactive ion etching to form a control gate electrode 6'. Subsequently, the control gate oxide film 5 and the first polycrystalline silicon film 4 are etched by reactive ion etching to perform a second shaping process of the floating gate electrode, thereby forming the floating gate electrode 4'.
The control gate electrode 6' and the control gate electrode 6' are formed in a self-adhesive manner. Next, the photoresist mask 7 is removed and the floating gate electrode 4'
In order to form an insulating film on the exposed side surface of the wafer, dry oxidation is performed at 900° C. to form a side oxide film 8 with a thickness of 20 nm, and arsenic ions are irradiated with an energy of 70 keV and a dose of I using the control gate electrode 6' as a mask. After implantation at 1016 cm-2, 10 cm was implanted in a mixed atmosphere of oxygen and inert gas.
A heat treatment is performed at 00° C. for 40 minutes to form an n+ type source region 9 and drain region 10. Furthermore, as shown in FIG. 1(d), an insulating film 1 between the eyebrows made of phosphorus glass
1 to deposit contact holes 12-1. -12-2 After opening the hole, a control gate electrode wiring (not shown), a source electrode wiring 13, and a drain electrode 14 are formed.
多結晶シリコン膜の結晶粒径の肥大化処理を行なったの
ちに制御ゲート酸化膜を形成するので、制御ゲート酸化
膜形成の熱酸化時に結晶粒径は安定しているので、酸化
シリコン膜の膜質は良好であり、従来例のように厚くす
る必要はない。Since the control gate oxide film is formed after enlarging the crystal grain size of the polycrystalline silicon film, the crystal grain size is stable during thermal oxidation to form the control gate oxide film, so the film quality of the silicon oxide film can be improved. is good, and there is no need to make it as thick as in the conventional example.
第２図は本発明の詳細な説明するための電気的に消去可
能な不揮発性半導体記憶装置の断面図である。FIG. 2 is a sectional view of an electrically erasable nonvolatile semiconductor memory device for explaining the present invention in detail.
フィールド酸化膜２を前述の実施例と同じように形成し
た後、ドレイン領域１０を形成する。次に、浮遊ゲート
酸化膜３を形成した後、トンネル領域を形成するために
選択的に浮遊ゲート酸化膜３をエツチングし、９００℃
の乾式酸化により９層ｍのトンネル酸化膜１−５を形成
する。それ以降は前述の実施例と同様に製造する。After field oxide film 2 is formed in the same manner as in the previous embodiment, drain region 10 is formed. Next, after forming the floating gate oxide film 3, the floating gate oxide film 3 is selectively etched at 900°C to form a tunnel region.
A nine-layer tunnel oxide film 1-5 is formed by dry oxidation. The subsequent steps are manufactured in the same manner as in the previous embodiment.
以上説明したように、本発明は浮遊ゲート電極を多結晶
シリコン膜で形成し、多結晶シリコン膜の粒径を熱酸化
により成長させ、この熱酸化により形成された酸化膜を
除去した後に、浮遊ゲート電極と制御ゲート電極との間
の絶縁膜（制御ゲート酸化膜）を形成することにより、
浮遊ゲート電極と制御ゲート電極との間の絶縁膜の形成
時に浮遊ゲート電極を構成する多結晶シリコン膜の粒径
の成長による絶縁膜質の劣、化を抑えることができ、し
たがって浮遊ゲート電極と制御ゲート電極との間の絶縁
膜を薄くでき、低電圧で動作する浮遊ゲート型半導体記
憶装置を実現できる効果がある。As explained above, the present invention forms a floating gate electrode with a polycrystalline silicon film, grows the grain size of the polycrystalline silicon film by thermal oxidation, and removes the oxide film formed by this thermal oxidation. By forming an insulating film (control gate oxide film) between the gate electrode and the control gate electrode,
When forming the insulating film between the floating gate electrode and the control gate electrode, it is possible to suppress the deterioration or deterioration of the insulating film quality due to the growth of the grain size of the polycrystalline silicon film that constitutes the floating gate electrode. This has the effect of making it possible to thin the insulating film between the gate electrode and realizing a floating gate semiconductor memory device that operates at low voltage.
１・・・Ｐ型シリコン半導体基板、２・・・フィールド
酸化膜、３・・・浮遊ゲート酸化膜、４・・・第１の多
結晶シリコン膜、４′・・・浮遊ゲート電極、５・・・
制御ゲート酸化膜、６・・・第２の多結晶シリコン膜、
６′・・・制御ゲート電極、７・・・フォトレジストマ
スク、８・・・側面酸化膜、９・・・ソース領域、１０
・・・ドレイン領域、１１・・・層間絶縁膜、１２−１
．１２−２．１２−３・・・コンタクト孔、１３・・・
ソース電極配線、１４・・・トレイン電極配線、１５・
・・トンネル酸化膜、１６・・・制御ゲート電極配線。DESCRIPTION OF SYMBOLS 1... P-type silicon semiconductor substrate, 2... Field oxide film, 3... Floating gate oxide film, 4... First polycrystalline silicon film, 4'... Floating gate electrode, 5...・・・
control gate oxide film, 6... second polycrystalline silicon film,
6'... Control gate electrode, 7... Photoresist mask, 8... Side oxide film, 9... Source region, 10
...Drain region, 11...Interlayer insulating film, 12-1
．． 12-2.12-3... contact hole, 13...
Source electrode wiring, 14... Train electrode wiring, 15.
...Tunnel oxide film, 16...Control gate electrode wiring.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めに工程順に示した半導体チップの断面図、第２図は本
発明の詳細な説明するための半導体チップの断面図であ
る。
矛１図
兜 ｊ 図
月 ２ 図FIGS. 1(a) to (d) are cross-sectional views of a semiconductor chip shown in order of steps to explain an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip to explain the present invention in detail. It is. Spear 1 illustration Helmet j Illustration 2
Claims (1)
シリコン膜を被着する工程と、熱酸化により前記多結晶
シリコン膜の結晶粒径の肥大化処理を行なう工程と、酸
化膜を除去したのち熱酸化を行なって制御ゲート酸化膜
を形成する工程とを含む手段により前記多結晶シリコン
膜から浮遊ゲート電極を形成することを特徴とする浮遊
ゲート型半導体記憶装置の製造方法。A step of depositing a polycrystalline silicon film on a floating gate oxide film provided on a semiconductor substrate, a step of enlarging the crystal grain size of the polycrystalline silicon film by thermal oxidation, and a step of removing the oxide film. A method for manufacturing a floating gate type semiconductor memory device, characterized in that a floating gate electrode is formed from the polycrystalline silicon film by means including a step of subsequently performing thermal oxidation to form a control gate oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63182203A JPH0231468A (en) | 1988-07-20 | 1988-07-20 | Manufacture of floating gate type semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63182203A JPH0231468A (en) | 1988-07-20 | 1988-07-20 | Manufacture of floating gate type semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0231468A true JPH0231468A (en) | 1990-02-01 |
Family
ID=16114158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63182203A Pending JPH0231468A (en) | 1988-07-20 | 1988-07-20 | Manufacture of floating gate type semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0231468A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5283973A (en) * | 1991-07-05 | 1994-02-08 | Daiwa Seiko, Inc. | Fishing line guide |
| US5419075A (en) * | 1991-07-05 | 1995-05-30 | Daiwa Seiko, Inc. | Fishing line guide |
| EP0877416A1 (en) * | 1997-05-08 | 1998-11-11 | STMicroelectronics S.r.l. | Integrated structure comprising a polysilicon element with large grain size |
| KR100390913B1 (en) * | 2001-06-28 | 2003-07-12 | 주식회사 하이닉스반도체 | Process for forming gate of flash mamory device |
| JP2006339415A (en) * | 2005-06-02 | 2006-12-14 | Renesas Technology Corp | Method for manufacturing semiconductor device |
-
1988
- 1988-07-20 JP JP63182203A patent/JPH0231468A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5283973A (en) * | 1991-07-05 | 1994-02-08 | Daiwa Seiko, Inc. | Fishing line guide |
| US5419075A (en) * | 1991-07-05 | 1995-05-30 | Daiwa Seiko, Inc. | Fishing line guide |
| EP0877416A1 (en) * | 1997-05-08 | 1998-11-11 | STMicroelectronics S.r.l. | Integrated structure comprising a polysilicon element with large grain size |
| KR100390913B1 (en) * | 2001-06-28 | 2003-07-12 | 주식회사 하이닉스반도체 | Process for forming gate of flash mamory device |
| JP2006339415A (en) * | 2005-06-02 | 2006-12-14 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP4651457B2 (en) * | 2005-06-02 | 2011-03-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
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