JPS5856467A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having large carrier mobility with less crystal defects by improving the steps of forming an amorphous layer due to implantation of silicon to a single crystal semiconductor layer and of recrystallizing the layer. CONSTITUTION:Silicon ions are implanted in the dosage of less than 5X10<15>/cm<2> at a part to be formed with a channel region, and are implanted in the dosage of more than 5X10<15>/cm<2> at parts to be formed with source and drain, thereby selectively crystallizing the amorphous layer of the channel region forming region implanted with Si ions in low dosage in case of heat treating for forming a gate insulating film 6 and forming a channel region 7 having a preferable crystallinity. As a result, the carrier mobility on the surface of the region 7 and the switching speed to the gate electrode 8 can be improved. Arsenic ions are implanted in the amorphous layers 5, 5 of the remaining source and drain forming regions without being recrystallized by the heat treatment, the arsenic is substituted for the Si in case of recrystallization, thereby reducing the activating temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are formed in a single crystal semiconductor layer of an insulating substrate.

In recent years, semiconductor devices on insulating substrates, such as 5OS (Sll
icon on 5apphire) W semiconductor devices are attracting attention because of their high speed and low power consumption. Higher integration of such semiconductor devices means that elements are miniaturized. This miniaturization generally follows the scaling law, and for example, M
OS transistors are no exception. For this reason,
The thickness of the single crystal semiconductor layer that forms the element on the insulating substrate is also
Become thin. Generally, the defect density of a single crystal semiconductor layer epitaxially grown on an insulating substrate changes in the thickness direction of the semiconductor layer, and decreases exponentially as the distance from the interface of the insulating substrate increases. Therefore, if a single crystal semiconductor layer is made thin as described above, and a MOS transistor is fabricated in the semiconductor layer, defects will increase near the surface of the semiconductor layer through which current flows, reducing the carrier mobility and increasing the SO8 ring length. The high speed performance etc. are impaired.

5081MO8) Since transistors have many defects in the single crystal semiconductor layer, they are not suitable for MOS transistors formed on semiconductor substrates. The drain leakage current is higher than that of a transistor.

Furthermore, when heat treatment is performed at high temperature and for a long time at Zorothes, which manufactures MOS transistors on semiconductor layers on insulating substrates, impurity atoms diffuse from the insulating substrates into the semiconductor layers.
These impurity atoms change the impurity content in the semiconductor layer, causing fluctuations and variations in threshold voltage.

The present invention has been made to solve the above problems,
By improving the process of forming an amorphous layer by implanting silicon into a single crystal semiconductor layer on an insulating substrate and the process of recrystallizing the amorphous layer, a single crystal semiconductor layer with few crystal defects and high carrier mobility can be obtained. An object of the present invention is to provide a method for manufacturing a semiconductor device having the following features.

That is, the present invention includes a single crystal semiconductor layer provided on an insulating substrate, source and drain regions provided electrically isolated from each other in this semiconductor layer, and a semiconductor layer between these source and drain regions. In manufacturing a semiconductor device having an f-) electrode provided on a channel region via an insulating film, silicon is applied to at least the channel region of the single crystal semiconductor layer before forming the source, drain/region. The intended portions are doped with a dose of 5 x 1015Δ- or less, and the intended source and drain regions of the semiconductor layer are doped with the same silicon at a dose of more than 5 x 1015/+2 to selectively form an amorphous layer. The characteristic of the dish is to form a .

As an insulating substrate in the present invention, for example, a sapphire substrate, a spinel substrate, a slo, an 8
Examples include a multilayer structure substrate provided with 102 films.

In the present invention, silicon is doped into the intended channel region of the single crystal semiconductor layer at such a rate that an amorphous layer is selectively formed in the thickness direction of the intended channel region. Such an amorphous layer is recrystallized by solid phase growth using the remaining single crystal layer as a seed and converted into a single crystal with good crystallinity and high carrier mobility.

In the present invention, silicon is doped into the portions of the single crystal semiconductor layer where the source and drain are to be formed in order to selectively form an amorphous layer in the thickness direction of the portions where the source and drain are to be formed. After forming such an amorphous layer O, the single crystal silicon layer including the amorphous layer is doped with impurities for forming a source and a drain,
By performing in-phase growth using the remaining single crystal layer as a seed, recrystallization of the amorphous layer and removal of impurities can be achieved. Hexasexualization occurs at the same time. The reason for limiting the silicon dose in the first and second rounds of fIg is that the dose to the area where the channel region is to be formed exceeds 5 x 1r)'7m, and the dose to the area where the source and drain regions are to be formed. Quantity s x 1015
/cII? By doing the following, the amorphous layer in the planned source and drain regions is recrystallized at the same time as the recrystallization of the amorphous layer in the planned channel region, and the amorphous layer is formed in the planned source and drain regions. When recrystallization is performed after doping with impurities for forming sources and drains, the intended channel region also becomes an amorphous layer, so the lateral diffusion of impurities is large (which makes it difficult to control the effective channel length). It is from.

Next, embodiments of the present invention will be described with reference to FIGS. 1 to 6.

Example [pt] 0.3 μm thick on sapphire substrate 1-
A single crystal silicon layer 2 was formed by, for example, an epitaxial growth method, and this silicon layer was selectively etched using a KOH solution to form an island-shaped single crystal silicon layer 2 (as shown in FIG. 1). Next, apply y/ to the entire surface at an acceleration voltage of 190 k@V and a dose of 1 x 1015/, 2
Ion implantation was performed under the following conditions.

At this time, at an acceleration voltage of 190 k@V, the projector range (R,) = 03μ, so the sapphire substrate 1
A first amorphous layer 3 was selectively formed on the single crystal silicon layer 2 near the interface (as shown in FIG. 2).

[ii:1 Next, a resist pattern 4 is selectively formed on the intended channel region of the single crystal silicon layer 20 by photolithography, and then the silicon is accelerated using the cough resist pattern 4 as a mask at a voltage of 170 k@V, )' -1
Amount 1 x 1016/I! l2f) A second amorphous layer 5 was selectively formed in the source and drain portions of the single crystal silicon layer 20 by ion implantation (as shown in Figure 3).
. Subsequently, after removing the resist pattern 4, a thermosetting treatment was performed at a temperature of, for example, 950° C. for 105 minutes.

At this time, on the surface of the island-shaped silicon layer 2? -) An oxide film 6 serving as an insulating film was formed. In addition, this thermal oxidation treatment
The amorphous layer part (channel region) 7 of @1 with a small dose of 1 is recrystallized by in-phase growth using the remaining single crystal layer near the surface as a seed to become a t single crystal layer, while the source and drain are formed. In the second amorphous layer 5 in the planned portion, since the dose of 81 is large, the amorphous or polycrystalline state is maintained (as shown in FIG. 4).

ci*] Next, for example, a phosphorus-doped polycrystalline silicon film is deposited on the entire surface, and this is etched for 7 times using the etching technique.
After turning to form a dirt electrode 8, the oxide film 6 was selectively etched using the dirt electrode 8 as a mask to form a dirt insulating film 9. Next, using the r-to electrode as a mask, an iris impurity, such as arsenic, is applied at an accelerating voltage of 50@V.

)' −, e quantity 5 x 1015/crs? Ion implantation was performed under these conditions to form an arsenic ion implanted layer having a peak concentration distribution in the second amorphous layer 6 of the single crystal silicon layer 2 (as shown in FIG. 5). Continuing, 3 at a temperature of 900℃
Annealing was performed for 0 minutes. At this time, the amorphous layer 5 is recrystallized by solid phase growth using the remaining single crystal layer as a seed,
At the same time as forming a single crystal layer, the implanted arsenic was activated to form 1+ type source and drain regions 10 and 11. He uses CVD as an interlayer insulation film on the entire surface.
8102 film 12 is deposited; contact holes are opened;
Furthermore, a metal film such as At@ is vacuum-deposited on the entire surface, and this is patterned to form the source and drain electrodes 13.
．． According to the method of the present invention, silicon is ion-implanted into the intended channel region at a low dose to form the source, drain, and By implanting ions at a high dose into the intended area, for example, during thermal oxidation treatment for forming a dirt insulating film, the amorphous layer in the intended area of the channel region into which SN ions are implanted at a low dose can be selectively removed. A channel region 7 having good crystallinity can be formed by recrystallization. As a result, the mobility of carriers on the surface of the channel region 1 is improved, the switching speed due to ON and OFF to the dart electrode 8 is improved, and the phenomenon of turning around and turning around near the interface of the sapphire substrate 1 is prevented. I can,
Furthermore, fluctuations and variations in threshold voltage can be improved.

t, the sheath remaining without being recrystallized in the thermal oxidation treatment;
Since arsenic is ion-implanted into the amorphous layers 5, 5 in the portion where the drain is to be formed, arsenic is replaced with si during recrystallization of the amorphous layer 6.6, and as a result, the activation temperature can be lowered. Reducing the activation temperature leads to suppressing the occurrence of defects in the silicon layer.

Further, when arsenic is introduced into the amorphous layers 5, 5, the diffusion rate of the impurity increases, so deep source and drain regions 10 and 11 can be formed even though they are activated at low temperatures. Even impurities with a small diffusion coefficient such as arsenic can reach the sapphire substrate 1 in the source and drain regions 1
0°11 can be formed, the junction capacitance of the source and drain regions can be reduced, and the high speed performance of the SO8 structure can be maintained. Moreover, in this arsenic activation step, the amorphous layer 5
．． 5 is formed only in the region where the source and drain are to be formed, and the channel region 1 is made into a single crystal in the previous heat treatment process.Next, the lateral diffusion of arsenic can be significantly suppressed, and the effective channel length can be controlled. Good and fine MOS
) It becomes possible to form a transistor.

In the above example, the case where a single crystal silicon layer as thin as 0.3 #ffl is used is described.Next, even in the case of a thick single crystal silicon layer, the acceleration voltage of silicon ion implantation is By repeating the process many times with different values, it is possible to obtain crystallinity that is uniform in the thickness direction of the silicon layer and is suitable for each region.

In the above embodiment, silicon ions were implanted into the regions where the source and drain were to be formed, using a resist pattern as a mask. In this case, the ion implantation 81 into the portion where the source and drain are to be formed and the subsequent ion implantation of impurities for forming the source and drain can be performed using a seven-phase line.

The method of the present invention can be applied not only to the production of a negative channel MO8 type conductor device, but also to the production of a P channel MO8 type semiconductor device or a complementary type MO8 type semiconductor device.

As described in detail above, according to the present invention, switching is achieved by improving the process of forming an amorphous layer by implanting silicon into a single crystal semiconductor layer on an insulating substrate and the process of recrystallizing the amorphous layer. High speed, low drain leakage current, good threshold controllability, low junction capacitance in the source and drain regions, and good channel length controllability, high speed, high reliability, and high performance. It has remarkable effects such as being able to manufacture MO8 integrated circuits that can achieve high density.

[Brief explanation of drawings]

1 to 6 are cross-sectional views showing the manufacturing process of an n-channel MO8m semiconductor device in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fire substrate, 2... Island-shaped single crystal silicon layer, 3.6... Amorphous layer, 4-... Resist arm turn, 1... Channel region, 8-...・Gate electrode, 9... r-to insulation, 10... source region, 11
...Drain region, 1 yen, 1 g-At electrode.

Claims (1)

[Claims] A single crystal semiconductor layer provided on an insulating substrate, source and drain regions provided electrically isolated from each other in this semiconductor layer, and a semiconductor layer between these source and drain regions. In manufacturing a semiconductor device having a dirt electrode provided on a channel region with a dirt insulating film interposed therebetween, silicon is applied to a small portion of the single crystal semiconductor layer (both in a portion where the channel region is to be formed) before forming the source and drain regions. 5 x 1
015/cm2 or less, and selectively form an amorphous layer by doping at a dose exceeding s x 1o 15/eJ in the planned source and drain regions of the same silicon-based semiconductor layer. 2. After doping a single-crystal semiconductor layer with silicon, during thermal oxidation treatment for forming a dirt insulating film, a semiconductor device is formed at least in a portion of the semiconductor layer where a channel region is to be formed. The single crystal layer with the remaining amorphous layer is recrystallized by solid-phase growth using the remaining amorphous layer as a seed, and the semiconductor layer is further doped with impurities for forming the source and drain regions, and then silicon is deposited in the areas where the source and drain regions are to be formed. Claim t$1 wherein an amorphous layer formed by doping is recrystallized by solid phase growth using a single crystal layer as a seed, and at the same time the impurities are activated. A method for manufacturing a semiconductor device according to section 1.