JPS5856467A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5856467A
JPS5856467A JP15519281A JP15519281A JPS5856467A JP S5856467 A JPS5856467 A JP S5856467A JP 15519281 A JP15519281 A JP 15519281A JP 15519281 A JP15519281 A JP 15519281A JP S5856467 A JPS5856467 A JP S5856467A
Authority
JP
Japan
Prior art keywords
layer
source
single crystal
semiconductor layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15519281A
Other languages
Japanese (ja)
Inventor
Shinji Taguchi
田口 信治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15519281A priority Critical patent/JPS5856467A/en
Publication of JPS5856467A publication Critical patent/JPS5856467A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

PURPOSE:To obtain a semiconductor device having large carrier mobility with less crystal defects by improving the steps of forming an amorphous layer due to implantation of silicon to a single crystal semiconductor layer and of recrystallizing the layer. CONSTITUTION:Silicon ions are implanted in the dosage of less than 5X10<15>/cm<2> at a part to be formed with a channel region, and are implanted in the dosage of more than 5X10<15>/cm<2> at parts to be formed with source and drain, thereby selectively crystallizing the amorphous layer of the channel region forming region implanted with Si ions in low dosage in case of heat treating for forming a gate insulating film 6 and forming a channel region 7 having a preferable crystallinity. As a result, the carrier mobility on the surface of the region 7 and the switching speed to the gate electrode 8 can be improved. Arsenic ions are implanted in the amorphous layers 5, 5 of the remaining source and drain forming regions without being recrystallized by the heat treatment, the arsenic is substituted for the Si in case of recrystallization, thereby reducing the activating temperature.

Description

【発明の詳細な説明】 本発明は絶縁基板の単結晶半導体層に素子を形成した構
造の半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are formed in a single crystal semiconductor layer of an insulating substrate.

近年、絶縁基板上の半導体装置、例えば5OS(Sll
icon on 5apphire) W半導体装置が
その高速性、低消費電力の点から注目されている。こう
した半導体装置が高集積化されることは、素子が微細化
されることを意味する。この微細化に際しては、スケー
リング則に従がうのが一般的で、絶縁基板上の例えばM
OSトランジスタにおいても例外ではない。このため、
絶縁基板上の素子を形成する単結晶半導体層の厚さも、
薄くなる。一般に、絶縁基板上にエピタキシャル成長さ
せた単結晶半導体層は欠陥密度が該半導体層の厚さ方向
に変化し、絶縁基板の界面から遠ざかるに従って指数関
数的に減少する。従って、上記の如く単結晶半導体層を
薄くすると、該半導体層にMOS )ランジスタを造っ
た場合、電流の流れる半導体層表面付近での欠陥が増加
し、キャリアの移動度が低下しSO8の鳴長である高速
性等が損なわれる。
In recent years, semiconductor devices on insulating substrates, such as 5OS (Sll
icon on 5apphire) W semiconductor devices are attracting attention because of their high speed and low power consumption. Higher integration of such semiconductor devices means that elements are miniaturized. This miniaturization generally follows the scaling law, and for example, M
OS transistors are no exception. For this reason,
The thickness of the single crystal semiconductor layer that forms the element on the insulating substrate is also
Become thin. Generally, the defect density of a single crystal semiconductor layer epitaxially grown on an insulating substrate changes in the thickness direction of the semiconductor layer, and decreases exponentially as the distance from the interface of the insulating substrate increases. Therefore, if a single crystal semiconductor layer is made thin as described above, and a MOS transistor is fabricated in the semiconductor layer, defects will increase near the surface of the semiconductor layer through which current flows, reducing the carrier mobility and increasing the SO8 ring length. The high speed performance etc. are impaired.

ま次、5081MO8)ランジスタは単結晶半導体層中
に欠陥が多く存在してiるため、半導体基板に形成され
るMOS ) ?ンジスタに比べて、ドレインリーク電
流が多くなる。
5081MO8) Since transistors have many defects in the single crystal semiconductor layer, they are not suitable for MOS transistors formed on semiconductor substrates. The drain leakage current is higher than that of a transistor.

更に、絶縁基板上り半導体層にMOS )ランジスタを
製造するゾロセスにお−て、高温、長時間の熱処理を行
なうと、絶縁基板から不純物原子が半導体層に拡散し、
この不純物原子によりて半導体層中の不純物議度が変化
し、閾値電圧の変動、ばらつきの原因となる。
Furthermore, when heat treatment is performed at high temperature and for a long time at Zorothes, which manufactures MOS transistors on semiconductor layers on insulating substrates, impurity atoms diffuse from the insulating substrates into the semiconductor layers.
These impurity atoms change the impurity content in the semiconductor layer, causing fluctuations and variations in threshold voltage.

本発明は上記問題点を解消する丸めになされたもので、
絶縁基板上の単結晶半導体層へのシリコンの注入による
非晶質層の形成工程及び該非晶質層の再結晶化工程を改
良することによって、結晶欠陥が少なくキャリア移動度
の大きい単結晶半導体層を有する半導体装置の製造方法
を提供しようとするものである。
The present invention has been made to solve the above problems,
By improving the process of forming an amorphous layer by implanting silicon into a single crystal semiconductor layer on an insulating substrate and the process of recrystallizing the amorphous layer, a single crystal semiconductor layer with few crystal defects and high carrier mobility can be obtained. An object of the present invention is to provide a method for manufacturing a semiconductor device having the following features.

すなわち、本発明は絶縁基板上に設けられた単結晶半導
体層と、この半導体層に互に電気的に分離して設けられ
たソース、ドレイン領域と、これらソース、yレイン領
域間の半導体層のチャンネル領域上にf−)絶縁膜を介
して設けられたf−)電極とを具備した半導体装置の製
造において、前記ソース、ドレイ/領域の形成前にシリ
コンを前記単結晶半導体層の少なくともチャンネル領域
予定部に5 X 1015Δ−以下のドーズ量でドーピ
ングすると共に、同シリコンを該半導体層のソース、ド
レイン領域予定部に5×1015/+2を越えるドーズ
量でドーピングして選択的に非晶質層を形成することを
肴徴とするものである。
That is, the present invention includes a single crystal semiconductor layer provided on an insulating substrate, source and drain regions provided electrically isolated from each other in this semiconductor layer, and a semiconductor layer between these source and drain regions. In manufacturing a semiconductor device having an f-) electrode provided on a channel region via an insulating film, silicon is applied to at least the channel region of the single crystal semiconductor layer before forming the source, drain/region. The intended portions are doped with a dose of 5 x 1015Δ- or less, and the intended source and drain regions of the semiconductor layer are doped with the same silicon at a dose of more than 5 x 1015/+2 to selectively form an amorphous layer. The characteristic of the dish is to form a .

本発明における絶縁基板として社、例えばサファイア基
板、スピネル基板、slo、根土に半導体層を介して8
102膜を設けた多層構造基板等を挙げることができる
As an insulating substrate in the present invention, for example, a sapphire substrate, a spinel substrate, a slo, an 8
Examples include a multilayer structure substrate provided with 102 films.

本発明において単結晶半導体層のチャンネル領域予定部
へのシリコンのドーピングは、該予定部の厚さ方向に非
晶質層を選択的に形成する尺めである。こうした非晶質
層は残存した単結晶層を種とした固相成長によって再結
晶化され結晶性が良好でキャリア移動度の高−単結晶に
変換される。
In the present invention, silicon is doped into the intended channel region of the single crystal semiconductor layer at such a rate that an amorphous layer is selectively formed in the thickness direction of the intended channel region. Such an amorphous layer is recrystallized by solid phase growth using the remaining single crystal layer as a seed and converted into a single crystal with good crystallinity and high carrier mobility.

本発明において単結晶半導体層のソース、ドレイン形成
予定部へのシリコンのドーピングは、該予定部の厚さ方
向に非晶質層を選択的に形成するためである。こうした
非晶質層O形成後、非晶質層を含む単結晶シリコン層に
ソース、ドレイン形成のための不純物をドーピングし、
残存した単結晶層を種とした同相成長を行なうことによ
りて、非晶質層の再結晶化と不純物の?6性化が同時に
なされる。上記第1回、fIg2回のシリコンのドーズ
量を夫々限定し次理由は、チャンネル領域予定部へのド
ーズ量が5 x 1r)”’7m’を越え、ソース、ド
レイン領域形成予定部へのドーズ量をs X 1015
/cII?  以下にすると、チャンネル領域予定部の
非晶質層の再結晶化と同時にソース、ドレイン領域予定
sの非晶質層も再結晶され、かつソース、ドレイン領域
予定部への非晶質層の形成、ソース、ドレイン形成用不
純−のドーピング後に再結晶化を行なう場合、チャンネ
ル領域予定部も非晶質層となるため、不純物の横方向拡
散も大き(なシ実効チャンネル長のコントロールが困難
となるからである。
In the present invention, silicon is doped into the portions of the single crystal semiconductor layer where the source and drain are to be formed in order to selectively form an amorphous layer in the thickness direction of the portions where the source and drain are to be formed. After forming such an amorphous layer O, the single crystal silicon layer including the amorphous layer is doped with impurities for forming a source and a drain,
By performing in-phase growth using the remaining single crystal layer as a seed, recrystallization of the amorphous layer and removal of impurities can be achieved. Hexasexualization occurs at the same time. The reason for limiting the silicon dose in the first and second rounds of fIg is that the dose to the area where the channel region is to be formed exceeds 5 x 1r)'7m, and the dose to the area where the source and drain regions are to be formed. Quantity s x 1015
/cII? By doing the following, the amorphous layer in the planned source and drain regions is recrystallized at the same time as the recrystallization of the amorphous layer in the planned channel region, and the amorphous layer is formed in the planned source and drain regions. When recrystallization is performed after doping with impurities for forming sources and drains, the intended channel region also becomes an amorphous layer, so the lateral diffusion of impurities is large (which makes it difficult to control the effective channel length). It is from.

次に、本発明の実施例を第1図〜第6因を参照して説明
する。
Next, embodiments of the present invention will be described with reference to FIGS. 1 to 6.

実施例 [p  tず、サファイア基板1−上に厚さ0.3μm
の単結晶シリコン層を例えばエピタキシャル成長法によ
り形成し、このシリコン層をKOH溶液を用いて選択的
にエツチングして島状の単結晶シリコン層2を形成した
(第1図図示)。つづいて、全面にシリ:y/を加速電
圧190 k@V、 ドーズ量1 x 1015/、2
の条件でイオン注入した。
Example [pt] 0.3 μm thick on sapphire substrate 1-
A single crystal silicon layer 2 was formed by, for example, an epitaxial growth method, and this silicon layer was selectively etched using a KOH solution to form an island-shaped single crystal silicon layer 2 (as shown in FIG. 1). Next, apply y/ to the entire surface at an acceleration voltage of 190 k@V and a dose of 1 x 1015/, 2
Ion implantation was performed under the following conditions.

この時、加速電圧190 k@Vではプロジェクテ、ト
レンジ(R,)=03μとなるため、サファイア基板1
界面付近の単結晶シリコン層2に第1の非晶質層3が選
択的に形成された(第2図図示)。
At this time, at an acceleration voltage of 190 k@V, the projector range (R,) = 03μ, so the sapphire substrate 1
A first amorphous layer 3 was selectively formed on the single crystal silicon layer 2 near the interface (as shown in FIG. 2).

[ii:1次いで、単結晶シリコン層20チャンネル領
域予定部上に写真蝕刻法により選択的にレジストパター
ン4を形成した後、咳レジストパターン4をマスクとし
てシリコンを加速電圧170 k@V 、  )’−1
量1 x 1016/I!l2f)lk件でイオン注入
して単結晶シリコン層20ソース、ドレイン形成予定部
に第2の非晶質層5を選択的に形成した(第3図図示)
。つづいて、レジストパターン4を除去した後、熱欧化
処理を例えば950℃の温度下で105分間行なった。
[ii:1 Next, a resist pattern 4 is selectively formed on the intended channel region of the single crystal silicon layer 20 by photolithography, and then the silicon is accelerated using the cough resist pattern 4 as a mask at a voltage of 170 k@V, )' -1
Amount 1 x 1016/I! l2f) A second amorphous layer 5 was selectively formed in the source and drain portions of the single crystal silicon layer 20 by ion implantation (as shown in Figure 3).
. Subsequently, after removing the resist pattern 4, a thermosetting treatment was performed at a temperature of, for example, 950° C. for 105 minutes.

この時、島状のシリコン層2表面に?−)絶縁膜となる
酸化膜6が形成された。また、この熱酸化処理によシS
1のドーズ量の少ない@1の非晶質層部分(チャンネル
領域)7が残存した表面付近の単結晶層を種とした同相
成長によって再結晶化されt単結晶層となり、一方ソー
ス、ドレイン形成予定部の第2の非晶質層5では81の
ドーズ量が多いため非晶質もしくは多結晶の牡態が維持
される(第4図図示)。
At this time, on the surface of the island-shaped silicon layer 2? -) An oxide film 6 serving as an insulating film was formed. In addition, this thermal oxidation treatment
The amorphous layer part (channel region) 7 of @1 with a small dose of 1 is recrystallized by in-phase growth using the remaining single crystal layer near the surface as a seed to become a t single crystal layer, while the source and drain are formed. In the second amorphous layer 5 in the planned portion, since the dose of 81 is large, the amorphous or polycrystalline state is maintained (as shown in FIG. 4).

ci*〕次いで、全面に例えばリンドープ多結晶シリコ
ン膜を堆積し、これを7オトエ、チング技術によシ/f
ターニングしてダート電極8を形成した後、該ダート電
極8をマスクとして酸化膜6を選択工、チングしてダー
ト絶縁膜9を形成した。つづいて、r−ト電極をマスク
として菖聾不純物、例えば砒素を加速電圧50に@V。
ci*] Next, for example, a phosphorus-doped polycrystalline silicon film is deposited on the entire surface, and this is etched for 7 times using the etching technique.
After turning to form a dirt electrode 8, the oxide film 6 was selectively etched using the dirt electrode 8 as a mask to form a dirt insulating film 9. Next, using the r-to electrode as a mask, an iris impurity, such as arsenic, is applied at an accelerating voltage of 50@V.

)’ −、e 量5 x 1015/crs?の条件で
イオン注入して、単結晶シリコン層2の第2の非晶質層
6に濃度分布のピークをもつ砒素イオン注入層を形成し
た(第5図図示)。ひきつづき、900℃の温度下で3
0分間アニールを行なりた。この時、非晶質層5が残存
した単結晶層を種とした固相成長によって再結晶化し、
単結晶層になると同時に、イオン注入された砒素が活性
化され1+型のソース、ドレイン領域10.11が形成
された。その彼、全面に層間絶縁膜としてのCVD −
8102膜12を堆積し、;ンタクトホールを開孔し、
更に全面に金属膜、例えばAt@を真空蒸着し、これを
バターニングしてソース、ドレイン申出しムを電極13
.14を形成して1チャンネルMO8屋半導体装置を製
造した(第6図図示)0 しかして、本発明方法によればシリコンをチャンネル領
域予定部に低ドーズ量でイオン注入し、ソース、ドレイ
/形成予定部に高ドーズ量でイオン注入することによっ
て、例えばダート絶縁膜の形成のための熱酸化処理に際
し、低ドーズ量でSNイオンが注入されたチャンネル領
域予定部の非晶質層が選択的に再結晶化されて良好な結
晶性を有するチャンネル領域7を形成できる。その結果
、チャンネル領域1表面でのキャリアの移動度が改善さ
れ、ダート電極8へのON 、 OFFによるスイ、チ
ンゲスピードが改善され、かつサファイア基板1界面付
近で反転を起こすツク、クチヤンネル現象を防止でき、
更には閾値電圧の変動、ばらつきを改善できる。
)' −, e quantity 5 x 1015/crs? Ion implantation was performed under these conditions to form an arsenic ion implanted layer having a peak concentration distribution in the second amorphous layer 6 of the single crystal silicon layer 2 (as shown in FIG. 5). Continuing, 3 at a temperature of 900℃
Annealing was performed for 0 minutes. At this time, the amorphous layer 5 is recrystallized by solid phase growth using the remaining single crystal layer as a seed,
At the same time as forming a single crystal layer, the implanted arsenic was activated to form 1+ type source and drain regions 10 and 11. He uses CVD as an interlayer insulation film on the entire surface.
8102 film 12 is deposited; contact holes are opened;
Furthermore, a metal film such as At@ is vacuum-deposited on the entire surface, and this is patterned to form the source and drain electrodes 13.
.. According to the method of the present invention, silicon is ion-implanted into the intended channel region at a low dose to form the source, drain, and By implanting ions at a high dose into the intended area, for example, during thermal oxidation treatment for forming a dirt insulating film, the amorphous layer in the intended area of the channel region into which SN ions are implanted at a low dose can be selectively removed. A channel region 7 having good crystallinity can be formed by recrystallization. As a result, the mobility of carriers on the surface of the channel region 1 is improved, the switching speed due to ON and OFF to the dart electrode 8 is improved, and the phenomenon of turning around and turning around near the interface of the sapphire substrate 1 is prevented. I can,
Furthermore, fluctuations and variations in threshold voltage can be improved.

tた、前記熱酸化処理で再結晶されずに残ったシース、
ドレイン形成予定部の非晶質層5,5に砒素をイオン注
入するため、非晶質層6.6の再結晶化に際して砒素が
siと置換され、その結果活性化温度を低下できる。活
性化温度の低減化はシリコン層への欠陥発生の抑制につ
ながる。
t, the sheath remaining without being recrystallized in the thermal oxidation treatment;
Since arsenic is ion-implanted into the amorphous layers 5, 5 in the portion where the drain is to be formed, arsenic is replaced with si during recrystallization of the amorphous layer 6.6, and as a result, the activation temperature can be lowered. Reducing the activation temperature leads to suppressing the occurrence of defects in the silicon layer.

更に、砒素を非晶質層5,5に導入すると、その不純物
の拡散速度が高くなるため、低温で活性したにもかかわ
らず、深いソース、ドレイン領域10.11を形成でき
る。つまシ、砒素のような拡散係数の小さい不純物でも
サファイア基板1にまで達するソース、ドレイン領域1
0゜11を形成でき、ひいてはソース、ドレイン領域の
接合容量を低減でき、SO8構造の高速性を維持できる
。しかも、この砒素の活性化工程において、非晶質層5
.5はソース、ドレイン形成予定部のみに形成され、チ
ャンネル領域1はその前の熱処理工程で単結晶化されて
いる次め、砒素の横方向の拡散を著しく抑制でき、実効
チャンネル長のコントロール性が良好なシ微細なMOS
 )ランジスタの形成が可能となる。
Further, when arsenic is introduced into the amorphous layers 5, 5, the diffusion rate of the impurity increases, so deep source and drain regions 10 and 11 can be formed even though they are activated at low temperatures. Even impurities with a small diffusion coefficient such as arsenic can reach the sapphire substrate 1 in the source and drain regions 1
0°11 can be formed, the junction capacitance of the source and drain regions can be reduced, and the high speed performance of the SO8 structure can be maintained. Moreover, in this arsenic activation step, the amorphous layer 5
.. 5 is formed only in the region where the source and drain are to be formed, and the channel region 1 is made into a single crystal in the previous heat treatment process.Next, the lateral diffusion of arsenic can be significantly suppressed, and the effective channel length can be controlled. Good and fine MOS
) It becomes possible to form a transistor.

なお、上記実施例では0.3#fflと薄い単結晶シリ
コン層を用いた場合について述べ次が、厚イ場合でもチ
ャンネル領域予定部或いはソース、ドレイン形成予定部
に対してシリコンイオノ注入の加速電圧を変えて何度も
行なうことによって、シリコン層の厚さ方向に対して均
一で夫々の領域に合った結晶性にすることが可能である
In the above example, the case where a single crystal silicon layer as thin as 0.3 #ffl is used is described.Next, even in the case of a thick single crystal silicon layer, the acceleration voltage of silicon ion implantation is By repeating the process many times with different values, it is possible to obtain crystallinity that is uniform in the thickness direction of the silicon layer and is suitable for each region.

上記実施例では、ソース、ドレイン形成予定部へのシリ
コンのイオン注入tレジストノターンをマスクとして行
なったが、多結晶シリコン、その他AA、高融点金属硅
化物からなるe−)電極をマスクとして行なってもよい
、この場合、ソース、ドレイン形成予定部への81のイ
オン注入と、その後のソース、ドレイン形成のための不
純物のイオン注入とを七ルファラインで行なうことがで
きる。
In the above embodiment, silicon ions were implanted into the regions where the source and drain were to be formed, using a resist pattern as a mask. In this case, the ion implantation 81 into the portion where the source and drain are to be formed and the subsequent ion implantation of impurities for forming the source and drain can be performed using a seven-phase line.

本発明方法は罵チャンネルMO8型牛導体装置の製造の
みに限らず、PチャンネルMO8型半導体装置や相補型
MO8半導体装置の製造等にも同様に適用できる。
The method of the present invention can be applied not only to the production of a negative channel MO8 type conductor device, but also to the production of a P channel MO8 type semiconductor device or a complementary type MO8 type semiconductor device.

以上詳述した如く、本発明によれば絶縁基板上の単結晶
半導体層へのシリコンの注入による非晶質層の形成工程
、及び該非晶質層の再結晶化工程を改良することによっ
て、スイッチングスピードが高く、ドレインリーク電流
の発生が少なく、かつ閾値の制御性が良好であると共に
ソース、ドレイン領域の接合容量が低く、かつチャンネ
ル長の制御性が良好である高速性、高信頼性、高密度化
を達成し得るMO8屋集積回路を製造できる等顕著な効
果を有する。
As described in detail above, according to the present invention, switching is achieved by improving the process of forming an amorphous layer by implanting silicon into a single crystal semiconductor layer on an insulating substrate and the process of recrystallizing the amorphous layer. High speed, low drain leakage current, good threshold controllability, low junction capacitance in the source and drain regions, and good channel length controllability, high speed, high reliability, and high performance. It has remarkable effects such as being able to manufacture MO8 integrated circuits that can achieve high density.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第6図は本発明の実施例におけるnチャンネル
MO8m半導体装置の製造工程を示す断面図である。 1・・・す、ファイア基板、2・・・島状の単結晶シリ
コン層、3.6・・・非晶質層、4−・・レジストノ臂
ターン、1・・・チャンネル領域、8−・・ゲート電極
、9・・・r−ト絶縁展、10・・・ソース領域、11
・・・ドレイン領域、1謔、1g−At電極。
1 to 6 are cross-sectional views showing the manufacturing process of an n-channel MO8m semiconductor device in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Fire substrate, 2... Island-shaped single crystal silicon layer, 3.6... Amorphous layer, 4-... Resist arm turn, 1... Channel region, 8-...・Gate electrode, 9... r-to insulation, 10... source region, 11
...Drain region, 1 yen, 1 g-At electrode.

Claims (1)

【特許請求の範囲】 絶縁基板上に設けられた単結晶半導体層と、この半導体
層に互に電気的に分離して設けられたソース、ドレイン
領域と、これらソース、ドレイン領域間の半導体層のチ
ャンネル領域上にダート絶縁膜を介して設けられたダー
ト電極とを具備した半導体装置の製造において、前記ソ
ース、ドレイン領域の形成前にシリコンを前記単結晶半
導体層の少な(ともチャンネル領域予定部に5 x 1
015/cm2以下Oドーズ量でドーピングすると共に
、同シリ;ン會骸半導体層のソース、ドレイン領域予定
部にs x 1o 15/eJを越えるドーズ量でドー
ピングして選択的に非晶質層を形成することを特徴とす
る半導体装置の製造方法・ 2、 シリコンを単結晶半導体層にドーピング後、ダー
ト絶縁膜の形成のための熱酸化処理に際して該半導体層
の少なくともチャンネル領域予定部に形成された非晶質
層を残存した単結晶層を種とした固相成長により再結晶
化し、更に前記半導体層にソース、ドレイン領域形成の
ための不純物をドーピングし、ひきつづきソース、ドレ
イン領域予定部へのシリコンのドーピングによシ形成さ
れた非晶質層を単結晶層を種とした固相成長によつて再
結晶化すると同時に前記不純物の活性化を行なうことを
特徴とする特許請求の範囲t$1項記載の半導体装置の
製造方法。
[Claims] A single crystal semiconductor layer provided on an insulating substrate, source and drain regions provided electrically isolated from each other in this semiconductor layer, and a semiconductor layer between these source and drain regions. In manufacturing a semiconductor device having a dirt electrode provided on a channel region with a dirt insulating film interposed therebetween, silicon is applied to a small portion of the single crystal semiconductor layer (both in a portion where the channel region is to be formed) before forming the source and drain regions. 5 x 1
015/cm2 or less, and selectively form an amorphous layer by doping at a dose exceeding s x 1o 15/eJ in the planned source and drain regions of the same silicon-based semiconductor layer. 2. After doping a single-crystal semiconductor layer with silicon, during thermal oxidation treatment for forming a dirt insulating film, a semiconductor device is formed at least in a portion of the semiconductor layer where a channel region is to be formed. The single crystal layer with the remaining amorphous layer is recrystallized by solid-phase growth using the remaining amorphous layer as a seed, and the semiconductor layer is further doped with impurities for forming the source and drain regions, and then silicon is deposited in the areas where the source and drain regions are to be formed. Claim t$1 wherein an amorphous layer formed by doping is recrystallized by solid phase growth using a single crystal layer as a seed, and at the same time the impurities are activated. A method for manufacturing a semiconductor device according to section 1.
JP15519281A 1981-09-30 1981-09-30 Manufacture of semiconductor device Pending JPS5856467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15519281A JPS5856467A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15519281A JPS5856467A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5856467A true JPS5856467A (en) 1983-04-04

Family

ID=15600496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15519281A Pending JPS5856467A (en) 1981-09-30 1981-09-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5856467A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470762A (en) * 1991-11-29 1995-11-28 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5627086A (en) * 1992-12-10 1997-05-06 Sony Corporation Method of forming thin-film single crystal for semiconductor
US5733793A (en) * 1994-12-19 1998-03-31 Electronics And Telecommunications Research Institute Process formation of a thin film transistor
US6808965B1 (en) * 1993-07-26 2004-10-26 Seiko Epson Corporation Methodology for fabricating a thin film transistor, including an LDD region, from amorphous semiconductor film deposited at 530° C. or less using low pressure chemical vapor deposition
US7692223B2 (en) 2006-04-28 2010-04-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5470762A (en) * 1991-11-29 1995-11-28 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US5627086A (en) * 1992-12-10 1997-05-06 Sony Corporation Method of forming thin-film single crystal for semiconductor
US6808965B1 (en) * 1993-07-26 2004-10-26 Seiko Epson Corporation Methodology for fabricating a thin film transistor, including an LDD region, from amorphous semiconductor film deposited at 530° C. or less using low pressure chemical vapor deposition
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5904513A (en) * 1994-10-24 1999-05-18 Micron Technology, Inc. Method of forming thin film transistors
US5936262A (en) * 1994-10-24 1999-08-10 Micron Technology, Inc. Thin film transistors
US6017782A (en) * 1994-10-24 2000-01-25 Micron Technology, Inc. Thin film transistor and method of forming thin film transistors
US6214652B1 (en) 1994-10-24 2001-04-10 Micron Technology, Inc. Thin film transistors and method of forming thin film transistors
US6420219B2 (en) 1994-10-24 2002-07-16 Micron Technology, Inc. Thin film transistors and method of forming thin film transistors
US5733793A (en) * 1994-12-19 1998-03-31 Electronics And Telecommunications Research Institute Process formation of a thin film transistor
US7692223B2 (en) 2006-04-28 2010-04-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same
US8896049B2 (en) 2006-04-28 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

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