JPS59138363A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the electrode resistance value of an MIS type element by making the thickness of the electrode of the MIS type element larger than that of the electrode of a bi-polar element, when an MIS transistor and the bi-polar element having the electrode composed of the same material as the gate electrode of this transistor are formed in the surface layer of a semiconductor substrate. CONSTITUTION:Two N<+> type buried regions 2 are formed in the P type Si substrate 1, an N type layer 3 is epitaxially grown over the entire surface including said regions, which layer 3 is isolated by a P<+> type isolation region 4 while including the regions 2 respectively. Next, an NMOS transistor is formed in one layer 3 isolated in island form, and an NPN bi-polar transistor in the other layer 3, and the gate electrode 11'' composed of polycrystalline Si and the emitter electrode 11''' are provided to each. At this time, the thicknesses of these electrodes are made different to each other. In other words, the thickness of the electrode 11'' is made larger than that of the electrode 11'''.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a method for manufacturing a semiconductor device and a method for manufacturing the same.
Jnsulator Sem1conductor
) ) A semiconductor device in which a transistor is formed and a method for manufacturing the same.

[Prior art]

Conventionally, bipolar elements and MI
S) As a semiconductor device in which a transistor is formed,
Bipolar transistor and MOS (Met4J Qxi
de Sem1conductor )) Those formed with transistors, bipolar transistors and 0M
O8 (Complementary Metal Qx
ide Semiconductor) ) transistors are known (Japanese Unexamined Patent Publication No. 54-46).
Publication No. 489, Japanese Patent Publication No. 55-91857, Japanese Patent Application Publication No. 55-91857
See JP-A No. 5-99763, JP-A No. 55-157257, and JP-A No. 57-75453.

These will be explained using FIG. 1. Figure 1 (11~αa
1 shows the main manufacturing steps of a semiconductor device in which an NPN bipolar transistor and an 0MO8) transistor are formed, and FIGS. 1(a) to 1(e) are schematic cross-sectional views of the main steps shown in purple.

←FIG. 1(a)) An N-type high impurity concentration buried layer 2 is formed in a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is grown to form a semiconductor substrate. Next, 22 layers 4 for isolation between elements, NMO
A P-type well region 5 for forming an S transistor is formed. Furthermore, by selective oxidation method, the oxide film layer 6, NM
OS) Transistor, PMO 8) After forming the gate oxide film 7 of the transistor, boron ions 9 are implanted using the photoresist film 8 as a mask to form the base region 1o of the Bibo 2 transistor.

(FIG. 1(b)) After removing the photoresist film 8, the photoresist film (
(not shown) and by known photoetching.
After opening an emitter window 12 in the gate oxide film 7, a polycrystalline silicon layer 11 to be used as a gate electrode and an emitter electrode is laminated, and the entire surface of the polycrystalline silicon layer 11 is doped with an N-type impurity (for example, arsenic) that will become an emitter electrode of a bipolar transistor. is implanted using the ion implantation method.

(FIG. 1(C)) The polycrystalline silicon layer 11 is photo-etched to form a PMO layer.
8 transistor, NMOS) transistor gate electrode 1
1', 11" and the emitter electrode 11 /// of the NPN bipolar transistor are formed, followed by the growth of oxide m13, 5jCh becomes a mask for forming the source and drain of the NMOS transistor, PMO8) transistor.
The film 14 is formed by a known chemical vapor deposition (CVD) process.
It is formed by the r1) eposition method.

(FIG. 1(d)) NMOS) A window is opened in the transistor section, and N-type source and drain regions 16 are formed by introducing N-type impurities.

(FIG. 1(e)) Again, the 8JO2 film 17 serving as a mask is formed by the CVJ method, windows are opened in the PMOS transistor part and the external base part of the bibolar transistor, and Pm impurities are introduced. A P-type source region, drain region 18, and external base region 18' are formed.

Above, we have described the conventional method and structure for producing polycrystalline silicon for the gate electrode of NMOS transistors and PMO8 transistors and polycrystalline silicon for the emitter electrode of bipolar transistors in the same process. There are problems such as the following ■ in semiconductor devices, and
Conventional semiconductor device manufacturing methods also have the following problems (1) and (2).

(1) First, it is best to use a material with a low resistance value (a thick material in terms of thickness) for the gate of the transistor (NMOS transistor and PMOB transistor). In addition, the emitter region of the bipolar transistor is made of polycrystalline silicon Jvti1.
Since it is necessary to ion-implant N-type impurities into the emitter electrode 1, it is preferable that the emitter electrode be thin.

The conventional semiconductor device shown in FIG. 1 cannot simultaneously satisfy these requirements.

For example, when the emitter electrode is formed of polycrystalline silicon, arsenic is used as an impurity in the emitter region in order to improve the high frequency characteristics of the bipolar transistor. It is preferable to use the ion J] inclusion method from a point. However, when forming emitter regions of the same depth υ by ion implantation into polycrystalline silicon, it becomes necessary to increase the number of ions implanted in proportion to the thickness of the polycrystalline silicon. this is,
The sales expansion coefficient of arsenic in polycrystalline silicon is more than two orders of magnitude larger than that in single crystal, so in the first stage of heat treatment after ion implantation, the arsenic intensity in polycrystalline silicon increases by the amount of ion implantation. This is due to the fact that 1 is divided by the thickness of the polycrystalline silicon film.

When polycrystalline silicon is used as the transistor gate (MOS) transistor, the thickness should be increased to about 3000 Ω, and the resistance should be lowered sufficiently by diffusing normal silicon (total resistance 20 Ω/sq). . However, when attempting to form an emitter region by implanting arsenic ions into an emitter electrode formed of polycrystalline silicon with a thickness of about 3,000, a safe implantation amount is 2×10”/cnl.

Ion implantation of high a thighs requires a long time (for example, 2
It takes 20 minutes to implant ions of
If it is set to about 150 OA), the time will be shortened, but CM
A problem arises in that the resistance value of the gate electrode of the OS transistor increases.

■ Problems with contamination of gate oxide film 7 and change in film thickness. That is, after the gate oxide film 7 is formed, the photoetching process is performed twice (
If steps (2) and (4) in FIG. 1) are present, the gate film 7 may be contaminated or the film thickness may change, causing a fluctuation in the threshold voltage of the NjOS transistor. This problem becomes more severe as the gate oxide film 7 becomes thinner due to higher speed and higher integration of MOS transistors.

■ MOS) Incompatible with the metal gate material of the transistor 6M08) The gate electrode material of the transistor is
Due to the high speed ratio of the circuit, gold silicide (e.g. molybdenum silicide, etc.) and high melting point metals (e.g. tungsten, etc.) are increasingly being used; Incompatible with electrodes.

Furthermore, when forming NPN bipolar transistors and NMOS transistors in addition to the above-mentioned transistors 1 to 2, it becomes difficult to control the current amplification rate (hrg) of the bipolar transistors. Formation of emitter region of bipolar transistor (first
After step (6)) in the figure, it is necessary to perform the step of forming the source and drain regions of the NMOS transistor (aυ in Figure 1). The same level of heat treatment is required, and the current amplification rate of the bipolar transistor tends to fluctuate.

This stock problem is not limited to CMUS transistors, but also PMO
8) General MIS such as transistors, NMOS transistors only) transistors, not only NPN bipolar transistors but also PNP bipolar transistors,
A similar problem occurs in a semiconductor device in which a general bipolar element such as a PNPN thyristor is formed on the same semiconductor substrate.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems (1) to (3).

[Summary of the invention]

The semiconductor device of the present invention that achieves the above object is characterized by having at least MIS,
In a semiconductor device in which a bipolar element having a gate electrode of the MIS) transistor and at least one electrode made of a 1iJ- material is formed, the thickness of the gate' electrode of the MIS) transistor is as described above. It is thicker than the thickness of at least one electrode of the bipolar element.

The method for manufacturing a semiconductor device of the present invention is characterized in that it manufactures a semiconductor device in which at least an MIS transistor and a bipolar element having at least one electrode made of polycrystalline silicon are formed on the main surface of a semiconductor substrate. (2) forming a first electrode layer on at least the gate oxide film; (3) forming a first electrode layer on at least the gate oxide film; (4) forming an oxide film on at least the surface of the gate electrode; (5) forming the main surface of the semiconductor substrate on the main surface of the semiconductor substrate; (4) forming an oxide film on at least the surface of the gate electrode; (6) selectively removing the second polarization layer to form at least one electrode of the bipolar element; There is a particular thing.

[Embodiments of the invention]

The present invention will be explained in detail below based on examples.

Figures 2(1) to 2(f) show the main manufacturing steps of a semiconductor device in which an NPN bipolar transistor and an 0MO8) transistor, which is an embodiment of the present invention, are formed. ) shows a schematic cross-sectional view of the main process.

(Fig. 2 (a)) After selectively thermally diffusing impurities such as antimony into a P-type silicon substrate 1 with a resistivity of 10Ω and brocade to form a buried layer 2 on a highly impurity base, an N-type silicon substrate 1 is formed. An epitaxial layer 3 (specific resistance 1Ω·(7), thickness 6 μm) is grown to form a semiconductor substrate. Next, a P-type element isolation layer 4 (depth 8 μm)
, P-type well region 5 for forming an NMOS transistor
(Surface impurity concentration I x 10"/lyn", depth 4
Further, a thick oxide film 6 (thickness: 1 μm) and a gate oxide film 7 (thickness: 300 Å) are formed by a normal selective oxidation method using a silicon nitride film. The process up to this point is the same as the conventional technique shown in FIG.

Next, a polycrystalline silicon layer 11 having a thickness of approximately 3,500 layers, which will serve as the gate terminals of the PMO8) transistor and the NMO8) transistor, is deposited using a known technique. Next, N-type impurities such as those in the polycrystalline silicon layer 11 are diffused to reduce the resistance value (approximately 20 Ω/Sq).

In this embodiment, since the polycrystalline silicon layer 11 is formed and the gate oxide film 7 is hammered by the polycrystalline silicon layer 11, contamination and film thickness changes of the gate oxide film 7 as described in the prior art are avoided. will not occur. Note that as the gate electrode of the MOS transistor, instead of the polycrystalline silicon 11, metal silicide (for example, molybdenum silicide) or a high melting point metal (for example, tungsten) can also be used. These metal-based electrodes cannot be used in a method in which the emitter electrode is also used as in the prior art.

(FIG. 2(b)) The polycrystalline silicon layer 11 is etched by a known photoetching method to form the gate 'ii:fill' of the PN10S transistor and the gate electrode 11'' of the NMOS transistor. Apply the process,
Oxide film 13 (thickness: 500 mm), NPN on the polycrystalline silicon surface of gate electrodes ii', ii" of MOS transistors
An oxide film 13' (500 mm thick) is formed in the bipolar transistor formation area. direction, gate electrodes 11', 11"
Alternatively, an oxide film may be deposited by CVD instead of a metal-based oxidation process.

(FIG. 2(C)) Using the photoresist film 8 as a mask, ion implantation of boron 9 is performed to form the base region IO of the NPN ζ Ibora transistor (energy 80 keV, implantation 4
712 x 10”/ctrl).

(Figure 2 (d) of nest) After removing the photoresist film 8, the photoresist film (
(not shown), and a window 12 for forming the emitter region of the N P N "polar transistor is opened in the gate oxide film 13' by known photoetching.
A polycrystalline silicon layer 1.9 having a thickness of approximately 1500 nm is laminated by a known method to serve as the emitter electrode of the NPN bipolar transistor. The resistance of this polycrystalline silicon layer 19 is 80Ω
・Since the thickness is thinner than the polycrystalline silicon layer 11, the resistance becomes larger than that of the polycrystalline silicon layer 11.

(FIG. 2(e)) The polycrystalline silicon layer 19 and oxide film 13 in the NMO8 transistor forming region are removed by known etching. Next, deep violet ion implantation (energy l Q k
e V % implantation irl )
The entire emitter region 12' is formed simultaneously with the formation of the source and drain regions 16 of the NMO8) transistor.

(Fig. 2(f)) (f) C. In the known CVD method, 1) Oxidation It! 17(
A photo-etching process is performed to mask the NMOS transistor part, and the oxide film and polycrystalline silicon 19 in the PMO transistor part are removed. A crystal electrode 1'' is formed using an oxide film 17'' formed by the CVD method as a mask. In addition, CV
Instead of the oxide film 17 formed by method D, polycrystalline silicon may be processed using only a photoresist film (not shown).

Next, ion implantation of boron is performed (energy 1
00 k e V, implantation 31 x i O”/i;nL
A heat treatment (950r, 20 minutes) is performed to form the source and drain regions 18 of the PMO8) transistor and the external base region 18'' of the NPN bipolar transistor.
1 #/ by a self-alignment method, and has a large effect of reducing external base resistance.

An embodiment of the present invention has been described above, and the effects of the embodiment of the present invention can be summarized as follows.

■ The thickness of the emitter electrode of an NPN bipolar transistor is thinner than that of the gate electrode of a CMOS transistor.
1' and 11'' are smaller than the resistance of the eminter voltage g 11 ' of the NPN bipolar transistor.

In addition, an emitter electrode made of polycrystalline silicon lt//l
The thickness of the gate electrodes 11' and 11'', which are made of polycrystalline silicon (approximately 1500 mm), is thinner than that of the gate electrodes 11' and 11'' (approximately 3500 mm), so as mentioned above, the implantation of ions such as arsenic can be reduced compared to conventional methods. , ion implantation time can be shortened.

After forming gate electrodes 11' and 11'', separate emitter region 1 is formed.
By forming 1#, the following advantages arise.

@ Since the gate oxide film 7 is covered by the polycrystalline silicon layer 11, there is no contamination or change in the thickness of the gate oxide film 7 (FIG. 2(a)).

θ　MO8I--gate electrode 11' of transistor.

11'', metals such as those mentioned above can also be used.

Other effects obtained from this embodiment are listed below.

■ Current amplification factor of NPN bipolar transistor (hr
z) becomes easier to control. This is the emitter region 12'
This is because the main heat treatment after the formation heat treatment (1000 t?, 30 minutes) is only the heat treatment for forming the source region 18 and drain region 18 of the PMOS transistor. The diffusion coefficient of boron is about twice as large as that of arsenic used to form the emitter region 12' at 1 ooo C. For example, to obtain a junction depth of 0.4 μm, 950 C, 20
A heating time of about 10,000 minutes is sufficient and has almost no effect on the impurity distribution of the layer formed previously for 10,000 minutes.

■ Emitter region 12 of NPN bipolar transistor
It is possible to share the impurity implantation when forming the source region 16 and the drain region 16 of the NMOS transistor with the impurity implantation when forming the source region 16 and the drain region 16 of the NMOS transistor.
Figure αD).

θ PMO8) Photoetching for forming the source region 18 and drain region 18 of the transistor and photoetching for forming the emitter electrode i 1 /// of the NPN bipolar transistor can be performed in the same process, simplifying the process (
Figure 2 03)).

(2) The formation of the source region 18 and drain region 18 of the PMOS transistor and the formation of the external base region 18'' of the NPN bipolar transistor can be performed in the same impurity introduction step, thereby simplifying the process (see α in FIG. 2).

In the above embodiments of the present invention, a semiconductor device in which a CMOS transistor and an NPN bipolar transistor are formed on the same semiconductor substrate has been described as an example, but the present invention is not limited to this, and the present invention is not limited to this. , NMO8) transistors, and general bipolar elements such as PNP bipolar transistors, PNPN thyristors, etc., can be applied to semiconductor devices formed on the same semiconductor substrate. Probably.

The present invention is not limited to these embodiments and can be modified in various ways within the scope of the idea of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a semiconductor device and a method for manufacturing the same that solves the above J and tm of the prior art.

[Brief explanation of the drawing]

FIG. 1 is a diagram and a schematic cross-sectional view showing the main steps of a semiconductor device in which a conventional NPN bipolar transistor and an 0MO8) transistor are formed, and FIG. 2 is a diagram showing an NPN bipolar transistor according to an embodiment of the present invention 0MO8
2) are diagrams and a schematic cross-sectional view showing the main steps of a semiconductor device in which a transistor is formed.

Claims (1)

[Claims] 1. A semiconductor device in which at least an MIS transistor and a bipolar element having at least one electrode made of the same material as the gate electrode of the MIS transistor are formed on the main surface of a semiconductor substrate. , MiS) A semiconductor device characterized in that the gate electrode of the transistor is thicker than the thickness of at least one electrode of the bipolar element. 2. In claim 1, the above-mentioned bipolar element! A semiconductor device characterized in that at least one of the poles and the gate electrode of the MIS transistor are made of polycrystalline silicon. 3. The semiconductor device according to claim 1, wherein the bipolar element is a bipolar transistor. 4. The semiconductor device according to claim 3, wherein the electrode of the bipolar transistor is an eminter electrode. 5. The semiconductor device according to claim 1, wherein the MIS transistor is a CMO8 transistor. 6. In a method for manufacturing a semiconductor device in which at least an MIS) transistor and a bipolar element having at least one electrode made of polycrystalline silicon are formed on the main surface of the semiconductor substrate, at least (1) the main surface of the semiconductor substrate is (2) forming a first 'rt electrode layer on at least the gate oxide film; (3) selectively removing the first electrode layer; a step of forming a gate electrode of an M I S I transistor; (4) a step of forming an oxidation film on at least the surface of the gate electrode; A semiconductor device comprising the following steps: (6) selectively removing the second electrode layer to form at least one 1! pole of the bipolar element. Manufacturing method. 7. A method for manufacturing a semiconductor device as set forth in claim 6, characterized in that the first electrode layer is made of polycrystalline silicon. 8. As set forth in claim 6 A method for manufacturing a semiconductor device, wherein the first electrode layer is made of metal silicide or a high melting point metal such as tungsten. 9. In claim 6, the bipolar element is a bipolar element. io, q+ Claim 9. The method for manufacturing a semiconductor device, wherein the electrode of the bipolar transistor is an emitter electrode. 11. The method of manufacturing a semiconductor device according to claim 6, wherein the MI8 transistor is a CMOB)) transistor.