JPH0221648A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simultaneously realize a MOS transistor and a bipolar transistor of high performance, and realize a device strong against soft errors, by making the concentration of a first N-well where a bipolar transistor is formed differ from that of a second N-well where a PMOS transistor is formed, and setting the impurity concentrations of the second N-well and a P-well where an NMOS transistor is formed in a specified range. CONSTITUTION:The concentration of a first N-well where a bipolar transistor is formed and that of a second N-well where a PMOS transistor is formed are made different. The impurity concentration of the second N-well and that of P-well where an NMOS transistor is formed are set in the range of 2X10<16>cm<-3>-2X10<17>cm<-3>. When a semiconductor device, in which the concentrations of N-wells are mutually different, is to be obtained, the following process is used; after an N-type epitaxial layer which constitutes a first N-well on a P-type substrate is formed, impurity to form the N-well on a P-type substrate is formed, impurity to form the N-well in the PMOS region, and impurity to form the P-well in the NMOS region are implanted by an ion implantation method, and the second N-well and the P-well having specified concentrations are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Industrial Application Field) The present invention relates to a semiconductor device constituting a mixed LSI (Large Scale Integrated Circuit) of bipolar transistors and MOS transistors, and a method for manufacturing the same.

(Prior art) Conventionally, when forming a bipolar element and a MOS element on the same semiconductor substrate, an N''13 (area) is selectively buried on a P-type silicon substrate, and then a P-type epitaxial layer is formed. 2.0 to 5.0 μm thick, and N-wells are selected in the regions where bipolar transistors and PMOS transistors will be formed, and P-wells are selected in the NMOS transistor formation regions and bipolar transistor element isolation regions using ion implantation and lithography methods. The wells are formed by implanting impurities, performing well diffusion using heat treatment at 1100° C. or higher, and then forming MO3 and bipolar elements using normal methods.

FIG. 5 shows the cross-sectional structure of a bipolar and MOS mixed LSI formed by the conventional technique, FIG. 6 shows the concentration profile of the N-well part, and FIG. 7 shows the concentration profile of the P-well part. 62 is a buried N+ region 6367 is an N well, 64 is an element isolation region,
6 is a buried N+ extraction electrode, 66 is a P well, 68
is gate acid 1 arsenic film, 69 is gate polycrystalline silicon, 70 is
71 is an emitter polycrystalline silicon, 72 is an N''' emitter, 73 is an internal base, 74 is a field P layer, 77 is an N − region of the LDD horizontal layer, 78 is an N +
area, 79 is P, area 80 is external base, 81 is LD
The D formation wall side 82 is an insulating film between the eyebrows, and 83 is an Aj electrode.

(Problem to be Solved by the Invention) When using the above-mentioned conventional technology, as the MOS is miniaturized, the concentration of the N well 67 is increased in order to prevent the short channel effect of the MOS from occurring, for example. If the well 63 is used in an Ibora device, the collector concentration of the bipolar device will increase. When the collector concentration of a bipolar element increases, the breakdown voltage between the base and collector, which is the basic performance of a bipolar element, < s v c
ao) and early voltage (■AF) deteriorate.

In addition, in the conventional technology, by using the above-mentioned P type epitaxial layer, well diffusion is required to rub the N wells 63 and 67 with the concentration profile G required for MOS or bipolar. 63 and 6
Even if the buried P''IJJ region 84 is formed as a countermeasure against the punch-slip of No. 7, upward diffusion occurs violently and affects the characteristics of the MOS.In other words, there is a limit to the concentration of the buried P'' region.

Further, when the collector is formed by well diffusion, the collector a degree profile has a slope, so that the bipolar characteristics on the high flow side are likely to deteriorate.

An object of the present invention is to realize a semiconductor device in which a high-performance bipolar transistor and a high-performance MOS transistor are simultaneously mounted together, and which is also strong in soft error resistance.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a semiconductor device that constitutes a mixed LSI including a bipolar transistor and a MOS transistor, in which the concentrations of the N-wells formed in the two transistors are different from each other. It is characterized by

Further, in the present invention, the N-type impurity concentration in the epitaxial layer constituting the N-well for forming the bipolar transistor is set in the range of 5 × 15 -3 to 2 × 16, -3, and the epitaxial layer with this concentration is The present invention is characterized in that the layer is used for the collector (first N-well) of the bipolar transistor. Further, the present invention is characterized in that, in addition to the buried N+ region used in the bipolar transistor, a buried P+ region is formed at a position that should be below the P well region. Further, the present invention provides a semiconductor device that constitutes a mixed LSI including a bipolar transistor and a MOS transistor, in which the concentration of N-wells used in each of the two transistors is different from each other.
After forming an N-type epitaxial layer on a P-type substrate, PMO
Impurities for forming an N well in the S region and a P well in the NMO3 region are implanted by ion implantation to a concentration of 4xlO.
a.

It is characterized by forming a second N-well and P-well of ~2×1017cxr-3. Moreover, the present invention
Mixed L of bipolar transistor and MOS transistor
In a semiconductor device constituting an SI, when obtaining a semiconductor device in which the concentrations of the N wells used in each of the two transistors are different from each other, the concentration of the buried P + region between the P type substrate and the N type epitaxial layer is determined. I×1016al
+-3~5x17c! ! The epitaxial layer was formed at a temperature of 1.0 to 1.8 μm, and the subsequent heat treatment was performed at 1050°C.
Please do not do this for more than 10 minutes, and
+The feature is that well diffusion on the buried region is not performed.

That is, in the present invention, the epitaxial layer is made N-type and is implanted in advance with the concentration necessary for the collector of the bipolar transistor, and the N-well of the P, MOS transistor is made of a type that is added to the concentration of the epitaxial layer. A conventional ion implantation method is used to form the collector, but nothing is done to the epitaxial layer of the collector, and no well diffusion is performed. This allows embedded P+
Even if the concentration of the region is increased, impurities in the buried region should not be exposed above. In this way, a high-performance MOS transistor and a bipolar transistor can be realized at the same time, and a device that is resistant to soft errors can be realized.

(Example) FIGS. 1(a) to 1(J) are sectional views showing an example of the present invention in the order of steps.

First, a silicon semiconductor substrate 1 of P type and (100) crystal plane.
An opening 12 is formed by depositing an insulating Mll on the wafer 0 and selectively removing the insulating Mll only at a position where a buried collector region is to be formed by photolithography. Next, this opening 12
An N+ type buried collector layer 13 is formed by vapor phase diffusion of Sb (antimony) or ion implantation of As (arsenic) or sb (FIG. 1(a)).

Next, after the insulation 11g1l is completely removed, a buried P region 16' is formed by B ion implantation in a region other than the buried N+ region 13 using photolithography.

At this time, the ion implantation conditions for B are, for example, 100 eν and a dose of 1.5 x 1013 cm-2 as shown in Fig. 1 (b
)).

At this time, the buried collector region and the buried P+ region 16' may be formed using the self-line method. After that, P is doped as an impurity on the substrate 10 by epitaxial growth.
An N-type epitaxial layer 14 containing about I x 1016 cm -'' of (phosphorus) is formed.

The growth temperature at this time is, for example, 1130°C, and the layer 1
4 has a thickness of 1.2 μm (FIG. 1(C)).

Next, a mask for ion implantation (not shown) is formed using photolithography, and using this mask, P ions are injected into the PMO5 formation region of the N-type epitaxial layer 14 at an acceleration energy of 160 ev and 5×1. The N well region 15 is selectively formed by ion implantation at a dose of 0.012/cm2, and then, using another ion implantation mask, B ions are implanted at an acceleration energy of 100 KeV 6×1o.
By implanting ions at a dose of 12/c112, the upper part of the P well region 6 is selectively formed (FIG. 1(d)).
.

Note that in this step, the P well region 16 is first formed, and then the N well region 16 is formed.
A well region 15 may also be formed.

Subsequently, a field oxide film 17 for isolating the MOS transistors and the MOS transistors from the bipolar transistors is formed by selective oxidation. The thickness of this field oxide film 17 is about 6000. Note that, prior to the formation of this field oxide film 17, an ion implantation region 18 for preventing field inversion is formed in a self-aligned manner.

Subsequently, a dummy gate oxide film 19 having a thickness of approximately 150 mm is formed over the entire surface by thermal oxidation. Thereafter, channel ion implantation regions m2 for threshold adjustment and bunch-through prevention of the P-channel MOS transistor and N-channel MOS transistor are formed on the surfaces of the N-well region 15 and the P-well region 6 through the dummy gate oxide film 19, respectively.
0.21 is formed. In the channel ion implantation region 20 on the side of the N well region 15, B ions are implanted with an acceleration energy of 20 eν and a dose of 3×1012/cI+2, and P ions are implanted with an acceleration energy of 240 eV and an acceleration energy of 2×
It is formed by two ion implantations consisting of ion implantation with a dose of 12/am2. The channel ion implantation region 21 on the P well region 16 side is formed by implanting B ions at an acceleration energy of 20 KeV and a dose of 4×1012/12. Further, by implanting P ions into the N-type epitaxial layer 14 at an acceleration energy of 320 eV and a dose of I×10 16/■2, a tape (DeeP) N + connected to the buried collector layer 13 is formed. A type ion implantation region 22 is formed (FIG. 1(e)).

Next, after peeling off the entire surface of the dummy gate oxide film 19,
A gate oxide film 23 having a thickness of about 150 layers is formed on the surface by an oxidation method. Further, a polycrystalline silicon layer 24 is deposited thereon to a predetermined thickness by CVD (chemical vapor deposition). Next, impurities are introduced into this polycrystalline silicon layer 24 by P diffusion to lower the resistance (FIG. 1(f)).
.

Next, the polycrystalline silicon layer 24 and gate oxide 11123 are patterned using photolithography.

The gate electrodes of the MOSh transistors are left on the N well region 15 and the P well region 16, respectively.

Subsequently, the field oxide film 17 and photolithography are performed.
KeV acceleration energy 5 x 1015/csn
Ion implantation was performed at a dose of 2, and N well region 1
P+ type source region 25 and drain region 2 on the surface of 5
form 6. At this time, ions are simultaneously implanted into the N-type epitaxial layer 14 on the buried collector layer 13 to form an external base region 27 of the bipolar transistor.
form. Next, using the field oxide film 17 and the gate electrode as a mask, ion implantation is performed on P''4 on at a dose of 60 eV acceleration energy 4 x 1013/am2 to form an N° type on the surface of the P well region 16. A source region 28 and two drain regions are formed (see FIG. 1(g)).
)).

Next, a CVD SiO2 film 30 was deposited on the entire surface at a rate of 2000
This CVD film is deposited to a certain thickness and then anisotropically etched, such as RIE (reactive ion etching).
-3i02M30 is etched, CVD-8io2
After forming a mask (not shown) that leaves plA 30 only on the side surfaces of the gate electrode and exposes only the P well region 16, As ions are deposited at an acceleration energy of 50 eV and a dose of 5 x 1015/cII2. By performing ion implantation, an N+ type source region 31 and drain 11 region 32 are formed on the surface of the P well region 16. That is, this P well region 16 has a so-called LDDIi.
A number of N-channel MOS transistors are formed. Subsequently, oxidation is performed for 30 minutes at 900° C. in an 02 atmosphere to form a post-oxide film 33. Furthermore, the surfaces of the P well region 15 and the N well region 16 are covered with a photoresist or the like (5×13/'cI+2).
Ion implantation is performed at a dose of 1 to form a P-type internal base region 34 in the N-type epitaxial layer 14 on the buried collector layer 13 (FIG. 1(h)).

Next, a CVD-3i O2 film 35 as a glabellar insulating film is deposited on the entire surface to a thickness of 2000 mm, and then this CVD-3i O2 film 35 is deposited to a thickness of 2000 mm.
3L 02[35, contact hole 36 communicating with the surface of the internal base region 34 and the N channel M
O3) Contact holes 37 communicating with the surface of the N+ type drain region 32 on the transistor side are opened, respectively. After this, a layer of polycrystalline silicon is deposited to a thickness of 2000 nm,
Further patterning is performed to leave a polycrystalline silicon layer 38, 39 only at the positions where the emitter tth, high resistance element, and wiring area are to be formed.Next, a portion of the three polycrystalline silicon layers is covered with a mask 40 such as photoresist. rear,
5 As ions were applied to the 383 polycrystalline silicon layers.
Ion implantation is performed at an acceleration energy of 0 eV and a dose of 5×15/2 to inject N into the internal base region 34.
At the same time as forming the type emitter region 41, the resistance of the polycrystalline silicon layer 38 is reduced to form the emitter electrode quadrupole of the bipolar transistor. At the same time, a portion of the polycrystalline silicon layer 39 is removed to reduce the resistance, thereby forming the drain wiring of the N-channel MOS transistor and the high resistance element 42 (FIG. 1(i)). On the land of the above ion implantation process, 950
Even better contact characteristics can be obtained by performing so-called rapid/door annealing, which is a heat treatment at a temperature of 1100°C to 1100°C for 5 seconds to 1 minute.

After depositing an interlayer insulating film 43 consisting of a CVD-8iO2M:tBPSG film on the entire surface and flattening the surface, a polycrystalline silicon layer as the emitter electrode is applied to the interlayer insulating JII 43. 38 and the contact hole 4 leading to the surface of the polycrystalline silicon layer 39 serving as the drain wiring.
At the same time, a P-channel Mo
A contact hole 46 communicating with the surface of the source region 25 of the s-transistor is opened. Next, aluminum for wiring is deposited on the entire surface by vacuum evaporation or the like, and this is further patterned to form aluminum wiring 47.degree. 48.49 (FIG. 1(j)).

Note that in the semiconductor device manufactured in this way,
A part of the polycrystalline silicon layer 39 constitutes a high resistance element 42, and this high resistance element 42 is used as a load resistance of a static type memory cell.

In this embodiment, the N-channel MO3 is changed to the LDD elliptic P-channel 81, and the S is the normal structure, or an optimal structure may be used for the 81os depending on the size of each element. FIG. 2 shows the N-well impurity distribution in this structure, FIG. 3 shows the P-well impurity distribution, and FIG. 4 shows the N-well impurity distribution in the bipolar region.

The advantages of doing so as described above are as follows.

That is, in the prior art, in a bipolar 0MO8 structure with a gate length of 0.8 μ or less, h f of a bipolar element
When t current amplification factor) = 100, "vCBOe (withstand voltage between collector and base) = t 5 v, s
V CEO emitter-collector breakdown voltage) = 5V, VA
F (early voltage) = 1ov, Io (collector current)
= f at 10rOA (cutoff frequency) = IGH7L,
or cannot be achieved. This is because the concentration of the collector layer 63 is high,
Another reason is that the profile is tilted by 1 degree.

However, according to the present invention, when hfe=100, B VcBo =41 V and B VCEO=13
When V, V = 51V, and Ic = 101WA, fTF = 30H2 can be achieved. This is because the collector layer 14 remains an epitaxial layer and has a low concentration, and the concentration profile does not have a slope. Further, the well 16 constituting the MOS transistor is formed by ion implantation, and the subsequent heat treatment is performed at a low temperature and in a short time to prevent well diffusion, so that a high performance MOS transistor can be obtained. Furthermore, since the Jrf of the buried P layer 16' can be increased, a device with strong soft error resistance can be realized when forming a device with severe soft errors such as a memory LSI.

In the present invention, when forming an epitaxial layer (first N-well) for forming a bipolar transistor, the N-type impurity concentration in the epitaxial layer is set to 5×1015a.
The practical range is set in the range of 1+-3 to 2Xlo16 cm-3. Moreover, after forming the above epitaxial layer, P
Ion implantation is performed to form an N well in the MO5 region and a P well in the M OS M region, but the practical range is to set the concentration of each well to 4 × 10 ~ 2 × 170-3. A second N-well and P-well are formed. Also, when forming a device that is prone to soft errors, such as a memory LSI, the embedded P ``f;
The concentration of 1t416' is IXI○16 pieces - 3 ~ 5 ×
cm, and the thickness of the epitaxial layer is x,
0 μm to 1.8 μm, and the heat treatment after forming the epitaxial layer is not performed for more than 10 minutes at 1050'c or more to prevent well diffusion.

[Effects of the Invention] As explained above, according to the present invention, a high-performance bipolar transistor and a high-performance MO3h run transistor,
Moreover, a semiconductor device with strong soft error resistance can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for obtaining a configuration according to an embodiment of the present invention, FIGS. 2 to 4 are impurity concentration distribution diagrams according to the same configuration, FIG. 5 is a sectional view of a conventional device, and FIG. FIG. 7 is an impurity concentration distribution diagram. 10... Silicon semiconductor substrate, 11... Insulating film, 1
2... Opening portion, 13... Embedded collector layer, 14...
・N-type epitaxial layer, 15...N well region, 1
6...P well region, 16'...buried P+ region,
17...Field oxide film, 18...Ion implantation g
area, one... dummy gate oxide film, 20.21...
Channel ion implantation region, 22... N type ion implantation region, 23... Gate oxide film, 24... Polycrystalline silicon layer, 25... P type source region, 26...
P+ type drain@region, 27...external base region, 2
8...N-type source region, 2...N'' type drain region, 30...CV D SiO2 film, 31
...N+ type source region, 32...N+ type train region, 33... Post oxide film, 34... Internal base region, 35... CVDSiO2 film, 36.37,4
4.45.46...Contact hole, 38.39.
...Polycrystalline silicon layer, 40...Mask, 41...
Emitter region, 42... High resistance element, 43... Interlayer insulating film, 47, 48.49... Aluminum wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 1, Display of the case, Japanese Patent Application No. 170683/1983, Title of the invention, Semiconductor device and its manufacturing method, 3, Person making the amendment, Relationship with the case, Special r "Applicant (307) Toshiba Corporation 4, Agent 3-chome Kasumigaseki, Chiyoda-ku, Tokyo [J 7-2-6, Subject of amendment 8, Contents of amendment (1) Special + i'F +: i'I request (2) Specification 11f, page 6, line 5 to page 8, line 13, start with [(Means for solving the problem)...is something that can be realized.'' The statement is corrected as follows. (Means and effects for solving the problem) The present invention provides bipolar transistors, PMOS and NM
In a 16-conductor device comprising mixed mounting of o5 transistors and SI, the bipolar transistor and l) M
The impurity concentrations of the first N-well and the second N-well in which the O3+ transistors are formed are different from each other, and the impurity concentration of the second N-well and the P-well in which the NMO3 IMOS transistor is formed is 2 x 10 "am-3". ~2 x 1
017cra-3. Further, the present invention provides a semiconductor device that constitutes a mixed LSI including a bipolar transistor and a MOS transistor, in which the N-wells used in each of the two transistors have different concentrations.
After forming an N-type epitaxial layer constituting the first N-well on a P-type substrate, impurities for forming a P-well in the PMO8 region and NMOS region are implanted by ion implantation to a concentration of 2. X 1016cm' ~2X
This method of manufacturing a semiconductor device is characterized by forming a second N well and a P well of 1017c+n-3. The present invention also provides a semiconductor device constituting a mixed LSI including bipolar transistors and MOS transistors.
pt of the N-well used for each of the above-mentioned both transistors.
When obtaining semiconductor devices with different rx, the concentration of the buried P small region between the P-type substrate and the N-type epitaxial layer is set to 1×IQ 16 cm −3 to 5×IQ 17
cm -3 and the thickness of the epitaxial layer is 1.0 to 1.8 μm to form the epitaxial layer, and the subsequent heat treatment is not performed for more than 10 minutes at a temperature of 1050° C. or higher, This method of manufacturing a semiconductor device is characterized in that well diffusion on the P buried region is not performed. In this way, a high-performance MO5I transistor and a bipolar transistor can be realized at the same time, and a device that is resistant to soft errors can be realized. (3) On page 18 of the specification, lines 11 to 14, "1 contains the words ``The concentration of each of these wells... is formed.'' [
The concentration of each of these wells is made higher than that of the first N well. Specifically, 2 X 10 "am-' ~ 2 X 10
It is desirable to set it within a range of 17 cm-'. ” and 1 correction. Claims and manufacturing method. IH12+ as a human agent

Claims (5)

[Claims] (1) A semiconductor device constituting a mixed LSI including a bipolar transistor and a MOS transistor, characterized in that N-wells in which both the transistors are formed have different concentrations. (2) The N-type impurity concentration in the epitaxial layer constituting the N-well for forming the bipolar transistor is 5
×10^1^5cm^-^3 to 2 × 10^1^6cm, and the epitaxial layer with this concentration is used for the collector (first N-well) of the bipolar transistor. The semiconductor device according to claim 1. (3) Buried N^ used in the bipolar transistor
Claim 1 characterized in that, in addition to the + region, a buried P^+ region is formed at a position that should be below the P well region.
The semiconductor device described in . (4) In a semiconductor device constituting a mixed LSI of a bipolar transistor and a MOS transistor, when obtaining a semiconductor device in which the concentrations of the N wells used for each of the two transistors are different from each other, a first N well is formed on a P-type substrate. After forming an N-type epitaxial layer constituting the N-type epitaxial layer, impurities are implanted by ion implantation to form an N-well in the PMOS region and a P-well in the NMOS region, to a concentration of 4×10^.
A method for manufacturing a semiconductor device, comprising forming a second N well and a P well each having a size of 1^6 cm^-^3 to 2 x 10^1^7 cm^-^3. (5) In a semiconductor device constituting a mixed LSI of a bipolar transistor and a MOS transistor, when obtaining a semiconductor device in which the concentrations of the N wells used for each of the two transistors are different from each other, it is necessary to The density of the embedded P^+ region between
^6cm^-^3~5x10^1^7cm^-^3, and the thickness of the epitaxial layer is 1.0~1.
The epitaxial layer is formed to have a thickness of 8 μm, and the subsequent heat treatment is not performed at 1050° C. or higher for more than 10 minutes to prevent well diffusion on the P^+ buried region. A method for manufacturing a semiconductor device.