JPH1027854A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to compose an N-MOS and a P-MOS of single polarity gate electrode and surface channel type by providing a transistor having a germanium containing electrode formed on a gate insulating film. SOLUTION: A transistor, having a semiconductor substrate 10, the gate insulating film 23 formed on the semiconductor substrate 10 and a germanium electrode layer 31 formed on the gate insulating film 23, is provided. For example, the gate insulating film is composed of the silicon oxide film 23 on the surface of the substrate 10 and a surface nitride film 24. A germanium electrode 31, where P-type impurities are introduced, a polycrystalline silicon layer 32 as the upper electrode, and an offset insulating film 25, consisting of silicon oxide, are stacked successively thereon. An insulative side wall 26 is formed on the side wall using silicon oxide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface channel type N-type field effect transistor (NMOS) and a P-type field effect transistor (PMO
The present invention relates to a semiconductor device that can constitute S) and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, an integrated circuit using a MOS type semiconductor is a CMOS which uses an NMOS and a PMOS complementarily.
Molds are the mainstream. As the gate material of the CMOS, polysilicon in which an N-type impurity is introduced is used for both the NMOS and the PMOS.

In this case, however, the NMOS has a surface channel type, but the PMOS has a threshold value of -1 V or more in the case of the surface channel type. Has been adopted.

[0004]

SUMMARY OF THE INVENTION However, LSI
As the miniaturization of the MOS transistor progresses, the influence of the short channel effect becomes remarkable as the gate length of the MOS transistor decreases,
Attention has been paid to a surface channel type PMOS which can suppress the short channel effect more easily than a buried channel type which easily causes the short channel effect.

However, the surface channel type PMOS has N
In the case where polysilicon doped with a type impurity is used as a gate material, the threshold voltage becomes -1 V or more.
It is necessary to introduce a P-type impurity into the gate electrode. At this time, an N-type impurity is introduced into the NMOS and a P-type impurity is introduced into the PMOS into the polysilicon constituting the gate electrode. Therefore, there are problems such as an increase in chip cost and manufacturing time due to an increase in the number of steps such as separate ion implantation at the time of gate electrode formation, and a change in threshold value due to mutual diffusion of these impurities in the gate electrode. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made in consideration of the above-mentioned problems, and has been made in consideration of the above problems, and has been made in consideration of the above-mentioned problems by providing a single-polarity gate electrode and a surface channel type NMOS
It is an object of the present invention to provide a semiconductor device capable of forming a semiconductor device and a PMOS and a method of manufacturing the same.

[0007]

In order to achieve the above object, the present invention comprises a semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and germanium formed on the gate insulating film. A semiconductor device including a transistor having a germanium electrode layer is provided.

In order to achieve the above object, the present invention provides a step of forming a gate insulating film on a semiconductor substrate, a step of forming a germanium-containing germanium electrode layer on the gate insulating film, Forming an upper electrode layer composed of a polycrystalline silicon layer or a compound alloy layer of refractory metal and silicon on the electrode layer; introducing an impurity into the germanium electrode layer; Forming an offset insulating layer, patterning the offset insulating layer, the upper electrode layer, and the germanium electrode layer to form a gate electrode; and introducing impurities into a semiconductor substrate to form a source / drain. And a method for manufacturing a semiconductor device, comprising:

The semiconductor device of the present invention is characterized in that a material containing germanium is used for a gate electrode in contact with a gate insulating film. The present inventor has found that the work function of germanium into which a P-type impurity has been introduced is approximately halfway between the work functions of N-type silicon and P-type silicon. Therefore, by using germanium doped with a P-type impurity as a gate electrode material, the threshold voltage of both the NMOS and the PMOS is lowered, and the impurity of the conductivity type opposite to that of the substrate is ion-implanted. Without the buried channel type,
Both the NMOS and the PMOS can be of a surface channel type with a lowered threshold. Therefore, a surface channel type CMOS can be realized with a gate electrode of a single polarity,
The effect of shortening the buried channel can be suppressed.

The process for manufacturing such a semiconductor device is the same as the process for manufacturing a normal MOS transistor, except for the process for forming a germanium electrode containing germanium directly on the gate insulating film. Can be omitted, and the process cost can be reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but the present invention is not limited to the following embodiments. The semiconductor device of the present invention is characterized in that a germanium electrode is used as a gate electrode in contact with a gate insulating film. FIG. 1 shows an example in which the present invention is applied to a CMOS.

This CMOS is, for example, a silicon substrate 10
N well 1 is formed in a region separated by the element isolation insulating film 21.
1 and P well 12 are formed, and N well is PM
An OS transistor is formed in the P-well, and an NMOS transistor is formed in the P-well. The gate insulating film is formed on the substrate 1
0 surface silicon oxide film 23 and its silicon oxide film 23
And a nitride film 24 whose surface is nitrided.
4, as a structure common to both NMOS and PMOS transistors, a germanium electrode 31 made of germanium doped with a P-type impurity, a polycrystalline silicon layer 32 as an upper electrode, and an offset insulating film made of silicon oxide 25 are sequentially stacked, and an insulating sidewall 26 is formed on these side walls with silicon oxide.
The LDDs 13 and 1 are provided in the substrate on both sides of the gate electrode 31.
5 and source / drain 14 and 16 are provided for each transistor. The germanium electrode 31 may be a mixed crystal of germanium and silicon instead of germanium, and the upper electrode may be a silicide which is an alloy of a high melting point metal and silicon such as tungsten silicide instead of polycrystalline silicon. good.

Next, the effect of using P-type germanium as the gate electrode will be described. The work functions of germanium and silicon are shown in the energy band diagram of FIG. In this figure, Ec is the energy at the edge of the conduction band, Ev is the energy at the edge of the valence band, the dashed line below Ec is the donor order,
The dashed line above Ev is the acceptor order. The work function is
The energy required to extract electrons from the Fermi level to the vacuum is shown. Here, Ec is the Fermi level in which an N-type impurity is introduced, and Ev is the Fermi level in which a P-type impurity is introduced. As shown in FIG. 2, when the N-type impurity is degenerated, the work functions of silicon and germanium are almost equal, and when the P-type impurity is degenerated, germanium is smaller by about 0.5V. The Fermi level of P-type germanium lies between N-type silicon and P-type silicon.

Therefore, as shown in FIG. 3, when the P-type germanium is used for the gate material, the threshold value of the NMOS is about 0.6 V as compared with the case where the N-type polycrystalline silicon is used for the gate. Rise, approx. 0.6 at PMOS threshold
V is reduced. Also, compared to the case where P-type polycrystalline silicon is used for the gate, the threshold value of the NMOS is about 0.5
V decreases and the threshold value of the PMOS increases by about 0.5V. Therefore, the absolute values of the threshold values of the NMOS and the PMOS are approximated.
There is no need to form a PN junction by ion-implanting an impurity of the conductivity type opposite to that of the substrate into the channel region. As a result, a buried channel structure is not formed.

As described above, a CM having a unipolar gate structure using germanium doped with a P-type impurity as a gate electrode.
The OS has a structure in which both the PMOS transistor and the NMOS transistor are of the surface channel type, and the short channel effect can be suppressed. Since the gate electrode has a single polarity, unlike a gate electrode in which impurities having different polarities are introduced, threshold fluctuation due to mutual diffusion of gate impurities does not matter. In addition, since both NMOS and PMOS are surface channel types and not buried channel types, it is advantageous for miniaturization of transistors.

In the case of a surface channel type NMOS using P-type polycrystalline silicon for the gate, it is difficult to lower the threshold value below 0.8 V even if the substrate impurity concentration is reduced. By using germanium as a gate material, a surface channel type having a threshold of about 0.3 V can be realized. Similarly, a surface channel type having a threshold value of about 0.3 V can be formed for NMOS. Further, by implanting impurities having different polarities into the substrate surface, a threshold value up to about 0.1 V can be realized.

Next, the process of manufacturing the CMOS will be described. First, as shown in FIG. 4A, an active region of the silicon substrate 10 is covered with a silicon nitride film, and an element isolation insulating layer 21 is formed by a usual method of thermal oxidation. Next, a silicon oxide film 22 is formed by thermal oxidation as a pad layer for preventing metal contamination during ion implantation. The conditions of the thermal oxidation are, for example, a temperature of 850 ° C., a time of 40 minutes, an oxygen gas, and a thickness of about 8 nm.

Thereafter, as shown in FIG.
The resist R1 is opened only in the S region, and for example, phosphorus is implanted into the silicon substrate by ion implantation to form the N well 11. The implantation conditions at this time are, for example, P, the energy is 300 keV, and the dose is 3 × 10 ¹²
cm- ² . Furthermore, to adjust the threshold and suppress the short channel effect, ion implantation
Phosphorus is implanted into a silicon substrate. At this time, the implantation conditions are, for example, P, energy 100 keV, and dose 3 ×.
10 ¹² cm ^-2 and P, energy 30keV, dose 1
It is about × 10 ¹² cm ^-2 .

Next, after removing the resist R1, FIG.
(C) As shown in FIG.
The resist is opened only in the region of, and for example, boron is implanted into the silicon substrate 10 by ion implantation to form a P well. The ion implantation conditions at this time are, for example, B, energy 200 keV, and dose 3 × 10 ^12.
cm- ² . Further, boron is implanted into the silicon substrate by ion implantation for adjusting the threshold value and suppressing the short channel effect. The implantation conditions at this time are, for example, B, 50 keV, 3 × 10 ¹² cm ⁻² ,
It is about 15 keV and about 1 × 10 ¹² cm ⁻² .

Next, after removing the resist, FIG.
As shown in (d), after removing the resist, the silicon oxide film 22 is removed with a diluted hydrofluoric acid solution, and then a silicon oxide film 23 as a gate insulating film is formed to a thickness of, for example, about 5 nm by thermal oxidation. Then, in order to prevent oxidation of a germanium layer to be formed next, the silicon oxide film 23 is nitrided to form a nitride film 24. These silicon oxide film 23 and nitride film 24 form a gate insulating film. Next, the germanium layer 31 is formed by, for example, 50 n
m, and the polycrystalline silicon layer 32 is
Deposit about 0 nm. In this case, a mixed crystal of germanium and silicon may be formed instead of germanium, and silicide which is an alloy of silicon and a high melting point metal such as tungsten silicide may be formed instead of polycrystalline silicon.

Then, ions are implanted into the germanium layer 31 to introduce a P-type impurity into the germanium layer 31. The implantation conditions at this time are, for example, BF ₂ , an energy of 20 keV, and a dose of about 3 × 10 ¹⁵ cm ⁻² .
Further, as shown in FIG. 5E, a silicon oxide film 25 as an offset insulating film is
Deposit to a degree.

Next, as shown in FIG. 5F, a resist is formed by lithography, and an offset insulating film 25, a polycrystalline silicon layer 32, and a germanium layer 31 are etched in this order by anisotropic etching to form a gate pattern. To form Then, a resist is opened only in the PMOS region by lithography, and BF ₂ is implanted into the silicon substrate by ion implantation to form an LDD. The implantation conditions at this time are, for example, BF ₂ , 10 ke
V, about 5 × 10 ¹³ cm ⁻² . Further, a resist is opened only in the NMOS region by lithography, and arsenic is implanted into the silicon substrate by ion implantation to form an LDD. The injection conditions at this time are, for example, A
s, 15 keV, about 3 × 10 ¹³ cm ⁻² . As a result, a structure in which the LDD is formed as shown in FIG.

Next, after removing the resist, a silicon oxide film is deposited, for example, to a thickness of about 150 nm by a conventional CVD method, and the silicon oxide film is etched back by anisotropic etching. As shown, a sidewall 26 of a silicon oxide film is formed.

Then, as shown in FIG.
The silicon oxide film 27 is formed to a thickness of, for example, 10 by EOSCVD.
Deposit about nm. Next, PMOS by lithography
The resist R3 is opened only in the region, and the polycrystalline silicon layer 32 and the silicon substrate 1 are formed by ion implantation.
The source / drain 14 is formed by injecting BF ₂ into 0. The implantation conditions at this time are, for example, BF ₂ , 10 ke
V, about 3 × 10 ¹⁵ cm ⁻² . At this time, no boron is implanted into the germanium electrode 31 by the offset insulating film 25.

Next, as shown in FIG. 6 (i), a resist R4 is opened only in the NMOS region by lithography, and arsenic is implanted into the polycrystalline silicon layer 32 and the silicon substrate 10 by ion implantation to form a source region. A drain 16 is formed. The implantation conditions at this time are, for example, As, an energy of 20 keV, and a dose of 3 × 10 ^15.
cm- ² . At this time, arsenic is not implanted into the germanium electrode 31 by the offset insulating film 25.

By the above steps, the CMOS shown in FIG.
Can be obtained. Thereafter, heat treatment is performed at 950 ° C. for 10 seconds by lamp annealing in a nitrogen atmosphere. Less than,
A silicide, a contact, and a wiring are formed by a conventional method. Through the above steps, a CMOS including a surface channel type NMOS and a PMOS with a gate electrode of a single polarity can be manufactured. Since impurities are not separately applied to the gate electrode, the number of steps is reduced, which is advantageous in cost.

In the above description, an example in which the present invention is applied to a CMOS is described. However, the present invention is not limited to the CMOS, but can be applied to other transistors having a MOS structure. Various changes can be made without departing from the scope.

[0028]

According to the semiconductor device of the present invention, it is possible to manufacture a surface channel type NMOS and PMOS with a single polarity gate electrode. Further, the method for manufacturing a semiconductor device according to the present invention can reliably manufacture such a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a CMOS according to the present invention.

FIG. 2 is an energy band diagram of silicon and germanium.

FIG. 3 is a schematic diagram showing the relationship between the polarity of a gate electrode and the threshold voltages of NMOS and PMOS.

FIGS. 4A to 4C are cross-sectional views showing steps of manufacturing the CMOS shown in FIG.

FIGS. 5D to 5F are cross-sectional views showing steps subsequent to FIG. 4;

6 (g) to 6 (i) are cross-sectional views showing steps subsequent to FIG.

[Explanation of symbols]

11 well, 12 p well, 21 element isolation insulating film, 23 gate oxide film, 24 nitride film, 25 offset insulating film, 31 germanium electrode layer, 32 upper electrode layer

Claims (6)

[Claims] 1. A semiconductor comprising a transistor having a semiconductor substrate, a gate insulating film formed on a surface of the semiconductor substrate, and a germanium electrode layer containing germanium formed on the gate insulating film. apparatus. 2. The semiconductor device according to claim 1, wherein the gate electrode of the complementary field effect transistor is formed of a germanium electrode layer containing germanium. 3. The semiconductor device according to claim 1, wherein the germanium-containing germanium electrode layer contains a P-type impurity. 4. A gate electrode comprising: a germanium-containing germanium electrode layer laminated on a gate insulating film; a polycrystalline silicon layer or a compound alloy layer of refractory metal and silicon laminated on the germanium electrode layer. The semiconductor device according to claim 1, wherein: 5. A step of forming a gate insulating film on a semiconductor substrate; a step of forming a germanium electrode layer containing germanium on the gate insulating film; and a polycrystalline silicon layer or a high-crystalline silicon layer on the germanium electrode layer. Forming an upper electrode layer composed of a compound alloy layer of a melting point metal and silicon, introducing an impurity into the germanium electrode layer, forming an offset insulating layer on the upper electrode layer, A semiconductor device comprising: a step of patterning an offset insulating layer, an upper electrode layer, and a germanium electrode layer to form a gate electrode; and a step of introducing impurities into a semiconductor substrate to form a source / drain. Production method. 6. The method according to claim 5, further comprising the step of nitriding the surface of the gate insulating film before forming the germanium electrode layer on the gate insulating film.