JPH09232524A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain short channel effect in both a pMOS transistor and an nMOS transistor, by covering a substrate part protruding from an end portion of an adjacent element isolation insulating layer, with a gate electrode via a gate insulating layer. SOLUTION: In a CMOS to be formed, pMOS and nMOS transistors are formed on the same substrate and are electrically isolated from each other by an element isolation insulating layer 21. Both of gate electrodes of the pMOS and nMOS transistors have the polarity of n<+> type, and the pMOS transistor is of a so-called edge-operating type, having a channel formed on a protruding substrate surface 11 protruding from the element isolation insulating layer. In this edge-operating MOS transistor, since the channel edge is surrounded by the gate electrode, the ratio of depletion-layer capacitance to gate capacitance is smaller than that of a flat channel. Therefore, controllability by the gate potential of the channel depletion layer is improved, and a sharp subthreshold characteristic is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (Comple
The present invention relates to a highly miniaturized and integrated semiconductor device having different conductivity type MOS transistors on the same substrate such as a mentary MOS) and a method for manufacturing the same.

[0002]

2. Description of the Related Art CMO
As an item required for a high speed device such as S, there is a reduction in the gate length, but the problem is to suppress the short channel effect. The structure of CMOS is as shown in FIG.
An n well and a p well are formed in a region electrically isolated by the field oxide film 21 on the surface of the substrate 10, a pMOS transistor is formed in the n well, and an nM is formed in the p well.
OS transistors are respectively formed, and the gate electrodes 30 of these transistors are composed of a polysilicon layer 31 into which impurities are introduced and a metal-containing layer 32 such as silicide formed thereon. As the impurities introduced into the polysilicon forming the gate electrode, the same n ⁺ type is generally used for both the pMOS transistor and the nMOS transistor.

However, when such an n-type impurity is introduced into the polysilicon of the gate electrode, the pMOS transistor and the nM are caused by the work function difference between the n-type polysilicon and the substrate.
In order to set the threshold voltage (V _th ) of the OS transistor to be the same, it is necessary to implant a p-type impurity for adjusting the threshold voltage in both the nMOS transistor and the pMOS transistor. Therefore, although the nMOS transistor is a surface channel type device, a very shallow pn junction is formed in the channel region of the pMOS transistor, and the pMOS transistor becomes a buried channel type device. However, in the buried channel type transistor,
It is difficult to suppress the short channel effect after deep submicron.

Further, polysilicon forming the gate electrode
Impurities to be introduced into⁺Type, this time nMOS
The transistor has a buried channel structure,
It becomes difficult to suppress the effect of the electric field. As a countermeasure, pMOS
P doped with boron for the gate electrode of the transistor ⁺Po
NMOS gate electrode polarity is n⁺
Type, pMOS gate electrode polarity is p⁺To be a mold
Both transistors are made into surface channel, and short channel
There is a technology to increase the drive while suppressing the effect.

However, in this method, p ⁺ gate pMO
When the S transistor and the n ⁺ gate nMOS transistor are combined into a CMOS and the gate electrode has a wiring structure in which polysilicon and metal silicide are stacked or a wiring structure in which polysilicon and metal are stacked, such a metal-containing layer Since the diffusion speed of the impurities therein is much higher than that of silicon or silicon oxide, the impurities of p ⁺ and n ⁺ are mutually diffused to cancel the impurities in the polysilicon. Due to this phenomenon, there is a problem that the Fermi level in the polysilicon fluctuates, and the threshold voltage fluctuates due to depletion of the gate electrode when the gate voltage is applied, resulting in fluctuations in device characteristics.

Therefore, there is a demand for a CMOS device capable of suppressing the short channel effect in both the pMOS transistor and the nMOS transistor even when the gate electrode is either of the n ⁺ type or the p ⁺ type.
The present invention has been made in view of the above circumstances, n ⁺ -type, p
^It has a gate electrode made of polysilicon having one of positive polarity and has a pMOS transistor and nM.
It is an object of the present invention to provide a semiconductor device such as CMOS capable of suppressing a short channel effect in both transistors of an OS transistor and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention provides the following semiconductor device. (1) A field-effect transistor of the first conductivity type and a field-effect transistor of the second conductivity type which are electrically isolated by an element isolation insulating layer are provided in the same substrate, and the gate electrode is of the first conductivity type or In a semiconductor device made of polysilicon doped with one of impurities of the second conductivity type, a substrate surface on which a channel in a field effect transistor of a conductivity type opposite to the conductivity type of impurities of the gate electrode is formed is A semiconductor device characterized in that it protrudes from an end portion of an adjacent element isolation insulating layer, and the protruding substrate portion is covered with a gate electrode via a gate insulating layer. (2) The semiconductor device according to (1), wherein the impurity of the gate electrode is n-type, and the channel in the p-type field effect transistor is formed on the protruding substrate surface. (3) The semiconductor device according to (1), wherein the impurity of the gate electrode is p-type, and the channel in the n-type field effect transistor is formed on the protruding substrate surface.

Further, in order to achieve the above object, the present invention provides the following method of manufacturing a semiconductor device. (4) A field-effect transistor of the first conductivity type and a field-effect transistor of the second conductivity type which are electrically isolated by an element isolation insulating layer are provided in the same substrate, and the gate electrode is of the first conductivity type or A method of manufacturing a semiconductor device made of polysilicon into which an impurity of one of the second conductivity types is introduced, the method comprising: forming an element isolation insulating layer on a substrate surface; Of the element isolation insulating layer on both sides of the region for forming a field effect transistor of a positive type is etched to corrode the substrate surface on which the transistor is formed to protrude from the edge of the element isolation insulating layer. To form a protruding substrate surface, and a step of covering the protruding substrate surface with an insulating layer,
A step of covering the surface of the protruding substrate with a gate electrode made of polysilicon containing an impurity having a conductivity type opposite to that of a channel formed on the surface of the protruding substrate. Method. (5) The method for manufacturing a semiconductor device according to (4) above, further including the step of previously eroding the surface of the substrate on which the element isolation insulating layer is formed by etching to form a recess. (6) After the step of forming the element isolation insulating layer on the surface of the substrate, at least the region for forming a field effect transistor having a conductivity type opposite to the impurity of the polysilicon layer forming the gate electrode and the element isolation insulating layers adjacent to both sides thereof are formed. Masking a portion other than the end portion with a resist, a step of eroding the end portion of the element isolation insulating layer not covered with this resist by etching to project the substrate surface from the end portion of the element isolation insulating layer, and using the resist as a mask A method of manufacturing a semiconductor device according to the above (4), including a step of forming a well by ion implantation.

The semiconductor device of the present invention is an nM such as CMOS.
In a semiconductor device in which an OS transistor and a pMOS transistor are provided on the same substrate and the polarity of the impurity of the gate electrode is either n type or p type, the conductivity type opposite to the polarity of the gate electrode, for example, the gate electrode A so-called edge operation type in which a pMOS transistor has a n-type polarity and an nMOS transistor has a p-type gate electrode polarity when the substrate surface where a channel is formed protrudes from the end of an adjacent element isolation insulating layer. It is a MOS transistor.

In such an edge operation type MOS transistor, the upper surface of the edge of the element isolation insulating layer is located below the surface of the silicon substrate in the element region, and the channel edge of the portion in contact with the element isolation is surrounded by the gate electrode. The ratio of capacitance to gate capacitance is smaller than that of the planar channel. Therefore, the controllability by the gate potential of the channel depletion layer is improved, and a steep subthreshold characteristic is obtained, and at the same time,
Less susceptible to substrate bias. Edge motion type MO
The threshold voltage of the S transistor is lower than that of a normal MOS transistor.

Therefore, when the n ⁺ gate electrode is used,
The pMOS transistor serves as an edge operation type MOS transistor, but since this pMOS transistor has a small threshold voltage due to the edge operation, it is not necessary to ion-implant an impurity having a conductivity type opposite to that of the substrate, or very few impurities are required. . As a result, this pMOS becomes a surface channel type, whereas the conventional type is a buried channel type.
In addition, the short channel effect can be suppressed due to the steep subthreshold characteristics of the edge operation transistor. Further, the decrease in the threshold voltage due to the effect of the edge is offset by the work function difference between the gate electrode and the n-type silicon substrate being reduced by using the n ⁺ gate electrode, so that the threshold voltage is increased. It As a result, the pMOS transistor can be made into a surface channel while using n ⁺ polysilicon for the gate, and the short channel effect of the pMOS transistor can be suppressed in combination with the edge operation.

On the other hand, when the p-type gate electrode is used, in the present invention, the nMOS transistor is an edge operation type transistor, but the gate electrode of this nMOS transistor is not the normal n-type but the p-type, Although the nMOS threshold voltage increases due to the work function difference from the substrate,
Since the edge type is used, the threshold voltage is lowered, which can be offset.

As a result, since the pMOS transistor has a p-type gate electrode, it can be made into a surface channel to suppress the short channel effect. On the other hand, the nMOS transistor also has a short channel due to the above characteristics of the edge operation type transistor. The effect can be suppressed.

Further, a method of manufacturing a semiconductor device according to the present invention
As a method of forming the edge operation type MOS transistor,
At least an end portion of the element isolation insulating layer on both sides of a region where the edge operation type transistor is formed, which is in contact with the region is eroded by etching so that a substrate surface on which a channel is formed protrudes from the end portion of the element isolation insulating layer. Thus, a protruding substrate surface that performs an edge operation is formed, and the protruding substrate surface is covered with a gate electrode through a gate insulating film.

As a result, it is possible to surely form the edge structure for performing the edge operation. In this case, a so-called recess LOCOS method is used in which the substrate surface in the region where the element isolation insulating layer is formed is etched by etching so that the edge of the protruding substrate surface is formed perpendicular to the substrate surface. It is desirable to adopt.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention will be specifically described below, but the present invention is not limited to the following embodiments. [First Embodiment] The present embodiment relates to a CMOS in which the polarity of the impurity of the gate electrode is n-type and the pMOS is an edge-operation type field effect transistor. This will be described using 5. Note that these figures are cross-sectional views in a direction perpendicular to the channel direction of the gate electrode of the MOS transistor, and the source / drain are in the vertical direction of the paper surface.

First, as shown in FIG. 1, a silicon substrate 1
At 0, a field oxide film (element isolation insulating layer) 21 is formed by recess LOCOS. In this recess LOCOS process, for example, a pad oxide film 41 is formed with a thickness of about 5 nm and a silicon nitride film 42 is formed with a thickness of about 200 nm, and a region for forming a field oxide film is opened by lithography to expose the substrate surface in that region. . Then, the substrate surface is etched to dig down, for example, about 30 nm. Then, for example, wet oxidation is performed at 950 ° C. to grow the field oxide film 21. When the field oxide film is formed under such conditions, the edge portion 21a of the field oxide film 21 becomes substantially vertical to the substrate surface. When forming an edge operation type transistor, it is preferable to form the edge portion of the field oxide film as perpendicular to the substrate surface as possible.

Next, as shown in FIG. 2, a silicon nitride film 42 is formed.
After removing the pad oxide film 41 and the pad oxide film 41, a resist film R1 is formed only in the nMOS transistor formation region by photolithography. In this case, the end of the resist R1 is placed on the field oxide film 21. As a result, at least an end portion (about half in the figure) of the field oxide film 21 in contact with the substrate surface of the pMOS formation region is exposed.

Then, using the resist R1 as a mask, HF
The field oxide film 21 is etched using a solution, and the surface of the field oxide film 21 is removed so that the substrate surface 10b is higher than the edge 21b of the field oxide film. As a result, the edge portion 10a in contact with the field oxide film 21 on the substrate surface is exposed, and the protruding substrate portion 11 is formed.
Is formed. At this time, the upper surface of the edge of the field oxide film is about 30 nm lower than the upper surface of the protruding substrate portion. That is, the height (recess depth) of the side surface of the protruding substrate portion is about 30 nm. The recess depth can be set in the range of about 20 to 100 nm.

Then, using the resist film R1 as a mask, n
For example, phosphorus ions are implanted into regions other than the MOS region (pMOS region) with a dose amount of 8 × 10 ¹² and an energy of about 330 keV to form an n-well. In addition, ion implantation for threshold adjustment, punch-through prevention ion implantation, element isolation ion implantation, and the like are performed.

Next, after removing the resist R1, FIG.
As shown in FIG. 5, a resist film R2 is formed in the pMOS region, and boron ions, for example, are implanted in the nMOS region at a dose amount of 1 × 10 ¹³ and an energy of 280 keV to form a p well. In addition, threshold implantation ion implantation, punch-through prevention ion implantation, element isolation ion implantation, and the like are performed.

Then, after removing the resist R2, FIG.
As shown in, the gate oxide film 22 is formed to a thickness of about 8 nm by, for example, a pyrogenic oxidation method. As a result, the protruding substrate portion 11 is covered with the gate oxide film 22.
Next, the polysilicon 31 forming the gate electrode is deposited by, for example, about 70 nm by the CVD method. Then, for example, it is annealed in POCl ₃ gas at 830 ° C. for 70 minutes, and phosphorus is introduced into the polysilicon layer 31 to make the polarity of the polysilicon n ⁺ type. Next, for example, WSi is deposited to a thickness of about 70 nm as the metal-containing layer 32 forming the gate electrode by the CVD method. As the metal-containing layer 32,
The metal silicide or the metal itself can be selected.

Next, after patterning the photoresist, as shown in FIG. 5, the polysilicon layer 31 and the metal-containing layer 32 are patterned by dry etching to form a gate electrode 30. After that, ion implantation for LDD is performed to form LDD. Then, after forming the silicon oxide film by CVD, the sidewall oxide spacer 23 is formed by etching back the silicon oxide film by dry etching. After that, nMOS, pMOS
Ion implantation is performed on each of the regions to form source / drain regions. In this way, the CM as shown in FIG.
An OS can be formed.

In this CMOS, a pMOS transistor and an nMOS transistor are formed on the same substrate, and these transistors are electrically isolated by an element isolation insulating layer 21. The polarities of the gate electrodes of both the pMOS transistor and the nMOS transistor are n ⁺ type, and the pMOS transistor is of the so-called edge operation type in which the channel is formed on the protruding substrate surface 11 protruding from the element isolation insulating layer. .

This edge operation type MOS transistor is
Since the channel edge is surrounded by the gate electrode, the ratio of the depletion layer capacitance to the gate capacitance is smaller than that of the planar channel. Therefore, the controllability by the gate potential of the channel depletion layer is improved, a steep subthreshold characteristic is obtained, and at the same time, it is less susceptible to the influence of the substrate bias. This allows
The short channel effect can be suppressed.

Further, in a normal pMOS transistor,
When the polarity of the gate electrode is n ⁺ , the work function difference with the n-type substrate (well) in the pMOS transistor becomes small, so the threshold voltage becomes large, and in order to adjust the threshold voltage with the nMOS transistor, Substrate (well)
It is necessary to lower the threshold voltage by ion-implanting an impurity of the conductivity type opposite to that. On the other hand, the threshold voltage of the edge operation MOS transistor is lower than that of a normal transistor. Therefore, in the CMOS of the present invention, the pMOS transistor can be of the edge operation type to lower the threshold voltage, so that the ion implantation of the impurity of the conductivity type opposite to that of the substrate becomes unnecessary or a small amount can be obtained. I'm done. Therefore, the pMOS transistor of the present invention becomes a surface channel type, and the short channel effect can be suppressed. In addition, the short channel effect is also suppressed due to the above-mentioned characteristics of the edge operation type. [Second Embodiment] In the present embodiment, the polarity of the gate electrode in the first embodiment is n ⁺ type, whereas the polarity of the gate electrode is p type and the conductivity type nM opposite to the gate electrode is used.
The present invention relates to a CMOS in which an OS transistor is an edge operation type MOS transistor. The manufacturing process is shown in FIGS.

First, as shown in FIG.
Recess LOCOS on the silicon substrate 10 in the same manner as
Then, a field oxide film (element isolation insulating layer) 21 whose edge is formed perpendicular to the substrate surface is formed. Next, FIG.
After removing the silicon nitride film 42 and the pad oxide film 41, as shown in FIG.
The resist film R3 is formed only in the S transistor formation region. In this case, the end portion of the resist R3 is placed on the field oxide film 21. As a result, at least an end portion (about half in the figure) of the field oxide film 21 in contact with the substrate surface of the nMOS formation region is exposed.

Then, using the resist R3 as a mask, HF
The field oxide film 21 is etched using a solution, and the surface of the field oxide film 21 is removed so that the substrate surface 10b is higher than the upper end of the edge portion of the field oxide film. As a result, the edge portion 10a of the substrate, which was in contact with the field oxide film on the substrate surface, is exposed, and the protruding substrate portion 1
1 is formed. At this time, the upper surface of the edge of the field oxide film is about 30 nm lower than the upper surface of the protruding substrate portion 11. That is, the height (recess depth) of the side surface of the protruding substrate portion 11 is about 30 nm. The recess depth can be set in the range of about 20 to 100 nm.

After that, using the resist film R3 as a mask, p
Boron ions, for example, are implanted into regions other than the MOS region (nMOS region) at a dose of 1 × 10 ¹³ and energy of about 280 keV to form a p-well. In addition, ion implantation for threshold adjustment, ion implantation for punch-through prevention,
Ion implantation for element isolation is performed.

Next, after removing the resist R3, FIG.
As shown in FIG. 5, this time, a resist film R4 is formed in the nMOS region, and, for example, phosphorus ions are implanted with a dose amount of 8 × 10 ¹² and an energy of about 330 keV to form an n well. In addition, threshold implantation ion implantation, punch-through prevention ion implantation, element isolation ion implantation, and the like are performed.

Then, after removing the resist R4, FIG.
As shown in, the gate oxide film 22 is formed to a thickness of about 8 nm by, for example, a pyrogenic oxidation method. As a result, the protruding substrate portion 11 is covered with the gate oxide film 22.
Then, a polysilicon layer 31 forming a gate electrode is deposited by, eg, about 70 nm by the CVD method. Next, C
By the VD method, for example, WSi is deposited to a thickness of about 70 nm as the metal-containing layer 32 forming the gate electrode. As the metal-containing layer 32, metal silicide or metal itself can be selected. Then, for example, BF ₂ is ion-implanted with an energy of 20 kev and a dose of about 2 × 10 ¹³ / cm ² , and boron is introduced into the polysilicon layer 31 to make the polarity of the polysilicon p ⁺ type.

Next, after patterning the photoresist, the polysilicon layer 31 and the metal-containing layer 32 are patterned by dry etching to form the gate electrode 30, as shown in FIG. After that, ion implantation for LDD is performed to form LDD. Then, after forming the silicon oxide film by CVD, the sidewall oxide spacer 23 is formed by etching back the silicon oxide film by dry etching. After that, nMOS, pMO
Ion implantation is performed on each of the S regions to form source / drain regions. In this way, a CMOS as shown in FIG. 10 can be formed.

The CMOS of the present invention shown in FIG.
The polarities of the gate electrodes of both the OS and pMOS transistors are p-type, and the nMOS transistors are edge-operation type. Therefore, since the gate electrode of the pMOS transistor is p-type, it becomes a surface channel type and the short channel effect can be suppressed. On the other hand, n
In a MOS transistor, a p-type gate electrode and a p-type substrate (well) are combined to increase the threshold voltage, but due to the edge operation type, the threshold voltage decreases.
Further, since it is of the edge operation type, the short channel effect can be suppressed. This makes it possible to make the pMOS transistor a surface channel and suppress the short channel effect and threshold voltage of the nMOS transistor while using p ⁺ -type polysilicon for the gate electrode.

[0034]

According to the semiconductor device of the present invention, the short channel effect of CMOS or the like is effectively suppressed. Further, according to the method for manufacturing a semiconductor device of the present invention, such a semiconductor device can be manufactured reliably.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device of the present invention following that of FIG. 1;

FIG. 3 is a cross-sectional view showing the manufacturing process of the embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing the manufacturing process of the embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing the manufacturing process of the embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing process of another embodiment of the semiconductor device of the invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of another embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process of another embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 7;

FIG. 9 is a cross-sectional view showing the manufacturing process of another embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 8;

FIG. 10 is a cross-sectional view showing the manufacturing process of another embodiment of the semiconductor device of the present invention, which is subsequent to FIG. 9;

FIG. 11 is a cross-sectional view showing a structure of a conventional CMOS.

[Explanation of symbols]

Reference numeral 10: substrate, 11: protruding substrate surface, 21: element isolation insulating layer, 22: gate oxide film, 30: gate electrode, 31: polysilicon layer of gate electrode, 32: metal-containing layer of gate electrode

Claims (6)

[Claims] 1. A first-conductivity-type field effect transistor and a second-conductivity-type field-effect transistor, which are electrically isolated by an element isolation insulating layer, are provided in the same substrate, and a gate electrode has a first conductivity type. Type or second conductivity type semiconductor device made of polysilicon into which impurities are introduced. In a semiconductor device, a substrate surface on which a channel is formed in a field effect transistor of a conductivity type opposite to the conductivity type of impurities of the gate electrode. But,
A semiconductor device characterized in that it protrudes from an end portion of an adjacent element isolation insulating layer, and the protruding substrate portion is covered with a gate electrode via a gate insulating layer. 2. The semiconductor device according to claim 1, wherein the impurity of the gate electrode is n-type, and the channel in the p-type field effect transistor is formed on the protruding substrate surface. 3. The semiconductor device according to claim 1, wherein the impurity of the gate electrode is p-type, and the channel in the n-type field effect transistor is formed on the protruding substrate surface. 4. A field-effect transistor of the first conductivity type and a field-effect transistor of the second conductivity type, which are electrically isolated by an element isolation insulating layer, are provided in the same substrate, and the gate electrode is the first conductivity type. A method of manufacturing a semiconductor device comprising polysilicon into which an impurity of one of a second conductivity type and a second conductivity type is introduced, the method comprising: forming an element isolation insulating layer on a substrate surface; By eroding at least the end portions of the element isolation insulating layers on both sides of the region where a field effect transistor of the opposite conductivity type is in contact with the region by etching, the substrate surface on which the transistor is formed is removed from the end portions of the element isolation insulating layer. Forming a protruding substrate surface by protruding, covering the protruding substrate surface with an insulating layer, and impure of a conductivity type opposite to the conductivity type of the channel formed on the protruding substrate surface. And a step of coating the surface of the protruding substrate with a gate electrode made of polysilicon containing a substance. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of previously eroding the surface of the substrate on which the element isolation insulating layer is formed by etching to form a recess. 6. A region for forming a field effect transistor having a conductivity type opposite to that of an impurity of a polysilicon layer forming a gate electrode and a device isolation insulating layer adjacent to both sides thereof after the step of forming the device isolation insulating layer on the substrate surface. At least other than the end portion of the element is masked with a resist, the step of causing the end portion of the element isolation insulating layer not covered with this resist to erode by etching to project the substrate surface from the end portion of the element isolation insulating layer, The method of manufacturing a semiconductor device according to claim 4, further comprising the step of forming a well by ion implantation as a mask.