JPH11233646A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the resistance of an n-type MOSFET at the same time and suppress the overgrowth of a p-type MOSFET, by suppressing a silicidizing reaction on a p<+> -type source/drain region to a degree substantially equal to that on an n<+> -type source/drain region, in the step for titanium-salicide treatment of a CMOSFET. SOLUTION: An n<+> type source/drain region 61 and an n<+> type gate electrode 62 are formed. Then, a p<+> type source/drain region 65 and a p<+> type gate electrode 66 are formed. Furthermore, using the same resist 63 as a mask, ions As<+> 67 are implanted into the region 65 and the electrode 66, to thereby form a layer 68 containing a high concentration of As on the surfaces of the region 65 and the electrode 66. After an activating heat treatment has been effected, a titanium-silicifying step is performed. Since each surface has As in substantially equal concentration, the silicidizing reaction proceeds uniformly on the surfaces. Therefore, even if the resistance of the titanium silicide on the n MOS side by increasing the first sintering temperature, the overgrowth of the titanium silicide on the p MOS side can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a CM for lowering resistance by siliciding a gate, a source and a drain in a self-aligned manner.
The present invention relates to a method for manufacturing an OSFET.

[0002]

2. Description of the Related Art The structure of a CMOS semiconductor device can be broadly divided into two types depending on the structure of a gate electrode. One is an n-n gate type using n-type polysilicon for both an n-type MOSFET and a p-type MOSFET, and the other is the other. The n-type MOSFET is of a pn gate type using n-type polysilicon and the p-type MOSFET is of p-type polysilicon. In a MOS semiconductor device, a so-called short channel effect in which a threshold voltage is reduced due to generation of charge sharing or punch-through becomes remarkable as the element becomes finer, and a pn gate type structure, which has a structure that can easily suppress this, is used. Has become the mainstream of current fine CMOS development.

[0003] In CMOS semiconductor devices, with the recent miniaturization of elements, a technique for reducing the resistance by silicidation on the gate and the source / drain region has become more and more essential. Reducing the resistance of the gate electrode is for improving the circuit speed, and reducing the resistance on the source and drain is for simplifying the layout of the device. In forming silicide on the gate and the source / drain region, for example, in a conventional nn gate type CMOSFET, a silicide layer is provided on gate polysilicon in advance, and then a gate electrode is processed. It is possible to use a polycide structure separately formed. However, in a pn gate type CMOSFET, which is currently the mainstream of development, doping of the gate electrode is performed simultaneously with source / drain implantation. A salicide process for simultaneously siliciding the source and drain regions is essential. A conventional example of the salicide process is also disclosed in, for example, Japanese Patent Application Laid-Open No. 8-78361, and the outline thereof is shown below with reference to FIGS. 4A to 4E as an example.

As shown in FIG. 4A, after an element isolation region 102 is formed in a p-type silicon substrate 101, a p-type MO is formed.
An n-type well region 103 is formed in a region where an SFET is to be formed. A gate oxide film 104 is formed in an active region surrounded by the element isolation region, and then polycrystalline silicon 105 is grown as a gate electrode material. Thereafter, the gate electrode 106 is formed by patterning the polycrystalline silicon by a well-known method such as a photolithography method and a dry etching method. After that, a sidewall 107 made of an oxide film is formed on the side surface of the gate electrode.

Thereafter, as shown in FIG. 4B, an n ⁺ -type source / drain region 108 and a p ⁺ -type source / drain region 109 are formed by photolithography and ion implantation. At this time, the gate electrodes are also doped, and the n ⁺ -type gate electrode 110 and the p ⁺ -type gate electrode 1
It becomes 11. Thereafter, an activation heat treatment is performed at 900 ° C. for about 20 minutes in a nitrogen atmosphere to recover the silicon crystal and activate the impurities.

[0006] Thereafter, as shown in FIG. 4 (c), As ⁺
At an energy of 30 keV and a dose of 3 × 10 ¹⁴ c
Ion implantation at m ⁻² and n ⁺ type source / drain regions 10
8. An amorphous silicon layer 112 having a depth of about 30 nm is formed in the p ⁺ -type source / drain region 109, the n ⁺ -type gate electrode 110, and the p ⁺ -type gate electrode 111. After removing the native oxide film on the surface of the polycrystalline silicon and the surface of the semiconductor substrate, which is the gate electrode, with dilute hydrofluoric acid, titanium 113 having a thickness of 30 nm is sputtered on the semiconductor substrate heated to 450 ° C.

After that, as shown in FIG. 4D, by performing a first sinter at 650 ° C. for 30 seconds in a nitrogen atmosphere, only titanium in contact with silicon is silicided,
A titanium silicide 114 is formed. At this time, titanium in a portion in contact with the element isolation region 102 and the side wall 107 and a part of titanium on the semiconductor substrate are nitrided into titanium nitride 115.

Next, as shown in FIG. 4E, wet etching is selectively performed using a mixed solution of aqueous ammonia and aqueous hydrogen peroxide to remove only the titanium nitride 115.
Thereafter, a second sintering is performed at 850 ° C. for 10 seconds in a nitrogen atmosphere to form a titanium silicide 116 having a lower electric resistivity than the titanium silicide 114 formed earlier.

However, FIGS. 4 (a) to 4 (e)
In the conventional example shown in (1), the following drawbacks occur.

As is well known, in the titanium salicide process, a first As ⁺ -doped n.sup. ⁺
There is a problem that the silicidation reaction is inhibited during sintering. FIGS. 5A and 5B schematically show the titanium salicide process when the n ⁺ -type source / drain region is heavily doped.

After the same steps as those shown in FIGS. 4A to 4D, the first sintering is performed as shown in FIG.
(A). n ⁺ type source / drain region 121, n ⁺
P ⁺ type source / drain region 12
3 and titanium silicides 125, 126, 127, and 128 are formed on the p ⁺ gate electrode region 124, respectively.
And n ⁺ -type source / drain region 121, on n ⁺ -type gate electrode 122, on p ⁺ -type source / drain region 123, p
A part of titanium on ⁺ gate electrode region 124 is nitrided to form titanium nitride 131. Then, FIG.
As shown in FIG. 3B, selective wet etching is performed using a mixed solution of ammonia water and hydrogen peroxide water to remove only the titanium nitride 131, and then a second sinter is performed to form the titanium silicide 125, 126,
Titanium silicides 132, 133, 134, and 135 having electric resistivity smaller than 127 and 128 are formed.

[0012] As shown in FIG. 5 (a), since the high concentration of As is present in the n ⁺ -type source and drain region 121, silicide reaction is inhibited during the first sintering, n ⁺ -type source and drain region 121 above Is formed only in a small thickness. Therefore, by performing the second sintering, the titanium silicide 13 having a lower electric resistivity is used.
Even if 2 is formed, the layer resistance is higher than the other portions of titanium silicides 133, 134, and 135 because the film thickness is small. For example, H. Kawaguchi et al., “A Robust 0.15 μm CMOS Tec
hnologywith CoSi ₂ Salicid
e and Shallow Trench Isol
ation ", Symp. on VLSI Tec
h. , P125 (1997), the sheet resistance of titanium silicide on the n ⁺ source / drain region is reduced to about 8 Ω / □ when the source / drain As ion implantation dose is 2 × 10 ¹⁵ cm ⁻² . It is reported that if the dose of the source / drain As ion implantation is increased to 3 × 10 ¹⁵ cm ^{−2, the} resistance is increased to about 25 Ω / □. Therefore, in order to reduce the resistance of the n ⁺ diffusion layer, the dose of the source / drain As implantation is set to 2 × 10 ¹⁵
It can be seen that it is necessary to suppress it to about cm ^-2 .

Now, the adverse effects caused by keeping the dose of the source / drain As implantation low will be described below. As described at the beginning, in order to suppress the short-channel effect, the current development of CMOSFETs mainly uses a pn gate structure. In this CMOSFET having a pn gate structure, impurities are introduced into the gate by ion implantation. Usually, in order to reduce the number of steps, the impurity is introduced into the gate simultaneously with the source / drain ion implantation. Now, in order to suppress the reaction inhibition of titanium silicide on the n ⁺ diffusion layer and reduce the resistance by increasing the film thickness, the dose of As at the time of source / drain ion implantation must be 2 times.
Although it is necessary to suppress the impurity concentration to about × 10 ¹⁵ cm ^{−2, the} impurity introduced into the gate electrode also decreases, and the dopant concentration near the polysilicon / gate oxide film interface decreases. Would. When the gate depletion phenomenon occurs, the gate capacitance decreases, and as a result, the drive current of the MOSFET decreases. In fact, H. Kawaguchi et al., “A Robust
0.15μm CMOS Technology wi
th CoSi ₂ Salicide and Sha
"low TrenchIsolation", Sym
p. on VLSI Tech. , P125 (199
In 7), when the dose of source / drain As ion implantation is increased to 3 × 10 ¹⁵ cm ⁻² , the gate depletion rate can be reduced to 2.5%.
This indicates that when the dose of the s-ion implantation is reduced to 2 × 10 ¹⁵ cm ⁻² , the depletion is about 6.5%.

[0014]

As described above, in the conventional method of forming titanium silicide, in order to reduce the resistance of titanium silicide on the n ⁺ -type source / drain region,
The dose of As ⁺ at the time of source / drain implantation is set to, for example, 2 ×
It is necessary to keep it as low as about 10 ¹⁵ cm ^-2 . However, if the dose of As ⁺ at the time of source / drain implantation is suppressed to a low value, the n ⁺ -type gate electrode becomes depleted, the gate capacitance of the nMOS becomes small, and the problem that the drive current of the nMOS decreases is caused. Source drain As
In order to increase the dose of ion implantation and to reduce the layer resistance of titanium silicide on the n ⁺ -type source / drain region, increase the film thickness during titanium sputtering or increase the temperature of the first sinter. It is effective. However, if the film thickness during titanium sputtering is increased or the temperature of the first sinter is increased, the following problem occurs on the p-type MOSFET side. The titanium silicidation reaction is more liable to occur on the p ⁺ type source / drain region than on the n ⁺ source / drain region. Therefore, if the film thickness at the time of titanium sputtering is increased or the temperature of the first sinter is increased, overgrowth is caused. Short-circuit occurs between the p ⁺ -type source / drain region and the p ⁺ -type gate region, and the titanium silicide is formed thickly on the p ⁺ -type source / drain region so that the p ⁺ -type source / drain region and the n-type well region In such a case, problems such as an increase in junction leakage occur. In order to suppress the junction leak between the p ⁺ -type source / drain region and the n-type well region, there is a method of increasing the junction depth of the p ⁺ -type source / drain region. It cannot be used because it degrades the short channel characteristics of the MOSFET. In order to suppress a short circuit between the p ⁺ -type source / drain region and the p ⁺ -type gate region, it is conceivable to increase the thickness of the gate electrode. Can not be adopted because it promotes.

The biggest cause of such a problem is that the titanium silicidation reaction is hindered on the n ⁺ -type source / drain region by the influence of As which is highly doped. In other words, there is no As on the p ⁺ -type source / drain diffusion layer, or the concentration of As is too low, so that the titanium silicidation reaction is too fast on the p-type MOSFET side. The present invention provides a method for manufacturing a semiconductor device that solves the above-mentioned problems.

[0016]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a p-type well region in a region where an n-type MOSFET is to be formed in a semiconductor substrate; a step of forming an n-type well region in a region where a p-type MOSFET is to be formed; a step of forming a gate oxide film on a semiconductor substrate; a step of forming a gate electrode; In particular, a step of ion-implanting As ⁺ to form an n ⁺ -type source / drain region and an n ⁺ -type gate electrode;
A p-type impurity is ion-implanted into a region where an SFET is to be formed.
At the same time as forming the ⁺ type source / drain region and the p ⁺ type gate electrode, ion implantation is performed so that n-type impurities, particularly As ^+, are shallow and the surface concentration is about the same as that of the n ⁺ type source / drain region of the n-type MOSFET. , p ⁺ -type source and process of as the surface of the surface and the p ⁺ gate electrode of the drain region forming a layer containing a high concentration, and performing activation heat treatment, n ⁺ -type source and drain regions on the known method,
n ⁺ type gate electrode, p ⁺ type source / drain region, p
^The method includes a step of silicidation on the ⁺ type gate electrode.

According to the present invention, the As concentration on the n ⁺ -type source / drain region and the p ⁺ -type source / drain region are substantially the same, and the titanium silicidation reaction on the p ⁺ -type source / drain region is suppressed by the n ⁺ -type source / drain region. This can be suppressed to a level above the drain region. Therefore, when the resistance of titanium silicide on the n ⁺ -type source / drain region is reduced by increasing the thickness of the titanium film and increasing the temperature of the first sinter, the overgrowth of titanium silicide on the pMOS side, which has conventionally been a problem, Short circuit between the gate and the source / drain and increase in junction leak current can be suppressed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below. FIGS. 1A to 1G show examples in which the present invention is applied to a CMOSFET.

First, as shown in FIG. 1A, an element isolation region 2 is formed in a p-type silicon substrate 1 by a known technique. Thereafter, n-type well region 3 and p-type well region 4
Is formed. The n-type well region 3 is formed, for example, by implanting p ⁺ ions at an ion implantation energy of 700 keV and a dose of 1.5 × 10 ¹³ cm ⁻² ,
s ⁺ ion implantation energy 100 keV, dose 5
It is formed by ion implantation at × 10 ¹² cm ⁻² . The p-type well region 4 is formed, for example, by implanting B ⁺ with an ion implantation energy of 300 keV and a dose of 2 × 10 ¹³ cm ⁻² , and then implanting B ⁺ with an ion implantation energy of 30 keV, for example.
V is formed by ion implantation at a dose of 6 × 10 ¹² cm ⁻² . Thereafter, a gate oxide film 5 of about 6 nm is formed by thermal oxidation, and then non-doped polycrystalline silicon 6 is deposited by about 200 nm by CVD. After that, the n-type M
The gate electrode of the OSFET and the gate electrode 7 of the p-type MOSFET are formed. Thereafter, a sidewall 8 of an oxide film having a thickness of about 80 nm is formed on the side surface of the gate electrode.

Thereafter, as shown in FIG.
After masking the region where the OSFET is to be formed with the resist 9, for example, As ⁺ 10 is ion-implanted at an energy of 30 ke.
V ions are implanted at a dose of 3 × 10 ¹⁵ cm ⁻² to form the n ⁺ -type source / drain regions 11 and simultaneously form the n ⁺ -type gate electrodes 12.

Thereafter, as shown in FIG.
After masking the region where the OSFET is to be formed with the resist 13, for example, BF ₂ ⁺ 14 is ion-implanted at an energy of 20 k.
eV, ion implantation at a dose of 3 × 10 ¹⁵ cm ⁻² and p ⁺
At the same time as forming the source / drain regions 15, a p ⁺ type gate electrode 16 is formed.

Further, as shown in FIG.
While masking the OSFET formation region with the resist 13, for example, As ₂ ⁺
ion implantation at keV and a dose of 6 × 10 ¹⁴ cm ⁻² ,
^A layer 18 containing As at a high concentration is formed on the surface of the ⁺ type source / drain region 15 and the surface of the p ⁺ type gate electrode 16. FIGS. 2A and 2B show profiles of boron and As in the n ⁺ type source / drain region 11 and the p ⁺ type source / drain region 15. 2, the concentration of the high-concentration As layer at the surface of the p ⁺ -type source / drain region 15 is about 4 × 10 ²⁰ cm ^−3, which is the same as the As concentration at the surface of the n ⁺ -type source / drain region. It turns out that it is about. Then, after the resist is removed, activation heat treatment is performed at 1000 ° C. for about 10 seconds in a nitrogen atmosphere to activate the impurities in the source / drain region and the gate electrode region.

Thereafter, except for the thickness of the titanium sputtering film, the gate electrode region and the source / drain region are made into titanium silicide by a known method as shown in the conventional example of FIGS. 4 (a) to 4 (e). I do. The outline is shown below.

First, As⁺The ion implantation energy 30
keV, dose 3 × 10¹⁴cm^-2 Ion implantation,
Amorphous layer in the source drain region and gate electrode region (Fig.
(Not shown), the gate electrode surface and the source
The native oxide film on the surface of the drain region is removed with dilute hydrofluoric acid
You. This step is the same as that shown in the conventional example. That
Thereafter, as shown in FIG. 1E, titanium having a thickness of about 50 nm is used.
19 was sputter deposited on a semiconductor substrate heated to 450 ° C.
I do. The sputtered film thickness of titanium is shown in the conventional example.
It is formed thicker than.

Thereafter, as shown in FIG. 1 (f), a first sintering is performed in a nitrogen atmosphere at 650 ° C. for about 30 seconds to silicide only the titanium in a portion in contact with silicon.
A titanium silicide 20 is formed. At this time, titanium in a portion in contact with the element isolation region 2 and the side wall 8 and a part of titanium on silicon are nitrided into titanium nitride 21.

Thereafter, as shown in FIG. 1 (g), only the titanium nitride 21 is selectively removed by etching with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. Thereafter, a second sintering is performed at 850 ° C. for 10 seconds in a nitrogen atmosphere to form a titanium silicide 22 having a lower electric resistivity than the titanium silicide 20.

Unlike the conventional example, the thickness of titanium is 50 n
Since the thickness is m, the titanium silicide film having a sufficient thickness can be formed even on the n ⁺ -type source / drain region 11 implanted at a high dose, and the layer resistance can be kept low. Also, on the p ⁺ -type source / drain region 15, the surface portion has the same A level as that of the n ⁺ -type source / drain region.
Since having s concentration, it is possible to suppress the excessive silicidation reaction, short circuit between the p ⁺ type gate electrode and the p ⁺ -type source and drain regions, and the p ⁺ -type source and drain regions and the n
There is no increase in junction leakage current between the mold well regions.

Next, a second embodiment of the present invention will be described. 3 (a) to 3 (g) show a CMOS according to the present invention.
It shows an example applied to an FET.

First, as shown in FIG. 3A, an element isolation region 52 is formed in a p-type silicon substrate 51 by a known technique. After that, an n-type well region 53 and a p-type well region 54 are formed. The n-type well region 53 is formed, for example, by implanting p ⁺ with an ion implantation energy of 700 keV,
After ion implantation at a dose of 1.5 × 10 ¹³ cm ⁻² ,
For example, As ^{+ is formed} by ion implantation at an ion implantation energy of 100 keV and a dose of 5 × 10 ¹² cm ⁻² . The p-type well region 54 is formed, for example, by implanting B ⁺ with an ion implantation energy of 300 keV and a dose of 2 × 10 ¹³ cm ^−2.
Then, for example, B ⁺ is ion-implanted with an ion implantation energy of 30 keV and a dose of 6 × 10 ¹² cm ⁻² . Thereafter, a gate oxide film 55 of about 6 nm is formed.
Is formed by thermal oxidation, non-doped polycrystalline silicon 56 is deposited to a thickness of about 200 nm by CVD. Thereafter, the gate electrode of the n-type MOSFET and the p-type MO are formed by a photolithography step and an etching step.
The gate electrode 57 of the SFET is formed. After that, a sidewall 58 having a thickness of about 80 nm made of an oxide film is formed on the side surface of the gate electrode.

Thereafter, as shown in FIG.
After masking the region where the OSFET is to be formed with the resist 59, for example, As ⁺ 60 is ion-implanted at an energy of 30 ke.
V ions are implanted at a dose of 3 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type source / drain region 61 and, at the same time, to form an n ⁺ -type gate electrode 62.

Thereafter, as shown in FIG.
After masking the OSFET formation region with a resist 63, for example, BF ₂ ⁺ 64 is ion-implanted at an energy of 20 k.
eV, ion implantation at a dose of 3 × 10 ¹⁵ cm ⁻² and p ⁺
At the same time as forming the source / drain regions 65, ap ⁺ type gate electrode 66 is formed.

Further, as shown in FIG.
While masking the OSFET formation region with the resist 63, for example, As ₂ ⁺
ion implantation at keV and a dose of 6 × 10 ¹⁴ cm ⁻² ,
^A layer 68 containing a high concentration of As is formed on the surface of the ⁺ source / drain region 65 and the surface of the p ⁺ gate electrode 66. The peak concentration of this high concentration As layer is 4 × 10 ²⁰ c
m ⁻³ , and A of the surface of the n ⁺ type source / drain region.
It is about the same as the s concentration. Then, after the resist is removed, activation heat treatment is performed at 1000 ° C. for about 10 seconds in a nitrogen atmosphere to activate the impurities in the source / drain region and the gate electrode region.

Thereafter, except for the temperature of the first sinter, the gate electrode region and the source / drain region are made of titanium silicide by a known method as shown in the conventional example of FIGS. 4 (a) to 4 (e). Become The outline is shown below.

[0034] First, ion implantation energy 30 As ⁺
After ion implantation at keV and a dose of 3 × 10 ¹⁴ cm ⁻² to form an amorphous layer (not shown) in the source / drain region and the gate electrode region, the native oxide film on the gate electrode surface and the source / drain region surface is removed. Remove with dilute hydrofluoric acid.

This step is the same as that shown in the conventional example. Thereafter, as shown in FIG. 3E, a titanium 69 having a thickness of about 30 nm is sputter deposited on the semiconductor substrate heated to 450.degree.

Thereafter, as shown in FIG. 3 (f), a first sinter is performed at 750 ° C. for about 30 seconds in a nitrogen atmosphere to silicide only the titanium in a portion in contact with silicon.
A titanium silicide 70 is formed. At this time, a portion of titanium in contact with the element isolation region 52 and the side wall 58 and a portion of titanium on silicon are nitrided into titanium nitride 71.

Thereafter, as shown in FIG. 3 (g), only the titanium nitride 71 is selectively removed by etching with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. Thereafter, a second sintering is performed at 850 ° C. for 10 seconds in a nitrogen atmosphere to form a titanium silicide 72 having a lower electric resistivity than the titanium silicide 70.

Unlike the conventional example, since the temperature of the first sinter is as high as 750 ° C., a titanium silicide film having a sufficient thickness can be formed even on the n ⁺ -type source / drain region 61 implanted at a high dose. Layer resistance can be kept low. Further, also on the p ⁺ type source / drain region 65, the surface portion has the same As concentration as the n ⁺ type source / drain region, so that an excessive silicidation reaction can be suppressed, and the p ⁺ type gate electrode and short circuit between the p ⁺ -type source and drain regions, and nor causes an increase in junction leakage current between the p ⁺ -type source and drain region and the n-type well region.

[0039]

As described above, according to the present invention, the As concentration on the n ⁺ -type source / drain region and the p ⁺ -type source / drain region are substantially the same, and the titanium silicide on the p ⁺ -type source / drain region The reaction can be suppressed to the same extent as on the n ⁺ -type source / drain region. Therefore, when the resistance of titanium silicide on the n ⁺ -type source / drain region is reduced by increasing the thickness of the titanium film and increasing the temperature of the first sinter, overheating of titanium silicide on the p-type MOSFET side, which has conventionally been a problem, has occurred. Gate by growth,
A short circuit between the source and drain and an increase in junction leak current between the p ⁺ -type source / drain region and the n-type well region can be suppressed.

[Brief description of the drawings]

FIGS. 1A to 1G are cross-sectional views showing a first embodiment of the present invention in the order of manufacturing steps.

FIGS. 2A and 2B show impurity concentration distributions of a device manufactured according to the present invention.

FIGS. 3A to 3G are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

4A to 4E are cross-sectional views showing a conventional example in the order of manufacturing steps.

FIGS. 5A and 5B are cross-sectional views showing a conventional example in the order of manufacturing steps.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type silicon substrate 2 element isolation region 3 n-type well region 4 p-type well region 5 gate oxide film 6 polycrystalline silicon 7 gate electrode 8 sidewall 9 resist 10 As ⁺ 11 n ⁺ type source / drain region 12 n ⁺ type gate Electrode 13 Resist 14 BF ₂ ⁺ 15 p ⁺ -type source / drain region 16 p ⁺ -type gate electrode 17 Layer containing As ⁺ 18 As at high concentration 19 titanium 20 titanium silicide 21 titanium nitride 22 titanium silicide 51 p-type silicon substrate 52 element isolation region 53 n-type well region 54 p-type well region 55 a gate oxide film 56 of polycrystalline silicon 57 gate electrode 58 side wall 59 resist 60 As ⁺ 61 n ⁺ -type source and drain regions 62 n ⁺ -type gate electrode 63 resist 64 BF ₂ ⁺ 65 p ⁺ type source / drain region 66 p ⁺ -type gate electrode 67 As ⁺ 68 As-rich layer 69 titanium 70 titanium silicide 71 titanium nitride 72 titanium silicide 101 p-type silicon substrate 102 element isolation region 103 n-type well region 104 gate oxide film 105 polycrystalline silicon 106 gate electrode 107 sidewall 108 n ⁺ type source / drain region 109 p ⁺ type source / drain region 110 n ⁺ type gate electrode 111 p ⁺ type gate electrode 112 amorphous silicon layer 113 titanium 114 titanium silicide 115 titanium nitride 116 titanium silicide 121 n ⁺ -type source and drain regions 122 n ⁺ -type gate electrode 123 p ⁺ -type source and drain region 124 p ⁺ -type gate electrode 125 of titanium silicide 126 titanium silicide 127 titanium silicide 128 Chitanshi Side 129 isolation regions 130 sidewall 131 titanium nitride 132 titanium silicide 133 titanium silicide 134 titanium silicide 135 titanium silicide

Claims (6)

[Claims] A step of forming an element isolation region made of an insulator in a semiconductor substrate; a step of forming a first conductivity type well region in the semiconductor substrate; and a second conductivity type well region in the semiconductor substrate. Forming a gate oxide film on the semiconductor substrate, forming a gate electrode on the gate oxide film, and forming a sidewall made of an insulator on a side surface of the gate electrode. , Second
Masking a conductive type MOSFET formation region with a first resist; and ion-implanting a first conductive type impurity to form a first conductive type source / drain region and a first conductive type gate electrode. Removing the first resist, masking the first conductive type MOSFET formation region with a second resist, and ion-implanting a second conductive type impurity to form a second conductive type impurity. Forming a source / drain region and a gate electrode of the second conductivity type;
Ion-implanting a first conductivity type impurity to form a layer containing a first conductivity type impurity on the surface portion of the source / drain region of the second conductivity type and the surface portion of the gate electrode of the second conductivity type; Removing the second resist, performing a heat treatment, the first conductivity type source / drain region, the first conductivity type gate electrode, the second conductivity type source / drain region, and the second conductivity type By silicidizing the surface of the gate electrode of
A first silicide layer and a second silicide layer in the source / drain region of the conductivity type, the gate electrode region of the first conductivity type, the source / drain region of the second conductivity type, and the gate electrode region of the second conductivity type; Third
Forming a first silicide layer and a fourth silicide layer, respectively. 2. The method according to claim 1, wherein the impurity of the first conductivity type is As. 3. The method according to claim 1, wherein the second impurity is BF ₂ . 4. The method according to claim 1, wherein the second impurity is B. 5. The impurity concentration of the first conductivity type near the surface of the source / drain region of the second conductivity type is equal to the impurity concentration of the first conductivity type near the surface of the source / drain region of the first conductivity type. 2. The method for manufacturing a semiconductor device according to claim 1, wherein 6. The first silicide layer and the second silicide layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein said silicide layer, said third silicide layer, and said fourth silicide layer have substantially the same thickness.