JP2001257343A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain short-channel effect and the inverse short-channel effect of an MISFET at the same time. SOLUTION: Ions, having polarity opposite to that of the impurity ions composing a p-type well 3, are implanted to form a first channel region 5b in the edge part of a gate electrode 7n and a second channel region 12, which gives influence only on the shallow region of an n--type semiconductor region 8. Also, the ions, having polarity opposite to that of the impurity ions composing an n-type well 4, are implanted to form a first channel region 5a in the edge part of a gate electrode 7p and a second channel region 13, which gives influence only on a shallow region of a p--type semiconductor region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a MISFET (Metal Insulator Semi).
The present invention relates to a technique effective when applied to a technique for controlling a short channel effect and an inverse short channel effect of a conductor field effect transistor.

[0002]

2. Description of the Related Art When the distance between a source and a drain is reduced due to a decrease in a channel length due to a decrease in a gate length of a MISFET, the influence of the characteristics of the source and the drain on the electric field and potential distribution in the channel portion is reduced. growing. As one of the effects, there is a short channel effect in which the threshold voltage of the MISFET rapidly decreases when the channel length becomes a certain length or less.

Conventionally, as a method of suppressing the short-channel effect, for example, a method of controlling the short-channel effect by adjusting the impurity concentrations of the channel region and the well region of the MISFET in a self-aligned manner with respect to the gate length has been adopted. Was. For such a technique for controlling the short channel effect, for example, (1) H. Kurata and T. Sugii, "Self-
Aligned Control of Threshold Voltagesin Sub-0.2μm
MOSFET's, "IEEE Trans. Electron Devices, vol. 45,
pp. 2161, 1998.

The above-mentioned document (1) discloses a technique using ion implantation at a high incident angle (threshold voltage control ion implantation) to adjust the impurity concentration in the channel region and the well region. Impurities due to threshold voltage control ion implantation are implanted from both ends of the gate electrode. When the gate length is small to some extent, the impurity concentration increases due to the superposition effect. As the impurity concentration of the channel region and the well region increases, the threshold voltage increases, and the short channel effect is suppressed.

[0005]

The prior art which suppresses the short channel effect by implanting impurities by threshold voltage control ion implantation and increasing the impurity concentration in the channel region and the well region has the following problems. Is generated.

That is, when the channel length is reduced to a certain value or less due to the decrease in the gate length, the MISFET
The reverse short channel effect occurs in which the threshold voltage increases. Further, as the channel length decreases, the short channel effect occurs continuously to the inverse short channel effect. When the amount of ions implanted into the channel region and the well region is increased to suppress the short channel effect and the impurity concentration is increased, the reverse short channel effect may appear even if the short channel effect can be suppressed. There is a trade-off relationship between the short channel effect and the inverse short channel effect, making it difficult to independently control the short channel effect and the inverse short channel effect.

An object of the present invention is to provide a technique for suppressing an inverse short channel effect under a situation where a short channel effect of a MISFET is suppressed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a source region and a drain region having an LDD structure in which a well of a first conductivity type has a semiconductor region of a second conductivity type having a high impurity concentration and a semiconductor region of a second conductivity type having a low impurity concentration. Is formed.

Further, according to the present invention, a source region and a drain region having an LDD structure in which a well of a first conductivity type has a semiconductor region of a second conductivity type having a high impurity concentration and a semiconductor region of a second conductivity type having a low impurity concentration. And a step of forming a high impurity concentration first conductivity type pocket layer in the well below the low impurity concentration semiconductor region.

Further, according to the present invention, a source region and a drain region having an LDD structure in which a well of a first conductivity type includes a semiconductor region of a second conductivity type having a high impurity concentration and a semiconductor region of a second conductivity type having a low impurity concentration. And forming a second conductivity type first semiconductor region having a lower impurity concentration than the low impurity concentration semiconductor region in the well inside the low impurity concentration semiconductor region.

Further, according to the present invention, a first conductivity type well of a MISFET includes a high conductivity second conductivity type semiconductor region and a low impurity concentration second conductivity type semiconductor region.
A source region and a drain region having a DD structure are formed;
A first conductive type pocket layer having a high impurity concentration is formed in the well below the low impurity concentration semiconductor region.

Further, according to the present invention, the first conductivity type well of the MISFET has a low impurity concentration second conductivity type semiconductor region and a low impurity concentration second conductivity type semiconductor region.
A source region and a drain region having a DD structure are formed;
A first semiconductor region of a second conductivity type having a lower impurity concentration than the low impurity concentration semiconductor region is formed in the well inside the low impurity concentration semiconductor region.

According to the present invention, by providing a pocket layer of the same conductivity type as that of the well, a decrease in the threshold voltage due to the short channel effect is prevented. By providing a second conductivity type first semiconductor region having a lower impurity concentration than the second conductivity type semiconductor region in the well inside the low impurity concentration semiconductor region,
The threshold voltage is prevented from rising due to the inverse short channel effect. Therefore, the short channel effect and the inverse short channel effect can be controlled independently.

Further, according to the present invention, the MISFE
Even when the gate length of T becomes short, the short channel effect and the reverse short channel effect are prevented, so that the fine processing of the gate electrode can be facilitated.

Further, according to the present invention, since fine processing of the gate electrode can be easily performed, the degree of integration of the semiconductor integrated circuit device can be increased, and the performance of the semiconductor integrated circuit device can be improved.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

In this embodiment, an n-channel MISFE
Complementary MOS (CMOS: Complementary Metal Oxide Semi) composed of TQn and p-channel MISFET Qp
The present invention is applied to a method of manufacturing a semiconductor integrated circuit device having a MISFET of a (conductor) type.

Hereinafter, a method of manufacturing the above-described semiconductor integrated circuit device will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, a surface of a semiconductor substrate 1 made of p-type silicon single crystal is selectively oxidized (L
After the field insulating film 2 for element isolation is formed by the OCOS method, a p-type impurity (for example, B (boron)) is doped into the p-type (first conductivity type) well formation region of the semiconductor substrate 1 by ion implantation or the like. To form a p-type well 3. Then, an n-type impurity (for example, P (phosphorus)) is doped into the n-type (second conductivity type) well formation region of the semiconductor substrate 1 by ion implantation or the like to form an n-type well 4.

Next, in a later step, an n-channel type MI
As shown in FIGS. 2A and 2B in which the vicinity of the location where the SFET Qn and the p-channel type MISFET Qp are formed is enlarged, the n-type well 4, for example, about About 3 × 10 ¹² P ions are implanted at an energy of about 450 keV to form the first channel region 5a. Similarly, about 5 × 10 ¹² B atoms are added to the p-type well 3 for about 180 k.
The first channel region 5b is formed by ion implantation at an energy of about eV.

Next, as shown in FIG. 3, a silicon oxide film having a thickness of about 3.5 nm serving as a gate insulating film 6 is deposited on the semiconductor substrate 1. Next, a film thickness of 9
A non-doped polycrystalline silicon film of about 0 nm to 100 nm is deposited by a CVD (Chemical Vapor Deposition) method. Subsequently, P (phosphorus) is added to the non-doped polycrystalline silicon film on the p-type well 3 by using a mask for ion implantation.
Is ion-implanted to form an n-type polycrystalline silicon film. Subsequently, using a mask for ion implantation, B (boron) is ion-implanted into the non-doped polycrystalline silicon film on the n-type well 4 to form a p-type polycrystalline silicon film.

Next, the silicon oxide film, the n-type polycrystalline silicon film and the p-type polycrystalline silicon film are dry-etched using the photoresist film as a mask. As a result, the gate insulating film 6 is formed, and the gate insulating film 6 of the p-type well 3 is formed.
Channel type MI made of n-type polycrystalline silicon
A gate electrode 7n of the SFET Qn is formed, and a gate electrode 7p of a p-channel type MISFET Qp made of a p-type polycrystalline silicon film is formed above the gate insulating film 6 of the n-type well 4.

Next, as shown in FIG.
Then, after removing the photoresist film used in the processing of 7p, about 2 × 10 ¹⁵ / cm ^{2 of} an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 3 at an energy of about 5 keV. Then, an n ⁻ -type semiconductor region 8 is formed in the p-type well 3 on both sides of the gate electrode 7n. Subsequently, a p-type impurity of about 1 × 10 ¹⁵ / cm ^{2 is} added to the n-type well 4.
For example, BF ₂ (boron difluoride) is ion-implanted at an energy of about 3 keV to form n on both sides of the gate electrode 7p.
A p ⁻ type semiconductor region 9 is formed in the type well 4.

Next, as shown in FIG. 5, n ^- -type n the bottom of the semiconductor region 8 ^- -type semiconductor impurity ions (e.g., As) which constitutes the region 8 and an ion having a polarity opposite of the (e.g., boron) The pocket layer 10 is formed by implantation. By adjusting the impurity ion concentration of the pocket layer 10,
It is possible to prevent the threshold voltage when the gate length of the n-channel MISFET Qn is short from being reduced by the short channel effect. In the present embodiment, the ion implantation for forming the pocket layer 10 is performed, for example, by setting the incident angle θ of the ions to about 35 ° and the energy of the ion implantation to about 15 keV, as shown in FIG. 7n is implanted from four directions (ion implantation direction 100) at a rate of about 1 × 10 ¹³ / cm ² . Similarly, p ^-
An ion (eg, P) having a polarity opposite to that of impurity ions (eg, BF ₂ ) forming p ⁻ type semiconductor region 9 is implanted below type semiconductor region 9 to form pocket layer 11. In the present embodiment, the ion implantation for forming the pocket layer 11 is performed, for example, by setting the incident angle θ of the ion to about 3
About 5 ° and the ion implantation energy is about 45 keV
About 1 × 1 with respect to the gate electrode 7p from four directions.
Inject about 0 ¹³ pieces / cm ² .

Next, as shown in FIG. 7, ions (eg, P) having a polarity opposite to that of the impurity ions (eg, B) forming the p-type well 3 are implanted into the p-type well 3 by ion implantation. By implantation, a second channel region (first semiconductor region) 12 is formed. The energy of ion implantation when forming the second channel region 12 is smaller than the energy of ion implantation when forming the pocket layer 10. In addition, the incident angle θ of ion implantation when forming the second channel region 12 is larger than the incident angle θ of ion implantation when forming the pocket layer 10. Therefore, the impurity ions forming the second channel region 12 do not reach the deep part of the p-type well 3, the peak of the impurity concentration distribution is formed shallower than that of the pocket layer 10, and the second channel region 12 It is formed so as to affect only the first channel region 5b at the end of the gate electrode 7n and the shallow region of the n ⁻ type semiconductor region 8. Also, the second channel region 12
Is smaller than the ion implantation amount when the pocket layer 10 is formed, the second channel region 12 is an n ^- type semiconductor region having a lower impurity concentration than the n ⁻ -type semiconductor region 8. .

Further, since ion implantation for forming the second channel region 12 is counter doping with respect to the first channel region 5a, the Fermi potential of the first channel region 5b at the end of the gate electrode 7n becomes intrinsic. Get closer to semiconductors. Therefore, the carrier density at the end of the gate electrode 7n increases. The region where the carrier density increases is a range of a certain distance from the end of the gate electrode 7n. In the present embodiment, the range is about 0.03 μm to 0.05 μm from the end of the gate electrode 7n. FIG.
When the gate length of the gate electrode 7n is sufficiently long with respect to the region where the carrier density increases as shown in (a), the carrier amount of the entire gate electrode 7n is large, and the effect of the increase of the carrier density at the end of the gate electrode 7n. Does not appear as a change in threshold voltage (FIG. 9). FIG. 8B
As shown in (2), as the gate length becomes shorter, the amount of increase in the carrier density at the end of the gate electrode 7n becomes larger than the amount of carriers in the entire gate electrode 7n. The threshold voltage decreases. As shown in FIG. 8C, when the gate length is short and the two second channel regions 12 overlap,
The amount of increase in carrier density in the region where the second channel region 12 overlaps is even greater than the amount of increase in carrier density at the end of the gate electrode 7n. by the way,
When the above-described pocket layer 10 is provided, the threshold voltage increases due to the inverse short channel effect before the threshold voltage decreases due to the short channel effect. In the semiconductor integrated circuit device of the present embodiment, the decrease in the threshold voltage due to the increase in the amount of carriers in the entire gate electrode 7n is offset by the increase in the threshold voltage due to the inverse short channel effect. It is possible to prevent the threshold voltage from increasing due to the channel effect. Thus, the provision of the pocket layer 10 prevents a decrease in threshold voltage due to the short channel effect, and the provision of the second channel region 12 prevents an increase in threshold voltage due to the reverse short channel effect. And the inverse short channel effect can be controlled independently. This is particularly effective when the gate length is about 0.2 μm or less. That is, even when MISFETs having different gate lengths are mixed on the semiconductor substrate 1, the threshold voltages of the MISFETs can be made uniform. Further, the short channel effect and the inverse short channel effect can be controlled independently, so that the gate electrode 7n
It is possible to reduce the variation in the performance of the semiconductor integrated circuit device due to the variation in the processing and the occurrence rate of the operation failure.
Further, even when the gate length is shortened, the short channel effect and the reverse short channel effect can be prevented, so that it is easy to finely process the gate electrode 7n. As a result, the degree of integration of the semiconductor integrated circuit device can be increased, and the performance of the semiconductor integrated circuit device can be improved.

The amount of impurity ions implanted to form the second channel region 12 is reduced by the threshold voltage due to the increase in the amount of carriers in the entire gate electrode 7n and the threshold voltage due to the inverse short channel effect. In this embodiment, for example, the incident angle θ of the impurity ions is set to about 45 ° to 60 °, preferably about 60 °, and the energy of the impurity ion implantation is set to about 60 °. At about 30 keV, about 3 × 10 ¹² ions / cm ² are implanted into the gate electrode 7n from four directions. Similarly, an ion (for example, B) having a polarity opposite to that of the impurity ion (for example, P) constituting the n-type well 4 is implanted into the n-type well 4 by ion implantation, and the second channel region (for the first semiconductor). Region 13 is formed. In the present embodiment, for the same purpose as in the case of the n-channel type MIFET, the impurity ion implantation for forming the second channel region 13 is performed, for example, by setting the incident angle θ of the impurity ion to about 6
About 0 ° and the energy of impurity ion implantation is about 10
At about keV, about 3 × 10 ¹² / cm ^{2 is} implanted into the gate electrode 7p from four directions.

Next, as shown in FIG.
(Omitted in FIG. 10) A silicon oxide film having a thickness of about 100 nm is deposited thereon by CVD, and this silicon oxide film is anisotropically etched by reactive ion etching (RIE), thereby forming an n-channel. Type MISFET Qn
Gate electrode 7n and p-channel type MISFET Qp
A sidewall spacer 14 is formed on each side wall of the gate electrode 7p.

Next, as shown in FIG.
Is implanted with an n-type impurity such as As to form an n ⁺ -type semiconductor region 15 (source and drain) of the n-channel MISFET, and a p-type impurity such as BF ₂ is ion-implanted into the n-type well 4 to form a p-type impurity. The p ⁺ type semiconductor region 16 (source, drain) of the channel type MISFET is formed. At this time, the ion implantation of the n-type impurity into the p-type well 3 is performed by implanting the n-type impurity of about 2 × 10 ¹⁵ / cm ^{2 with} the energy of the impurity ion implantation of about 40 keV. The ion implantation of the p-type impurity into the n-type well 4 is performed by implanting p-type impurities of about 2 × 10 ¹⁵ / cm ^{2 at} an energy of about 25 keV. Thereby, the LDD (Lightly Doped) is provided for each of the n-channel MISFET and the p-channel MISFET.
ped Drain) structure source and drain regions are formed,
n-channel MISFET Qn and p-channel MI
The SFET Qp is completed.

Next, as shown in FIG. 12, a titanium film is deposited on the entire surface of the semiconductor substrate 1 by using a sputtering method. Subsequently, by annealing the semiconductor substrate 1 in a nitrogen gas atmosphere at a temperature of about 650 to 700 ° C., the interface between the gate electrodes 7 n and 7 p and the titanium film,
And source and drain regions (n ⁺ semiconductor region 15, p ⁺
A silicidation reaction is caused at the interface between the semiconductor region 16) and the titanium film to form a titanium silicide film 17. In the drawings after FIG. 12, illustration of the first channel regions 5a and 5b, the pocket layers 10 and 11, and the second channel regions 12 and 13 is omitted.

Next, as shown in FIG.
An insulating film 18 is formed by depositing a silicon oxide film thereon by the CVD method and flattening the surface thereof by the CMP method. Further, a connection hole 19 is formed in the insulating film 18 by using a photolithography technique.

Subsequently, the insulating film 1 including the inside of the connection hole 19 is formed.
8 is sputter-etched to remove a natural oxide film formed on the surface of the insulating film 18 including the inside of the connection hole 19. By this sputter etching, the electrical resistance between the plug 22 formed inside the connection hole 19 in a later step and the titanium silicide film 17 at the bottom of the connection hole 19 is reduced.

Subsequently, the insulating film 1 including the inside of the connection hole 19 is formed.
On the surface of the barrier layer 8, a barrier conductor film 20 having a thickness of about 50 nm, such as titanium nitride, is deposited by a sputtering method. Subsequently, the connection hole 19 is formed in the surface of the barrier conductor film 20.
A conductive film 21 made of, for example, tungsten or the like is buried therein by CVD. Subsequently, the barrier conductor film 20 and the conductive film 21 on the insulating film 18 other than the connection holes 19 are removed by, for example, a CMP method to remove the plug 22.
To form

Next, as shown in FIG.
A conductive film 23 such as titanium nitride is deposited on the entire surface by sputtering. The conductive film 23 prevents atoms constituting the conductive film 24 described later from diffusing into the plug 22 by electromigration or the like,
It has a function to prevent disconnection failure. Then, the conductive film 2
3, a conductive film 24 made of, for example, aluminum.
Is deposited. Subsequently, a conductive film 25 such as titanium nitride is deposited on the surface of the conductive film 24. This conductive film 25 is made of conductive films 23, 24 and 2
5 has a function of preventing irregular reflection of light when patterning 5 by a photolithography process. The deposition of the conductive films 24 and 25 is performed by a sputtering method.

Subsequently, the conductive films 23, 24, and 25 are processed by using a dry etching technique to form the wiring 26, and the semiconductor integrated circuit device of the present embodiment is manufactured. Note that a wiring may be further formed in multiple layers above the wiring 26 by a process similar to the process described with reference to FIGS.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

The present invention is not limited to application to CMOS,
Application to a memory or the like is also possible.

[0040]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, by independently controlling the decrease in the threshold voltage due to the short channel effect and the increase in the threshold voltage due to the inverse short channel effect, variations in the performance and operation of the semiconductor integrated circuit device Defects can be reduced. (2) According to the present invention, even when the gate length is shortened, the short channel effect and the reverse short channel effect can be prevented, and the fine processing of the gate electrode can be facilitated. (3) According to the present invention, since fine processing of the gate electrode can be easily performed, the degree of integration of the semiconductor integrated circuit device can be increased, and the performance of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

FIG. 6 is a main part plan view for explaining an ion implantation direction for forming a pocket layer.

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

FIG. 8 is a cross-sectional view of a principal part explaining channel regions at various gate lengths.

FIG. 9 is a graph illustrating a relationship between a gate length of a MISFET and a threshold voltage.

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;

12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 field oxide film 3 p-type well 4 n-type well 5a first channel region 5b first channel region 6 gate insulating film 7n gate electrode 7p gate electrode 8 n ^- type semiconductor region 9 p ^- type semiconductor region 10 pocket layer Reference Signs List 11 pocket layer 12 second channel region (first semiconductor region) 13 second channel region (first semiconductor region) 14 sidewall spacer 15 n ⁺ type semiconductor region 16 p ⁺ type semiconductor region 17 titanium silicide film 18 insulating film 19 connection Hole 20 barrier conductive film 21 conductive film 22 plug 23 conductive film 24 conductive film 25 conductive film 100 impurity ion implantation direction Qn n-channel MISFET Qp p-channel MISFET

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a MISFET having a pocket layer is formed on a main surface of a semiconductor substrate, wherein a well of a first conductivity type of the MISFET has a semiconductor region of a second conductivity type having a high impurity concentration. And low impurity concentration second
A source region and a drain region having an LDD structure including a semiconductor region of a conductivity type are formed; a pocket layer of a first conductivity type having a high impurity concentration is formed in the well below the semiconductor region having a low impurity concentration; The second well having the low impurity concentration is provided in the well inside the semiconductor region having the low impurity concentration.
A semiconductor integrated circuit device, wherein a first semiconductor region of a second conductivity type having a lower impurity concentration than a semiconductor region of a conductivity type is formed.