JPH04127538A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To relax the concentration of an electric field on the end part, on which the electric field is easily concentrated and which is located on the side of a drain, of a gate electrode by making thick a gate oxide film at the end part, to lessen a change with time in a MOSFET and to improve the reliability of the MOSFET by a method wherein in the MOSFET, the gate electrode is formed ranging from the upper part of a gate insulating film to the upper part of a silicon dioxide film thicker than the gate oxide film. CONSTITUTION:A silicon dioxide film (a first insulating film) 2 of a thickness of 600 to 1000nm, P-type diffused layers 3 and a silicon dioxide film (a second insulating film) 9 of a thickness of 35 to 70nm are formed at an element isolation region of a P-type silicon substrate 1. Then, after an opening 10 is formed, a gate insulating film 4 of a thickness of 10 to 20nm is formed in the opening 10 by performing a thermal oxidation. Then, a gate electrode 5 of a width (l1) larger than the width (l2) of the opening 10 is formed. After that, N-type diffused layers 6 and 8 are formed in a self-alignment manner using the film 2 and the electrode 5 as masks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a highly reliable MOSFET even when the pattern is miniaturized.

[Conventional technology]

LDD by conventional technology (upper 1ghtly doped
A MOSFET having a drain) structure will be explained with reference to FIG.

A thick silicon dioxide film 2 and a P-type diffusion layer 3 serving as a channel stopper are formed in an element isolation region on a P-type silicon substrate 1 by selective oxidation.

A gate insulating film 4 is formed in the element forming region, and a gate electrode 5 made of polysilicon or a stack of a polysilicon layer and a silicide layer containing a high melting point metal such as tungsten is formed thereon.

An N-type diffusion layer 6 with a low impurity concentration is formed in a self-aligned manner using the gate electrode 5 and the thick silicon dioxide film 2 as a mask.

The N-type diffusion layer 6 with a low impurity concentration is formed by, for example, phosphorus with an acceleration energy of 50 to 80 keV and an implantation amount (dose) of 2.0×10'.
It is formed by implanting 3 to 1.0 x 10'4/Cm2 ions.

Further, a side wall 7 made of a silicon dioxide film is formed on the gate electrode 5 by, for example, a CVD method.

An N-type diffusion layer 8 with a high impurity concentration is formed in a self-aligned manner using the gate electrode 5, side walls 7, and thick silicon dioxide film 2 as masks.

For example, the N-type diffusion layer 8 with a high impurity concentration accelerates arsenic with an energy of 50 to 80 keV1 and a dose of 3.0XIO.
It is formed by implanting ions of '5 to 1.0XIO16/cm2.

In order to reduce the contact resistance with the metal wiring layer formed in the subsequent process, 5.0
An impurity concentration of I9/Cm3 or higher is required.

Furthermore, the N-type diffusion layer 6 with a low impurity concentration has a thickness of 5×10” to 1.OX 10 for the purpose of preventing concentration of electric field between the gate electrode 5 and the N-type diffusion layers 6 and 8 at the drain side end.
It is necessary to set the impurity concentration to ”/cm−3.

Therefore, for the purpose of high integration, the gate length should be set to 1.2μ.
MO with a gate insulating film thickness of 250 Å or less
In the SFET, double N-type diffusion layers 6 and 8 with different impurity concentrations were used as source-drain diffusion layers.

[Problem to be solved by the invention]

Such MOSFETs have the following problems.

First, if we try to keep the electric field strength at the conventional level by thinning the gate insulating film and shortening the gate length for the purpose of higher speed and higher integration, the impurity concentration of the N-type diffusion layer, which has a low impurity concentration, will decrease. It is necessary to do so. As a result, the drain current per unit channel width of the transistor body increases, while the parasitic resistance associated with the source-drain diffusion layer increases. Therefore, in the transistor as a whole including the transistor body and parasitic resistance components, the drain current per unit channel width can only be increased by a small amount compared to the degree of reduction.

Second, the pattern accuracy of the gate length, which causes variations in the characteristics of semiconductor devices, is determined only by the device capabilities of the exposure device and the gate electrode etching device. Therefore, in the mass production process, the manufacturing standard for gate length is 0.8±0
．． The limit is 15 μm. The actual gate length is 0.95μ
The ratio of the delay time of the logic circuit when it is 065 μm is approximately 1.5 times that of when it is 065 μm, and the variation in delay time under the operating environment of semiconductor logic circuits such as power supply voltage fluctuations and temperature fluctuations is suppressed to 3 times or less. This is a guideline. Further, as a cause of variation in gate length, for example, partial shedding of crystal grains at crystal grain boundaries of polysilicon, which is a gate electrode material, can be considered. The only solution to this problem is to make the crystal grains finer.

[Means to solve the problem]

A semiconductor device of the present invention includes a first insulating film selectively formed in an element isolation region of a first conductivity type semiconductor substrate, and a gate insulating film formed on a channel forming region in an element region of the semiconductor substrate. , a second insulating film that is thicker than the gate oxide film and thinner than the first insulating film and selectively formed outside the channel forming region in the element region; and a second insulating film that is formed on the gate oxide film. It has a gate electrode formed thereover and a second conductivity type source-drain diffusion layer formed under the second insulating film.

[Example] Regarding the first example of the present invention, FIGS. 1(a) to (d)
Explain with reference to.

Firstly, as shown in FIG.
A silicon dioxide film (first insulating film) 2 of 1000 nm is formed.

Next, boron ions are implanted at an acceleration energy of 70 to 100 keV1 (dose) of 1.0XIO13/cm2, and then 2 to 4
By performing thermal oxidation for a period of time, a P-type diffusion layer 3 is formed directly under the silicon dioxide film 2 in a self-aligned manner.

Next, a silicon dioxide film (second insulating film) with a thickness of 35 to 70 nm is formed on the element region of the P-type silicon substrate 1 by thermal oxidation.
form 9.

Next, as shown in FIG. 1(b), an opening 10 is formed in the silicon dioxide film 9 in a region where a channel is to be formed by photolithography, and then thermal oxidation is performed to form an opening 10.
A gate insulating film 4 having a thickness of 10 to 20 nm is formed thereon.

Next, as shown in FIG. 1C, a phosphorous-doped polysilicon layer is deposited and then selectively etched by photolithography to form a gate electrode 5.

At this time, a polysilicon layer with a thickness of 300 to 450 nm is deposited by low pressure CVD method, and phosphorus is thermally diffused at 820 to 950° C., so that the layer resistance is 10 to 40 Ω/hole.

Width of gate electrode 5! 1 is the width of opening 10! It is set to be larger than 2.

Therefore, the gate electrode 5 is formed from the gate insulating film 4 to the silicon dioxide film 9. Here, it corresponds to the junction depth of the source-drain diffusion layer 6 formed in the subsequent process! t f2 = 800 nm.

Next, as shown in FIG. 1(d), a silicon dioxide film 2
Then, N-type diffusion layers 6 and 8 are formed in a self-aligned manner using gate electrode 5 as a mask.

The N-type diffusion layers 6 and 8 accelerate phosphorus with energy of 50 to 80 ke.
V, implantation amount (dose)2. OX 10" ~ 1.0XI
O”/cm2 and arsenic acceleration energy 50-100
keV1 injection large amount (dose) 3゜0×10'5~1.0X
It is formed by implanting IO"/cm2 ions and then heat-treating them at 950° C. in a nitrogen atmosphere. Due to the difference in diffusion coefficient between phosphorus and arsenic, a diffusion layer 6 with a low impurity concentration and a deep junction depth due to phosphorus, A double diffusion layer is formed with the diffusion layer 8 made of arsenic and having a high impurity concentration and a shallow junction depth. , the junction depth is set to 500 nm.Also, the thickness of the silicon dioxide film 9 is set to 15 to 30 nm so that impurities can be sufficiently ion-implanted into the P-type silicon substrate 1.
It has been reduced to m.

Next, regarding the second embodiment of the present invention, FIGS.
This will be explained with reference to (d).

First, as shown in FIG. 2(a), a silicon dioxide film 2 and a P-type diffusion layer 3 are formed in an element isolation region of a P-type silicon substrate 1. Next, a silicon dioxide film 11 with a thickness of 5 to 10 nm is formed on the element region by thermal oxidation, and an impurity layer 12 of 30 to 50 nm thick made of phosphorus-doped silicon dioxide or polysilicon is deposited on the entire surface.

Next, as shown in FIG. 2(b), the impurity layer 12 on the channel formation region is selectively removed by photolithography to form an opening 10. Next, by thermal oxidation at a temperature of 950 to 1050° C., phosphorus is diffused from the impurity layer 12 into the P-type silicon substrate 1 to form an N-type diffusion layer 6 with a low impurity concentration. When the impurity layer 12 is a polysilicon layer,
This thermal oxidation converts it into a silicon dioxide layer 9.

Next, as shown in FIG. 2C, the entire surface is etched to expose the P-type silicon substrate 1 in the channel formation region, and then thermally oxidized to form the gate insulating film 4.

Next, a gate electrode 5 is formed from the gate insulating film 4 to the silicon dioxide film 9.

Next, as shown in FIG. 2(d), a silicon dioxide film 2
By ion-implanting arsenic using the gate electrode 5 as a mask, an N-type diffusion layer 8 with a high impurity concentration is formed in a self-aligned manner.

Unlike the first embodiment, the second embodiment is characterized in that the N-type diffusion layer 6 with a low impurity concentration can be formed in a self-aligned manner with respect to the opening 10.

Although the N-channel MO8FET has been described above, similar effects can be obtained even when applied to a P-channel MO8FET.

〔Effect of the invention〕

In the MOSFET of the present invention, a gate electrode is formed from the gate insulating film to the silicon dioxide film, which is thicker than the gate oxide film.

At the drain side end of the gate electrode, where electric fields tend to concentrate, the gate oxide film is thicker, which alleviates the electric field concentration.
This has the effect of improving reliability by reducing changes in the MOSFET over time.

Furthermore, the parasitic capacitance formed between the sheet electrode and the source-drain diffusion layer can be reduced, making it possible to increase the speed of circuit operation.

Furthermore, the gate length, which was conventionally determined by the width of the gate electrode, can now be determined by the width of the opening in the present invention, which has the effect of eliminating manufacturing variations caused by the gate electrode material.

[Brief explanation of the drawing]

1(a) to (d) are cross-sectional views showing a first embodiment of the present invention, FIGS. 2(a) to (d) are cross-sectional views showing a second embodiment of the present invention, and FIG. The figure shows an MO of LDD structure according to the conventional technology.
FIG. 3 is a cross-sectional view showing an element portion of an SFET. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Silicon dioxide film (first insulating film), 3... P-type diffusion layer, 4... Gate insulating film, 5... Gate electrode, 6...・N-type diffusion layer,
7... Side wall, 8... N-type diffusion layer, 9... Silicon dioxide film, 10... Opening, 11... Silicon dioxide film, 12... Impurity layer.

Claims (1)

[Claims] 1. A first insulating film selectively formed in an element isolation region of a first conductivity type semiconductor substrate, and a gate insulating film formed on a channel forming region in the element region of the semiconductor substrate. a second insulating film that is thicker than the gate oxide film and thinner than the first insulating film selectively formed outside the channel forming region in the element region; A semiconductor device comprising: a gate electrode formed over an insulating film; and a second conductivity type source-drain diffusion layer formed under the second insulating film. 2. Selectively forming a first insulating film in an element isolation region on a semiconductor substrate of one conductivity type, and forming a second insulating film thinner than the first insulating film in a region where an element is to be formed on the semiconductor substrate. selectively removing the second insulating film on the channel forming region; forming a gate insulating film thinner than the second insulating film in the channel forming region; and removing the second insulating film from above the gate insulating film. Manufacturing a semiconductor device comprising the steps of selectively forming a gate electrode over a second insulating film, and forming a second conductivity type source-drain diffusion layer under the second insulating film. Method.