JP3038857B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a MOSFET with high reliability even when a pattern is miniaturized.

[Conventional technology]

The MOSFET of the prior art LDD by (l ightly d oped d rain) structure will be described with reference to Figure 3.

In an element isolation region on a P-type silicon substrate 1, a thick silicon dioxide film 2 formed by a selective oxidation method and a P-type diffusion layer 3 serving as a channel stopper are formed.

A gate insulating film 4 is formed in the element formation region, and a gate electrode 5 made of polysilicon or a laminate of a polysilicon layer and a silicide layer containing a high melting point metal such as tungsten is formed thereon.

Using gate electrode 5 and thick silicon dioxide film 2 as a mask, low impurity concentration N-type diffusion layer 6 is formed in a self-aligned manner.

The N-type diffusion layer 6 having a low impurity concentration is, for example, phosphorous having an acceleration energy of 50 to 80 keV and a dose (dose) of 2.0 × 10 ^{13 to} 1.0 × 10 5.
It is formed by ion implantation of ¹⁴ / cm ² .

Further, a side wall 7 made of a silicon dioxide film is formed on the gate electrode 5 by, for example, a CVD method.

An N-type diffusion layer 8 having a high impurity concentration is formed in a self-aligned manner using the gate electrode 5, the side wall 7, and the thick silicon dioxide film 2 as a mask.

The N-type diffusion layer 8 having a high impurity concentration is, for example, arsenic with an acceleration energy of 50 to 80 keV and an implantation dose (dose) of 3.0 × 10 ^{15 to} 1.0 × 1.
It is formed by ion implantation of 0 ¹⁶ / cm ² .

In order to reduce contact resistance with a metal wiring layer formed in a subsequent process, 5.0 × 10 ¹⁹ /
An impurity concentration of cm ³ or more is required.

The N-type diffusion layer 6 having a low impurity concentration has a concentration of 5 × 10 ^{17 to} 1.0 × 10 ¹⁹ /1.0 for preventing concentration of an electric field between the gate electrode 5 and the N-type diffusion layers 6 and 8 at the end on the drain side. It is necessary to have an impurity concentration of cm ^-3 .

Therefore, for the purpose of high integration, the gate length is set to 1.2μ.
m and MOSFET with gate insulating film thickness of 250 mm or less
In this case, double N-type diffusion layers 6 and 8 having different impurity concentrations are applied to the source-drain diffusion layers.

[Problems to be solved by the invention]

 Such a MOSFET has the following problems.

First, if the gate insulating film is made thinner, the gate length is shortened, and the electric field strength is maintained in the conventional state for the purpose of high speed and high integration, the impurity concentration of the low impurity concentration N-type diffusion layer is reduced. Need to be done. As a result, the drain current per unit channel width of the transistor body increases, while the parasitic resistance associated with the source-drain diffusion layers increases. Therefore, in the transistor as a whole including the transistor body and the parasitic resistance component, the drain current per unit channel width can obtain only a small increase in current as compared with the degree of reduction.

Second, the pattern accuracy of the gate length that causes the characteristic variation of the semiconductor device is determined only by the device capabilities of the exposure device and the gate electrode etching device. Therefore, in the mass production process, the manufacturing standard of the gate length is 0.8 ± 0.1
5 μm is the limit. Actually, the ratio of the delay time of the logic circuit when the gate length is 0.95 μm and 0.65 μm is about 1.5.
This is a measure to suppress the variation of the delay time under the operating environment of the semiconductor logic circuit such as the power supply voltage fluctuation and the temperature fluctuation to three times or less. Further, as a factor of variation of the gate length, for example, partial dropout of crystal grains at a crystal grain boundary of polysilicon serving as a gate electrode material can be considered. There is no countermeasure other than miniaturization of the crystal grains.

[Means for solving the problem]

In the method of manufacturing a semiconductor device according to the present invention, a first insulating film is selectively formed in an element isolation region on a semiconductor substrate of one conductivity type, and then the first insulating film is formed in a region where an element is to be formed on the semiconductor substrate. Forming a thin third insulating film, subsequently depositing an impurity-containing film containing impurities of the second conductivity type on the third insulating film, and then depositing an impurity-containing film on the channel formation region of the element formation planned region; Selectively removing the impurity-containing film,
Subsequently, a heat treatment is performed on the one-conductivity-type semiconductor substrate to diffuse impurities of the impurity-containing film through the third insulating film into the region where the element is to be formed, thereby forming a second conductivity-type source-drain diffusion layer. Subsequently, the impurity-containing film and the third insulating film are removed to expose the surface of the element formation planned region, and then the surface of the element formation planned region is oxidized to cover the source-drain diffusion layer. Forming a gate insulating film thinner than the fourth insulating film on the fourth insulating film and the channel formation region, and finally covering the gate insulating film on the gate insulating film to form the fourth insulating film; It is characterized in that a gate electrode extending over a film is formed.

Before describing the embodiments of the present invention, the related art of the present invention will be described with reference to FIGS. 1 (a) to 1 (d).

First, as shown in FIG. 1A, the element isolation region of the P-type silicon substrate 1 is formed to a thickness of 600 to 100 using a selective oxidation method.
A 0 nm silicon dioxide film (first insulating film) 2 is formed.

Next, boron is implanted with an acceleration energy of 70 to 100 keV and an implantation dose (dose) of 1.0 × 10 ¹³ / cm ^2.
° C., by oxidizing 2-4 hours heat in H ₂ -O ₂ atmosphere,
P-type diffusion layer 3 self-aligned directly under silicon dioxide film 2
To form

Next, a silicon dioxide film (second insulating film) 9 having a thickness of 35 to 70 nm is formed in the element region of the P-type silicon substrate 1 by thermal oxidation.

Next, as shown in FIG. 1B, an opening 10 is formed in the silicon dioxide film 9 in a region where a channel is to be formed by photolithography, and then a gate insulating film having a thickness of 10 to 20 nm is formed in the opening 10 by thermal oxidation. The film 4 is formed.

Next, as shown in FIG. 1C, a phosphorus-doped polysilicon layer is deposited, and then selectively etched by photolithography to form a gate electrode 5.

At this time, a polysilicon layer having a thickness of 300 to 450 nm is deposited by a low pressure CVD method, and phosphorus is thermally diffused at 820 to 950 ° C. to form a layer resistance of 10 to 40 Ω / □.

The width l ₁ of the gate electrode 5 is set to be larger than the width l _{2 of the} opening 10.

Therefore, gate electrode 5 is formed over gate insulating film 4 and silicon dioxide film 9. Here, l ₁ to l ₂ = 600 nm is set corresponding to the junction depth of the source-drain diffusion layer 6 formed in the subsequent step.

Next, as shown in FIG. 1D, N-type diffusion layers 6 and 8 are formed in a self-aligned manner using the silicon dioxide film 2 and the gate electrode 5 as a mask.

The N-type diffusion layers 6 and 8 are formed by accelerating phosphorus at an acceleration energy of 50 to 80 keV and implanting dose (dose) of 2.0 × 10 ^{13 to} 1.0 × 10 ¹⁴ / cm ² and arsenic at an accelerating energy of 50 to 100 keV and implanting dose (dose) of 3.0 × 10 4. ^Fifteen
It is formed by implanting ions of about 1.0 × 10 ¹⁶ / cm ² and then performing heat treatment in a nitrogen atmosphere at 950 ° C. Due to the difference between the diffusion coefficients of phosphorus and arsenic, a double diffusion layer of a diffusion layer 6 with a low impurity concentration of phosphorus and a deep junction depth and a diffusion layer 8 of a high impurity concentration of arsenic and a shallow junction depth are formed. Have been. Here, the junction depth of the N-type diffusion layer 6 made of phosphorus is set to 500 nm so that the junction end reaches the vicinity immediately below the opening 10. The thickness of the silicon dioxide film 9 is reduced to 15 to 30 nm so that impurities can be sufficiently implanted into the P-type silicon substrate 1.

〔Example〕

Next, an embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 2A, a silicon dioxide film 2 and a P-type diffusion layer 3 are formed in an element isolation region of a P-type silicon substrate 1. Next, a silicon dioxide film 11 having a thickness of 5 to 10 nm is formed on the element region by thermal oxidation, and an impurity layer 12 having a thickness of 30 to 50 nm made of phosphorus-doped silicon dioxide or polysilicon is deposited on the entire surface.

Next, as shown in FIG. 2 (b), the opening 10 is formed by selectively removing the impurity layer 12 on the channel formation region by photolithography. Next, phosphorus is diffused from the impurity layer 12 to the P-type silicon substrate 1 by thermal oxidation at a temperature of 950 to 1050 ° C. to form an N-type diffusion layer 6 having a low impurity concentration. When the impurity layer 12 is a polysilicon layer, it is converted into the silicon dioxide layer 9 by this thermal oxidation.

Next, as shown in FIG. 2 (c), the entire surface is etched to expose the P-type silicon substrate 1 in the channel formation region and then thermally oxidized to form the gate insulating film 4. Next, a gate electrode 5 is formed from the gate insulating film 4 to the silicon dioxide film 9.

Next, as shown in FIG. 2 (d), arsenic is ion-implanted using the silicon dioxide film 2 and the gate electrode 5 as a mask to form a self-aligned high impurity concentration N-type
To form

Unlike the related art of the present invention, this embodiment is characterized in that the N-type diffusion layer 6 having a low impurity concentration can be formed in a self-aligned manner with respect to the opening 10.

Although the N-channel MOSFET has been described above, a similar effect can be obtained by applying the present invention to a P-channel MOSFET.

〔The invention's effect〕

In the MOSFET of the present invention, a gate electrode is formed from over the gate insulating film to over the silicon dioxide film thicker than the gate oxide film.

At the drain-side end of the gate electrode where the electric field tends to concentrate, the thicker gate oxide film alleviates the concentration of the electric field and reduces the change with time of the MOSFET, thereby improving the reliability.

Further, the parasitic capacitance formed between the gate electrode and the source-drain diffusion layer can be reduced, and the circuit operation can be speeded up.

In the present invention, the gate length, which has conventionally been determined by the width of the gate electrode, can now be determined by the width of the opening, and there is an effect that manufacturing variations due to the gate electrode material can be eliminated.

[Brief description of the drawings]

1 (a) to 1 (d) are cross-sectional views showing the related art of the present invention, FIGS. 2 (a) to 2 (d) are cross-sectional views showing an embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view showing an element portion of a MOSFET having a structure. Reference Signs List 1 ... P-type silicon substrate, 2 ... Silicon dioxide film (first insulating film), 3 ... P-type diffusion layer, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... N-type diffusion layer , 7 ... sidewall, 8 ... N-type diffusion layer, 9 ... silicon dioxide film, 10 ...
... opening, 11 ... silicon dioxide film, 12 ... impurity layer.

Claims (1)

(57) [Claims] A first insulating film is selectively formed in an element isolation region on a semiconductor substrate of one conductivity type, and a third insulating film thinner than the first insulating film is formed in a region where an element is to be formed on the semiconductor substrate. Forming a film, subsequently depositing an impurity-containing film containing an impurity of the second conductivity type on the third insulating film, and subsequently, the impurity-containing film located on a channel formation region of the element formation planned region Is selectively removed, and then the one-conductivity-type semiconductor substrate is subjected to a heat treatment to diffuse the impurities of the impurity-containing film through the third insulating film into the region where the element is to be formed. Forming a drain diffusion layer, subsequently removing the impurity-containing film and the third insulating film to expose the surface of the element formation planned region, and subsequently oxidizing the surface of the element formation region to form the source formation region; A fourth layer on the drain diffusion layer; Forming a gate insulating film thinner than the fourth insulating film on the insulating film and the channel forming region, and finally covering the gate insulating film on the gate insulating film and on the fourth insulating film; Forming a gate electrode that also extends.