JPS6126234B2 - - Google Patents
Info
- Publication number
- JPS6126234B2 JPS6126234B2 JP53025564A JP2556478A JPS6126234B2 JP S6126234 B2 JPS6126234 B2 JP S6126234B2 JP 53025564 A JP53025564 A JP 53025564A JP 2556478 A JP2556478 A JP 2556478A JP S6126234 B2 JPS6126234 B2 JP S6126234B2
- Authority
- JP
- Japan
- Prior art keywords
- recess
- oxidation
- film pattern
- semiconductor substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 37
- 235000012239 silicon dioxide Nutrition 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000005468 ion implantation Methods 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Weting (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は絶縁ゲート型半導体装置の製造方法に
関し、相互コンダクタンスが大きく、且つドレー
ン耐圧特性の良い、たとえばMOS型電界効果ト
ランジスタ（以下MOSFETと略す）を提供する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate semiconductor device, and provides, for example, a MOS field effect transistor (hereinafter abbreviated as MOSFET) with large mutual conductance and good drain breakdown characteristics. .
従来より、MOSFETでは相互コンダクタンス
を増加させる方法として、チヤンネル長を短くす
る方法がある。しかしながら、通常のMOSFET
ではチヤンネル長を短くしていくと、第１図に示
すように、ソース、ドレイン電極１，２間に電圧
を印加した場合シリコン基板３とドレイン拡散層
４の界面では空乏層が破線５のように広がりこの
空乏層がソース拡散層６に到達してしまいパンチ
スルー現象を生じて、MOSFETが正常に動作し
なくなる欠点があつた。この場合、実際の空乏層
の広がりは、ゲート酸化膜７上のゲート電極８の
効果によりシリコン基板表面では少く、ある深さ
においては広がつている。 Conventionally, one way to increase mutual conductance in MOSFETs is to shorten the channel length. However, normal MOSFET
Now, as the channel length is shortened, as shown in FIG. 1, when a voltage is applied between the source and drain electrodes 1 and 2, a depletion layer forms at the interface between the silicon substrate 3 and the drain diffusion layer 4 as shown by the broken line 5. This depletion layer spreads to reach the source diffusion layer 6, causing a punch-through phenomenon and causing the MOSFET to malfunction. In this case, the actual spread of the depletion layer is small at the silicon substrate surface due to the effect of the gate electrode 8 on the gate oxide film 7, but it spreads at a certain depth.
一方、上記の欠点を除去する手段として、第２
図に示す構造が提案されている。こゝでは、
MOSFETのゲート電極１１を、シリコン基板１
０上に形成した凹部側面のゲート酸化膜１３上に
形成し、前記凹部の底面のシリコン基板表面付近
１４を反対導電形に変えることにより、実際のチ
ヤンネル長を短くし、相互コンダクタンスを大き
くしている。そして、この構造ではソース、ドレ
イン電極１５，１６間に電圧を印加した場合のド
レイン拡散層１７とシリコン基板１２界面の空乏
層広がりは、深さ方向にのみ生じるのでソース拡
散層１８にはとゞかずソース、ドレイン耐圧を向
上させることができる。 On the other hand, as a means to eliminate the above drawbacks, the second
The structure shown in the figure is proposed. Here,
The gate electrode 11 of the MOSFET is connected to the silicon substrate 1.
By changing the conductivity type near the silicon substrate surface 14 at the bottom of the recess to the opposite conductivity type, the actual channel length is shortened and the mutual conductance is increased. There is. In this structure, when a voltage is applied between the source and drain electrodes 15 and 16, the depletion layer at the interface between the drain diffusion layer 17 and the silicon substrate 12 expands only in the depth direction. However, source and drain breakdown voltages can be improved.
ところが、この形状のMOSFETの従来の製造
方法は、第３図に示すように、まず、シリコン基
板１２上の所定の部分に、二酸化シリコン膜パタ
ーン１９をマスクにして、基板とは反対導電型の
拡散層２２を形成する（第３図Ａ）。 However, as shown in FIG. 3, in the conventional manufacturing method for a MOSFET of this shape, first, using a silicon dioxide film pattern 19 as a mask, a silicon dioxide film pattern 19 of a conductivity type opposite to that of the substrate is deposited on a predetermined portion of the silicon substrate 12. A diffusion layer 22 is formed (FIG. 3A).
次に、もう一度イオン注入マスク用の第２の二
酸化シリコン膜パターン２０を形成し、これをマ
スクにして、前記拡散層２２と基板１２の一部を
エツチング除去して、凹部を形成する（第３図
Ｂ）。このときソース、ドレイン拡散層１８，１
７が形成される。 Next, a second silicon dioxide film pattern 20 for an ion implantation mask is formed once again, and using this as a mask, the diffusion layer 22 and a part of the substrate 12 are etched away to form a recess (a third Figure B). At this time, source and drain diffusion layers 18,1
7 is formed.
その後、垂直方向より前記拡散と同導電形のイ
オン注入を矢印のごとく行い、前記凹部の底面に
第２の拡散層１４を形成する（第３図Ｃ）。 Thereafter, ions of the same conductivity type as the diffusion are vertically implanted as shown by the arrow to form a second diffusion layer 14 at the bottom of the recess (FIG. 3C).
そして、最後にゲート酸化膜１３を形成した
後、コンタクト窓開けを行い、ゲート電極１１、
ソース電極１５、およびドレイン電極１６を形成
する（第３図Ｄ）。 Finally, after forming the gate oxide film 13, a contact window is opened, and the gate electrode 11,
A source electrode 15 and a drain electrode 16 are formed (FIG. 3D).
しかしながら、上記第３図の方法では、ソース
ドレイン用の拡散層２２の形成を最初に行うた
め、チヤンネル長Ｌは、前記凹部形成時のエツチ
ング精度でのみ決つてしまい、相互コンダクタン
スの制御性が非常に悪かつたし、製造工程も複雑
であつた。すなわち、酸化膜パターンの形成がバ
ラツクとともに凹部のエツチングはシリコン基板
１２に直接施されるため制御性が悪く、またソー
ス、ドレインをあらかじめ拡散したのち基板と反
対導電の領域１４を形成するため、チヤンネル長
Ｌのバラツキをたとえば0.5μ以下に制御するこ
とは不可能であつた。 However, in the method shown in FIG. 3, since the source/drain diffusion layer 22 is formed first, the channel length L is determined only by the etching accuracy when forming the recess, and the controllability of mutual conductance is extremely poor. The manufacturing process was also complicated. That is, the formation of the oxide film pattern varies, and the etching of the recesses is difficult to control because it is performed directly on the silicon substrate 12. Also, since the region 14 of opposite conductivity to the substrate is formed after the source and drain are diffused in advance, the etching of the recess is difficult. It has been impossible to control the variation in length L to, for example, 0.5 μ or less.
上記製造方法の欠点を鑑み、本発明の目的はソ
ース、ドレイン耐圧が良好で、且つ、相互コンダ
クタンスの大きなMOSFETを、高精度にしかも
より簡単に製造する方法を提供することにより、
高密度な半導体集積回路を制御性良く製造可能と
するものである。 In view of the drawbacks of the above manufacturing methods, an object of the present invention is to provide a method for easily manufacturing MOSFETs with good source and drain breakdown voltages and large mutual conductance with high precision.
This makes it possible to manufacture high-density semiconductor integrated circuits with good controllability.
以下、本発明の内容を実施例（第４図）を用い
て詳しく説明する。たとえば、第４図は高密度
LSIにおけるｎチヤンネルMOSFETの製造例を
示す。 Hereinafter, the content of the present invention will be explained in detail using an example (FIG. 4). For example, Figure 4 shows high density
An example of manufacturing an n-channel MOSFET in LSI is shown.
まず、ｐ形シリコン基板３１上にCVD法によ
り、耐酸化性膜であるチツ化シリコン膜を700Å
程度堆積し、その後、全面にホトレジストを塗布
し所定のマスクを用い、露光・現像を行い、レジ
ストパターン（図示せず）を形成（以下この工程
をレジストパターンの形成と略す）し、これをマ
スクとして前記チツ化膜の一部をエツチング除去
し、耐酸化性膜であるチツ化シリコン膜パターン
３２を形成する（第４図Ａ）。こゝで、耐酸化性
膜としては、シリコン基板を酸化から守り、後の
イオン注入工程でイオンを通す物質であれば何で
も良く、厚みもイオンの加速エネルギーに応じて
設定すれば良い。 First, a silicon dioxide film, which is an oxidation-resistant film, is deposited to a thickness of 700 Å on a p-type silicon substrate 31 using the CVD method.
After that, a photoresist is applied to the entire surface, exposed and developed using a prescribed mask, and a resist pattern (not shown) is formed (hereinafter this process is abbreviated as resist pattern formation). Then, a part of the silicon dioxide film is removed by etching to form a silicon dioxide film pattern 32 which is an oxidation-resistant film (FIG. 4A). Here, the oxidation-resistant film may be any material as long as it protects the silicon substrate from oxidation and allows ions to pass through in the subsequent ion implantation step, and the thickness may be set depending on the acceleration energy of the ions.
次にチツ化膜パターン３２をマスクにして基板
３１を選択酸化して二酸化シリコン層３３をたと
えば1.0μｍ程度の厚さに形成し、さらにチツ化
シリコン膜パターン３２と二酸化シリコン層３
３′（MOSFETのゲート形成部）の一部を除いて
他部分をレジストパターン３４で被う（第４図
Ｂ）。 Next, using the silicon dioxide film pattern 32 as a mask, the substrate 31 is selectively oxidized to form a silicon dioxide layer 33 to a thickness of, for example, about 1.0 μm, and then the silicon dioxide film pattern 32 and the silicon dioxide layer 3 are formed.
Except for a part of 3' (gate formation part of MOSFET), the other parts are covered with a resist pattern 34 (FIG. 4B).
次に、チツ化シリコン膜パターン３２とレジス
トパターン３４により、ゲート形成領域の二酸化
シリコン層３３′を完全にエツチング除去し、凹
部を形成する（この場合には、凹部深さは1.0μ
ｍとなる。また、さらに深さ、すなわちゲート長
を長くする必要があればｐ形Si基板３１の一部を
追加エツチングしてもよい）。この工程は二酸化
シリコン層３３′のエツチングであるためエツチ
ングはシリコン基板３１との界面で正確に停止
し、高精度に凹部を形成することができる。 Next, the silicon dioxide layer 33' in the gate formation region is completely etched away using the silicon dioxide film pattern 32 and the resist pattern 34 to form a recess (in this case, the recess depth is 1.0 μm).
m. Furthermore, if it is necessary to further increase the depth, that is, the gate length, a part of the p-type Si substrate 31 may be additionally etched). Since this step involves etching the silicon dioxide layer 33', the etching stops accurately at the interface with the silicon substrate 31, making it possible to form recesses with high precision.
その後、ｐ形シリコン基板３１の露出した部分
３１′をチツ化シリコン膜の厚みの1.0〜1.4倍程
度の厚み、すなわち、700Å〜1000Å程度酸化
し、イオン注入用保護酸化膜３３″を形成した後
ｎ形不純物たとえば砒素イオンを矢印の方向より
200KeVの加速エネルギーで１×101 52cm2程度矢印
のごとく注入する。このとき、不純物イオンはチ
ツ化シリコン膜３２の下部の基板３１表面および
凹部の３３″直下の底面にのみ注入され、凹部側
面ではイオンはセルフアライメント的に形成され
たチツ化シリコン膜突起部３２′と凹部側面の酸
化膜３３″を斜方向より通過するため、ほぼ完全
に保護されている。したがつて凹部の側面に不純
物イオンは注入されない。この工程においてもイ
オン注入領域は正確に制御性良く形成することが
できる。また、レジストパターン３４はイオン注
入の前あるいは後で任意に除去すればよい（第４
図Ｃ）。 After that, the exposed portion 31' of the p-type silicon substrate 31 is oxidized to a thickness of about 1.0 to 1.4 times the thickness of the silicon oxide film, that is, about 700 Å to 1000 Å, and a protective oxide film 33'' for ion implantation is formed. n-type impurities, such as arsenic ions, from the direction of the arrow.
Inject about 1×10 1 52 cm 2 as shown in the arrow with an acceleration energy of 200 KeV. At this time, the impurity ions are implanted only into the surface of the substrate 31 under the silicon dioxide film 32 and the bottom surface directly below 33'' of the recess, and on the side surfaces of the recess, the ions are implanted into the silicon dioxide film protrusion 32' formed in a self-alignment manner. Since it passes through the oxide film 33'' on the side surface of the recess from an oblique direction, it is almost completely protected. Therefore, impurity ions are not implanted into the side surfaces of the recess. In this step as well, the ion implantation region can be formed accurately and with good controllability. Further, the resist pattern 34 may be arbitrarily removed before or after ion implantation (fourth
Figure C).
こうしたのち、チツ素ガス雰囲気中で任意の熱
処理を行い注入イオンを活性化する。たとえば、
今の場合1100℃で50分間の熱処理を行うと0.7μ
ｍ程度のｎ形不純物層３５が形成された。すなわ
ち、この熱処理によりｎ形のソース、ドレイン領
域３５ａ，３５ｂならびにｎ形領域３５ｃを形成
することができる。そして、保護用の酸化膜３
３″を完全に除去するとともに、前記二酸化シリ
コン層３３の表面も一部除去し、ゲート酸化膜３
６を1000Å程度形成し、チツ化シリコン膜パター
ン３２を除去するとソース、ドレイン領域３５
ａ，３５ｂが露出する。そして凹部にゲート電極
３７を形成し、ソース、ドレイン領域上にソース
電極３８とドレイン電極３９を形成する。このよ
うにして、MOSFETを作成することができる。
（第４図Ｄ）。 After this, arbitrary heat treatment is performed in a nitrogen gas atmosphere to activate the implanted ions. for example,
In this case, when heat treated at 1100℃ for 50 minutes, it becomes 0.7μ.
An n-type impurity layer 35 having a thickness of about m was formed. That is, by this heat treatment, n-type source and drain regions 35a, 35b and n-type region 35c can be formed. And a protective oxide film 3
3'' is completely removed, and a portion of the surface of the silicon dioxide layer 33 is also removed to form a gate oxide film 3.
6 is formed to a thickness of about 1000 Å and the silicon dioxide film pattern 32 is removed to form the source and drain regions 35.
a and 35b are exposed. Then, a gate electrode 37 is formed in the recess, and a source electrode 38 and a drain electrode 39 are formed on the source and drain regions. In this way, a MOSFET can be created.
(Figure 4D).
なお、第４図の方法において、イオン注入抑保
護酸化膜３３″を直接ゲート酸化膜３６の代りに
用いることもできる。すなわち、この場合にはイ
オン注入後の熱処理後、チツ化シリコン膜パター
ン３２を除去したのちただちにゲート電極やソー
スドレイン電極を形成することができる。また、
第４図において、チツ化膜パターン３２を全面除
去せず、コンタクト部のみホトエツチにより選択
的にコンタクト窓開けを行い、電極配線を形成し
ても良い。 In the method shown in FIG. 4, the ion implantation inhibiting oxide film 33'' can also be used directly in place of the gate oxide film 36. In other words, in this case, after the heat treatment after ion implantation, the silicon nitride film pattern 32 Gate electrodes and source/drain electrodes can be formed immediately after removing.
In FIG. 4, the electrode wiring may be formed by selectively forming a contact window by photo-etching only the contact portion without removing the entire surface of the silicon film pattern 32.
上記の如き製造方法では、耐酸化性膜パターン
３２の性質を積極的に利用することにより、従来
の製造方法にくらべ工程が大巾に短縮される。 In the manufacturing method as described above, by actively utilizing the properties of the oxidation-resistant film pattern 32, the steps can be greatly shortened compared to conventional manufacturing methods.
すなわち、パターン３２により選択酸化、選択
エツチング、選択的イオン注入を行うことがで
き、かつ領域３５ａ，３５ｂ，３５ｃ形成を同時
に制御性良く行うことができる。そして、ゲート
長ｌは、凹部を形成した後、イオン注入後の熱処
理で制御できるので１μｍ以下に容易に制御性良
く形成される。ゲート長ｌのバラツキは0.2μｍ
以下におさえることも容易である。具体的には本
実施例では0.7μｍ程度の実効チヤンネル長の
MOSFETを作成することができた。このように
第４図の方法では相互コンダクタンスが大きく、
ソース、ドレイン耐圧の良好なMOSFETを容易
にしかも高精度に製造することが可能になつた。 That is, selective oxidation, selective etching, and selective ion implantation can be performed using the pattern 32, and regions 35a, 35b, and 35c can be formed simultaneously with good controllability. Since the gate length l can be controlled by heat treatment after ion implantation after forming the recess, it can be easily formed to 1 μm or less with good controllability. The variation in gate length l is 0.2μm
It is also easy to keep it below. Specifically, in this example, the effective channel length is approximately 0.7 μm.
I was able to create a MOSFET. In this way, the method shown in Figure 4 has a large mutual conductance,
It has become possible to easily and precisely manufacture MOSFETs with good source and drain breakdown voltages.
以上のように本発明の方法によると、従来法に
くらべて、ソース、ドレインの拡散が凹部底面へ
の拡散と同時にできるので、拡散工程が一回省略
でき、凹部の形状が酸化時間に応じて常に同じ形
状をなし、エツチング時のエツチ速度やエツチン
グ深さによるバラツキがない。従つて、本発明で
はチヤンネル長はイオン注入後の熱処理で高精度
に制御でき、半導体基板上のイオン注入時のセル
フアライメント・マスクとなるもり上りの突起部
が耐酸化膜で形成されているため、容易に耐酸化
性膜の選択エツチングができ突起部の除去が容易
である。このように本発明は高性能絶縁ゲート型
半導体装置の製造に大きく寄与するものである。 As described above, according to the method of the present invention, compared to the conventional method, the source and drain can be diffused simultaneously to the bottom surface of the recess, so one diffusion step can be omitted, and the shape of the recess can be changed according to the oxidation time. It always has the same shape, and there is no variation due to etching speed or etching depth during etching. Therefore, in the present invention, the channel length can be controlled with high precision by heat treatment after ion implantation, and the raised protrusion that serves as a self-alignment mask during ion implantation on the semiconductor substrate is formed of an oxidation-resistant film. , the oxidation-resistant film can be easily selectively etched, and the protrusions can be easily removed. In this manner, the present invention greatly contributes to the manufacture of high-performance insulated gate semiconductor devices.
第１図は従来構造のMOSFETの断面図、第２
図は高耐圧で相互コンダクタンスの大きな従来の
MOSFETの断面図、第３図Ａ〜Ｄは第２図の
MOSFETの従来の製造工程断面図、第４図Ａ〜
Ｄは本発明の一実施例にかかる高耐圧で相互コン
ダクタンスの大きなMOSFETの製造方法を示す
工程断面図である。
３１……ｐ形シリコン基板、３２……チツ化シ
リコン膜パターン、３３，３３′……二酸化シリ
コン層、３４……レジストパターン、３３″……
保護酸化膜、３５ａ，３５ｂ……ソース、ドレイ
ン領域、３５ｃ……ｎ形領域、３７，３８，３９
……ゲート、ソース、ドレイン電極。
Figure 1 is a cross-sectional view of a MOSFET with a conventional structure, Figure 2
The figure shows a conventional device with high withstand voltage and large mutual conductance.
Cross-sectional views of MOSFET, Figures 3 A to D are similar to Figure 2.
Cross-sectional diagram of conventional MOSFET manufacturing process, Figure 4A~
D is a process cross-sectional view showing a method of manufacturing a MOSFET with high breakdown voltage and large mutual conductance according to an embodiment of the present invention. 31...p-type silicon substrate, 32...silicon film pattern, 33, 33'...silicon dioxide layer, 34...resist pattern, 33''...
Protective oxide film, 35a, 35b...source, drain region, 35c...n type region, 37, 38, 39
...Gate, source, drain electrodes.
Claims (1)
る工程と、この耐酸化性膜パターンをマスクにし
て前記半導体基板の所定の部分を選択酸化する工
程と、前記耐酸化性膜パターンと前記選択酸化領
域の一部を被うように、第１のレジストパターン
を形成する工程と、この第１のレジストパターン
と前記耐酸化性膜パターンをマスクにして所定の
部分をエツチング除去し、前記半導体基板に凹部
を形成する工程と、前記耐酸化性膜パターン下な
らびに凹部底部の半導体基板に、前記酸化工程で
発生する耐酸化性膜パターン突起部をセルフアラ
イメントマスクとして、選択的に半導体と反対導
電形の不純物をイオン注入する工程と、熱処理し
て前記凹部に隣接した半導体基板にソース、ドレ
イン領域を、凹部底部に前記ソース、ドレイン領
域と同一導電形の領域を形成する工程と、前記凹
部、ソース、ドレイン領域上に選択的に電極配線
を形成する工程とを備えたことを特徴する絶縁ゲ
ート型半導体装置の製造方法。 ２ 凹部を形成したのち、この凹部側面部に酸化
膜を形成したのちイオン注入することを特徴とす
る特許請求の範囲第１項に記載の絶縁ゲート型半
導体装置の製造方法。 ３ 酸化膜をゲート酸化膜とすることを特徴とす
る特許請求の範囲第１項に記載の絶縁ゲート型半
導体装置の製造方法。[Scope of Claims] 1. A step of forming an oxidation-resistant film pattern on a semiconductor substrate, a step of selectively oxidizing a predetermined portion of the semiconductor substrate using the oxidation-resistant film pattern as a mask, and a step of selectively oxidizing a predetermined portion of the semiconductor substrate, and forming a first resist pattern so as to cover the film pattern and a part of the selective oxidation region; etching away a predetermined portion using the first resist pattern and the oxidation-resistant film pattern as a mask; The step of forming a recess in the semiconductor substrate, and selectively applying the oxidation-resistant film pattern protrusion generated in the oxidation step to the semiconductor substrate under the oxidation-resistant film pattern and at the bottom of the recess as a self-alignment mask. a step of ion-implanting impurities of a conductivity type opposite to that of the semiconductor; and a step of heat-treating to form source and drain regions in the semiconductor substrate adjacent to the recess and regions of the same conductivity type as the source and drain regions at the bottom of the recess. . A method of manufacturing an insulated gate semiconductor device, comprising the steps of: selectively forming electrode wiring on the recessed portion and the source and drain regions. 2. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein after forming the recess, an oxide film is formed on the side surfaces of the recess, and then ions are implanted. 3. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the oxide film is a gate oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2556478A JPS54117691A (en) | 1978-03-06 | 1978-03-06 | Production of insulating gate-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2556478A JPS54117691A (en) | 1978-03-06 | 1978-03-06 | Production of insulating gate-type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54117691A JPS54117691A (en) | 1979-09-12 |
| JPS6126234B2 true JPS6126234B2 (en) | 1986-06-19 |
Family
ID=12169418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2556478A Granted JPS54117691A (en) | 1978-03-06 | 1978-03-06 | Production of insulating gate-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54117691A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56133869A (en) * | 1980-03-24 | 1981-10-20 | Oki Electric Ind Co Ltd | Mos type semiconductor device and manufacture thereof |
| JPS5931067A (en) * | 1982-08-14 | 1984-02-18 | Matsushita Electric Works Ltd | Manufacture of vertical type transistor |
| JP2615667B2 (en) * | 1987-09-28 | 1997-06-04 | 日産自動車株式会社 | Method of manufacturing MOS field effect transistor |
| US6528847B2 (en) * | 1998-06-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Metal oxide semiconductor device having contoured channel region and elevated source and drain regions |
-
1978
- 1978-03-06 JP JP2556478A patent/JPS54117691A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54117691A (en) | 1979-09-12 |
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