JPS63302562A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the fluctuation of gate threshold voltage even when an N layer as a punch-through top is formed at a shallow position in high concen tration by shaping the N guard layer, using a gate electrode as a mask and forming source-drain layers, employing the gate electrode and an oxide film in the periphery of the gate electrode as masks. CONSTITUTION:When a buried channel type PMOS type semiconductor device having a channel in a section inner than the surface of an N-type region 2 in a semiconductor substrate 1 is manufactured, a gate electrode 10 is formed onto the surface of the N-type region 2 through a gate oxide film 5, an N type impurity is implanted onto the N-type region 2, using the gate electrode 10 as a mask, and an N guard layer 14 is shaped near the surface of the N-type region 2. An oxide film 15 is formed around the gate electrode 10, and a P-type impurity is implanted into the N-type region 2, employing the gate electrode 10 and the oxide film 15 as masks, thus forming source-drain layers 16 in the external sections of a section under the oxide film 15 in the N guard layer 14 as the section under the oxide film 15 in the N guard layer 14 is left as it is. The source-drain layers 16 are diffused to the inside through heat treat ment, and the N guard layers 14 are changed into P-type layers 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing an MO≦ type semiconductor device, and particularly to a method of manufacturing a buried channel type MOS type semiconductor device.

(Prior Art) In a semiconductor device equipped with a buried channel type PMOS type FET, in order to prevent punch-through from occurring between the source and drain, there is a There is a method of forming a type of diffusion layer and having the diffusion layer function as a punch-through stop.

FIG. 5 shows a PMO5 type O5T as an example (Dlg, ol' VLSI Symp, p62
-03, (1985)). In the figure, 101 is an N well, 102 is a source/drain region (P), and 10
3 is a counter doping layer (P), 104 is a punch-through stop (N), 105 is an oxide film, 106 is a gate (N''), and 107 is a spacer as a gate sidewall.

The punch-through stop (N”) 104 is, for example,
At a high energy of 130 KcV, 1, OX
It is formed by ion implantation of phosphorus ions at a low dose of 10'cm-2.

In this way, conventionally, the punch-through stop (N”
) 104 was formed by high acceleration, low dose ion implantation. The reason for doing this is to prevent the gate threshold voltage from changing even in the presence of the N layer as the punch-through stop 104. That is, when the N layer becomes shallow or has a high a degree, the channel is turned off in the vicinity of the N layer. In this case, the channel will not turn on unless a deeper voltage is applied to the gate electrode. In other words, the gate threshold voltage becomes extremely deep. The cause of this is
The N layer serves as the punch-through stop 104, and the P layer serves as the opposite type source/drain region 102.
+ layer offset amount during ion implantation (spacer 10
7) is as large as 0.25 μm, for example, and this is caused by the fact that the highly doped source/drain P+ region cannot compensate for the N layer, and as a result, a wide N layer remains.

However, the above-described high acceleration, low dose ion implantation has the following various drawbacks. That is, 13
Ion implantation at a high acceleration such as 0 KeV cannot be used also as ion implantation for forming a lightly doped drain (LDD) N- of an N-channel transistor. Therefore, PEP
(Photo-etching process) and ion implantation process are increased, resulting in higher costs. Furthermore, due to high acceleration, ions penetrate through the gate electrode used as a mask during implantation.
It gets stuck in the channel. For this reason, a problem also arises in reliability as an element. In addition, above 1, Qx
The low dose of 1012CI11-2 is on the order of 10160111-3, which is a lower concentration than the channel region. Such a low dose does not block the diffusion of the source/drain P layer, and furthermore, the depletion layer extending from the source/drain to the channel side cannot be suppressed very much, so the ability to prevent the short channel effect is small.

(Problem to be Solved by the Invention) As described above, in order to prevent the gate threshold voltage from changing, conventionally, the punch-through stop was formed at a deep position with low concentration. Dose ion implantation was being carried out. However, such ion implantation and the resulting punch-through stop have drawbacks such as an increase in the number of steps, a decrease in device reliability, and a low ability to prevent short channel effects.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause a change in gate threshold voltage even when a high concentration N layer is formed at a shallow position as a punch-through stop. be.

[Structure of the invention]

(Means for Solving the Problems) A first aspect of the present invention is a MOS type semiconductor device for manufacturing a buried channel type PMOS type semiconductor device having a channel inside an N type region in a semiconductor substrate than the surface thereof. In the manufacturing method, a gate electrode is formed on the surface of the N-type region of the semiconductor substrate via a gate oxide film;
forming an N-type impurity near the surface of the N-type region; forming an oxide film around the gate electrode; and using the gate electrode and the oxide film as a mask to form an N-type impurity. a step of implanting an impurity into the N-type region, leaving a portion of the N guard layer under the oxide film as it is, and forming a source/drain layer on the outside of the portion left as it is; The source/drain layer is diffused inward by heat treatment, and the N
The process of making the card layer into a P type.

A second aspect of the present invention is a method for manufacturing a MOS semiconductor device for manufacturing a CMOS semiconductor device having a channel in an N-type region and a P-type region for forming a CMOS in a semiconductor substrate; forming gate electrodes on the surfaces of the N-type and P-type regions through gate oxide films; implanting N-type impurities into the N-type and P-type regions using the respective gate electrodes as masks; simultaneously forming an N guard layer near the surface of the P-type region and a low concentration drain N layer near the surface of the P-type region; forming an oxide film around each of the gate electrodes; forming an oxide film around each of the gate electrodes; Using the oxide film as a mask, a P-type impurity is implanted into the N-type region, and an N-type impurity is implanted into the P-type region, so that the N-guard layer and the low-concentration drain N-layer are implanted under each oxide film. a step of forming source and drain layers on the outside of these portions while leaving the portions as they are; a subsequent heat treatment to diffuse the source and drain layers inward and make the N card layer P type; It is configured as having a process.

(Function) In the first invention of the present invention for manufacturing a PMOS type semiconductor device, an N guard layer is formed using the gate electrode as a mask, and then an oxide film around the gate electrode is used as a mask. A source/drain layer is formed. Therefore, the portion of the N guard layer under the oxide film remains as thin as the oxide film. In this way, the N-guard layer remains as a thin layer, and in order to diffuse the source/drain layer inward through subsequent heat treatment and make the N-guard layer P-type, N-type impurities are added when forming the N-guard layer. Even if it is formed by implantation at low energy and high dose, a deep threshold voltage can be avoided. Moreover, since the N guard layer was formed with a high concentration,
The N guard layer functions well as a diffusion block of the source-drain layer, improving the ability to prevent short channel effects. Furthermore, by implanting the N-type impurity at low energy, the N-type impurity is reliably prevented from penetrating the gate electrode and oxide as a mask and entering the channel region, thereby increasing the reliability of the device.

In the second aspect of the present invention for obtaining a CMOS type semiconductor device, in addition to the effects obtained by the first invention described above, the following effects are expected. That is, N.M.O.
Low concentration drain (LDD) is used to manufacture S-type semiconductor devices.
) In order to form a single layer of N, it is necessary to implant N-type impurities. The implantation of the N-type impurity must be performed with low energy and low acceleration. In the manufacturing process of the PMO5 type semiconductor device, the N-type impurity is implanted in a low energy state as described above to form the N guard layer. Therefore, the process of forming this N guard layer and the process of forming a single layer of LDDN can be combined. As a result, a CMOS type semiconductor device can be manufactured with a small number of steps.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1(a) to (h).

As shown in Figure 1(a), the impurity concentration is 1×1015c.
Using a photoresist as a mask, phosphorus ions and boron ions are implanted into the surface of a P-type single crystal silicon substrate 1 of Il+-3, and activated by heat treatment to form an N well 2 and a P well 3. N-well 2 becomes a P-channel transistor region, and P-well 3 becomes an N-channel transistor region.

Next, as shown in FIG. 1(b), a field oxide film 4 is formed on the surfaces of the N well 2 and P well 3 by selective oxidation using a silicon nitride film. Subsequently, a thickness of 150 mm is applied to the element region of the substrate 1 sandwiched between the field oxide films 4.
A gate oxide film 5 is formed on the surface. After this, in order to prevent punch-through between the source and drain and to obtain the desired gate threshold voltage, boron ions 6 are applied to the element region of the N-channel transistor, and phosphorus ions 7 are applied to the element region of the P-channel transistor. Arsenic ions 8 and boron ions 9 are implanted. By these ion implantations, the PN junction of the PMOS channel is formed at a depth of 800 mm.

Next, as shown in FIG. 1(c), a polycrystalline silicon layer 10A is deposited on the entire surface to a thickness of 5000 nm. This polycrystalline silicon layer 10A is etched by reactive ion etching (RIE) using a photoresist as a mask to form a gate electrode 10 as shown in FIG. 1(C). However, the resistance of the polycrystalline silicon film 10A is lowered by diffusion of phosphorous oxychloride (POCN 3) before etching, so that the polycrystalline silicon film 10A can be used as a metallic conductor. The polycrystalline silicon film used as the gate electrode has phosphorus diffused in this way and is of N type, so it has a gate threshold voltage of about -0.8V due to the difference in work function from the substrate element region. When attempting to form a P-channel transistor with 2 layers (11A) and an N layer (11A) in the channel region, as shown on the right side of FIG.
It is a buried type in which a PN junction 11 is formed as a boundary with the N well 2).

Next, as shown in FIG. 1(d), using the gate electrode 10 as a mask, phosphorus ions 12 were irradiated with 4×1 ions at 70 KeV.
0 ``'m''''2 injections.

This implanted phosphorus ion 12 is heated to the first
As shown in Figure (e), an N- region 13 of the LDD is formed on the N-channel transistor side (left side), and an N guard layer 14 is formed on the P-channel transistor side (right side). The N-1 region 13 of the LDD weakens the electric field near the drain and reduces the generation of hot carriers. The N'''' guard layer 14 prevents the P+ type source/drain diffusion layer to be formed later from penetrating into the channel side.

Next, the intermediate stage semiconductor device shown in FIG.
Oxidize in 02 atmosphere at 00°C for 60 minutes.

As a result, a silicon oxide film 15 is grown around the polycrystalline silicon gate electrode 10.degree. 10 to a thickness of about 0.1 .mu.m.

Figure 1(f) shows the P-channel transistor side (right side).
This shows a state in which a silicon oxide film 15 has grown around the gate electrode 10. In this state, on the P-channel transistor side, using the gate electrode 10 and silicon oxide film 15 as a mask, boron fluoride ions (BF, ") are
5X1015cII+-2 is injected and heat treated. As a result, a P type source/drain diffusion layer 16 is formed as shown in FIG. 1(g). With its formation, the N-guard layer 14 remains as a P'''' layer 21 that is thinner than the two layers 11A formed on the channel surface due to the diffusion of boron in the source and drain.

On the other hand, on the N-channel transistor side (left side),
The silicon oxide film 15 is RIEL, and a portion of the oxide film 15 is left on the side wall of the gate electrode 10.

By implanting arsenic ions into the outside of the remaining silicon oxide film, a source/drain diffusion layer (N) 17 is formed as shown in FIG. 1(h).

Thereafter, as shown in FIG.
Deposit 8. A contact hole 19 is formed in this insulating film 18.
A CMOS semiconductor device shown in FIG. 1(h) is obtained by opening a hole and applying A, 77 wiring 20.

The semiconductor device manufactured in this manner can be expected to have the effect of suppressing short channel effects without adversely affecting circuit operation. This will be explained in detail below.

That is, as shown in FIGS. 1(d) and (e), phosphorus ions 12 were implanted to form the N'''' guard layer on the P-channel transistor side (right side), but the amount of phosphorus ions implanted was It has a large effect on the short channel effect of the transistor.Figure 2 shows the relationship between the phosphorus dose and the short channel effect.From this figure, in order to suppress the short channel effect, I It can be seen that a dose of -2 or more is required. Also, the relationship between the phosphorus dose and the threshold voltage is shown in Figure 3. From this figure, it can be seen that the threshold voltage becomes deeper with the dose. I see. The reason why it becomes so deep is due to the presence of the N-guard layer. Generally, there are fluctuations in the manufacturing process of semiconductor devices, that is, slight changes in the formation state. Due to these fluctuations, the N'''' guard layer 14 The way they are made is slightly different.

Since the formation of the N-guard layer 14 is slightly different, variations occur in the gate threshold voltage. However, circuits are generally designed with a margin of about ±0.2V regarding the gate threshold voltage. Therefore, N
``''If the change in threshold voltage Δvth due to the difference in the formation of the guard layer 14 is within ±0.2 V, there will be no problem in circuit operation. From this point of view, if we look for a region where the gate threshold voltage does not change much even if the structure of the N-guard layer 14 changes, with reference to FIG.
It can be seen that the dose is 14CII+-2 or less. As mentioned above, in order to suppress the short channel effect and to prevent the gate threshold voltage from changing too much even with process changes, the dose should be set to 1×1.
013cm-2 and I x 10'' CII+-2. However, in the above example, the
Since the ions are implanted at X 1013am-",
It is clear that this condition is satisfied.

Furthermore, from FIG. 4, it can be seen that the offset between the phosphorus ion implantation for forming the N-guard layer and the P source-drain ion implantation needs to be 1000 Å or less. Since it is difficult to control an offset amount of 1000 Å or less, in the above embodiment, a silicon oxide film 15 is formed around the polycrystalline silicon gate 10 instead of forming side walls.
The oxide film 15 satisfies the offset of 1000A or less.

Further, in the above embodiment, after the ion implantation to form the N-guard layer 14, a heat treatment called oxidation is added to form the N-guard layer 14.
4 is diffused further inside (channel side), so that it can be controlled by the gate voltage, and the N-guard layer 14
The effect can be further increased.

[Effects of the Invention] According to the first aspect of the present invention, the PMO5 type semiconductor device does not have a deep gate threshold voltage, has excellent ability to prevent short channel effects, and has high reliability as an element. You can get it as something.

According to the second aspect of the present invention, a PMOS type semiconductor device in a CMOS type semiconductor device can be obtained with the same effects as in the first aspect. Furthermore, by combining the manufacturing steps for each of the P and NMOS type semiconductor devices, it is possible to obtain an efficient and inexpensive device with fewer steps.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are process cross-sectional views of an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of N'''' guard layer resilience, the shortest achievable gate length, and the threshold voltage. FIG. 4 is a diagram showing the relationship between the oxide film thickness around the polycrystalline silicon gate and the gate threshold voltage, and FIG. 5 is a cross-sectional view showing an example of a conventional PMOS semiconductor device. be. DESCRIPTION OF SYMBOLS 1... P-type t-crystalline silicon substrate, 2... N-well (N-type region), 3... P-well (P-type region), 4...
・Field oxide film, 5... Gate oxide film, 6...
Boron ion, 7... Phosphorus ion, 8... Arsenic ion, 9... Boron ion, 10... Gate electrode, 1
0A... Polycrystalline silicon layer, 11... PN junction of buried channel, 11A... P layer, 12... Phosphorus ion, 13... LDDN'''' (N channel side), 1
4...N"""guard layer channel side), 15...Silicon oxide film around gate electrode, 16...P source/drain diffusion layer, 17...N source/drain diffusion layer, 18... ...SiO2 insulating film, 19...contact hole, 20...AN wiring, 21...P layer formed by diffusing P'' layer impurity into N- guard layer. Applicant's agent: Sato - Yuhaku 1 Figure 1 Figure 5

Claims (1)

[Scope of Claims] 1. In a method of manufacturing a MOS type semiconductor device for manufacturing a buried channel type PMOS type semiconductor device having a channel inside the N type region of the semiconductor substrate from the surface; forming a gate electrode on the surface of the region via a gate oxide film; using the gate electrode as a mask, implanting an N-type impurity into the N-type region to form an N guard layer near the surface of the N-type region; forming an oxide film around the gate electrode;
By implanting a P-type impurity into the N-type region using the gate electrode and the oxide film as a mask, a portion of the N guard layer under the oxide film is left as it is, and a portion outside the left portion is implanted. A step of forming a source/drain layer; a subsequent heat treatment
A method for manufacturing a MOS type semiconductor device, comprising: diffusing a drain layer inward to make the N card layer a P type. 2. CMOS having channels in each of the N-type region and P-type region for forming CMOS on a semiconductor substrate
In a method for manufacturing a MOS type semiconductor device for manufacturing a semiconductor device; forming gate electrodes on the surfaces of the N-type and P-type regions of the semiconductor substrate through gate oxide films; and using each of the gate electrodes as a mask. a step of simultaneously forming an N guard layer near the surface of the N type region and a low concentration drain N layer near the surface of the P type region by implanting N type impurities into the N and P type regions; forming an oxide film around each gate electrode; using the gate electrode and the oxide film as a mask, implanting a P-type impurity into the N-type region and implanting an N-type impurity into the P-type region; , leaving the portions of the N guard layer and the low concentration drain N layer under the respective oxide films as they are, and forming source and drain layers on the outside of the portions left as they are; by subsequent heat treatment; An MO characterized by comprising the step of diffusing the source/drain layer inward to make the N card layer a P type.
A method for manufacturing an S-type semiconductor device.