JPH04142749A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a field concentration on the end part, which is situated on the side of a drain, of a gate electrode and to reduce a parasitic capacitance, which is constituted between the gate electrode and source and drain diffused layers, by a method wherein the gate electrode is formed into such a form that it is extendedly provided from the upper part of a gate insulating film to the upper part of a silicon dioxide film thicker than the gate insulating film. CONSTITUTION:A silicon dioxide film (a second insulating film) 14 is formed at a position other than the position of a channel formation region of an element formation region. Then, a silicon nitride film 12 and a silicon dioxide film 11 are removed and moreover, an oxidation treatment is performed, whereby a gate insulating film 4 is formed at the channel formation region. Moreover, a polycrystalline silicon layer added with phosphorus is applied and formed on the main surface of a P-type silicon substrate 1 and a selective etching is performed to form a gate electrode 15. Here, the width (l1) of the electrode 15 is set in such a way that it is larger than the width (l2) of the channel formation region and the electrode 15 is formed in such a way that it is extendedly provided from the upper part of the film 4 to the upper part of the film 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an MO3 type transistor.

[Conventional technology]

The structure of a conventional MO8 type transistor will be explained with reference to the drawings. Figure 3 shows a lightly doped drain (
Lightly Doped Drain, hereinafter referred to as LDD
This shows a MOS type transistor with a configuration called .

In FIG. 3, a thick silicon dioxide film 2 formed by selective oxidation and a P-type diffusion layer 3 called a channel stopper are formed in an element isolation region on a P-type silicon substrate 1. A gate insulating film 4 is formed in the element formation region, and a gate electrode 5 made of polycrystalline silicon or a laminated layer of a polycrystalline silicon layer and a silicide layer containing a high melting point metal such as tungsten is provided on the gate insulating film 4. 5
An N- type diffusion layer 6 with a low impurity concentration is provided by being matched with the thick silicon dioxide film 2. Further, a side wall 7 of a silicon dioxide film called a side wall is provided on the side surface of the gate electrode 5 by, for example, a CVD method, and the gate electrode 5 and the side wall 7 are aligned with the thick silicon dioxide film 2 to form a high impurity concentration N. “A type diffusion layer 8 is provided.

The N-type diffusion layer 6 is formed by ion implantation of phosphorus, for example, 50 to 80K.
eV energy and 2.0X1013 to 1.0XIO1
The N1 type diffusion layer 8 is realized by ion implantation with a dose of 4/cm2, and the N1 type diffusion layer 8 is formed by arsenic ion implantation, for example, with an energy of 50 to 100 keV and 3.0×1015
This is achieved by ion implantation at a dose of ~1.0X1016/cm2.

In order to reduce the contact resistance with the metal wiring layer formed in the subsequent process of the N+ type diffused layer 8, a predetermined or higher impurity concentration is required. In order to prevent concentration of the electric field between the gate electrode 5 and the N-type diffusion layers 6 and 8 in the region, the impurity concentration must be within a predetermined range. Therefore, in a MOS transistor in which the gate length is 142 μm or less and the gate insulating film is 250 A or less for the purpose of high integration, the source/drain diffusion layer region has double N-type diffusion layers with different impurity concentrations.
will be applied.

[Problem to be solved by the invention]

This conventional MOS type transistor has the following problems.

First, when thinning the gate insulating film and reducing the gate length for the purpose of higher integration and higher speed, in order to maintain the electric field strength at the conventional level, it is necessary to reduce the impurity concentration of the N-type diffusion layer. Although the drive capability of the transistor increases, the parasitic resistance associated with the source/drain diffusion layer increases, making it impossible to achieve the desired capability.

Second, the pattern accuracy of the gate length, which is an index of performance of a transistor, is determined only by the device performance of the exposure device and the gate electrode etching device. Therefore, from the viewpoint of manufacturing yield, the maximum gate length manufacturing standard is 0.8 ± 0.15 μm with the current technology, and in this case, the derating factor of circuit operation
g factor (ratio of fastest to slowest) is about 1.5 times. A possible cause of variations in gate length may be, for example, partial shedding of crystal grains at the grain boundaries of polycrystalline silicon, which is the material for the gate electrode, and in this case, the only countermeasure that can be taken is to make the crystal grains finer.

[Means to solve the problem]

A first method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a first insulating film in a region other than an element formation region of a semiconductor substrate of one conductivity type, and forming a channel formation region in the element formation region. selectively forming a second insulating film thinner than the first insulating film in the region to be removed; forming a gate insulating film thinner than the second insulating film in the channel forming region; forming a gate electrode extending from above the film onto the second insulating film; and forming a source/drain diffusion layer of opposite conductivity type in alignment with the first insulating film and the gate electrode. It consists of:

A second method of manufacturing a semiconductor device according to the present invention includes a step of selectively forming a first insulating film in a region other than an element formation region of a semiconductor substrate of one conductivity type, and a channel formation region in the element formation region. a step of selectively forming a second insulating film thinner than the first insulating film in a region excluding the first insulating film; After forming the source/drain diffusion layer, forming a gate insulating film thinner than the second insulating film in the channel forming region, and forming a gate electrode extending from above the gate insulating film onto the second insulating film. and forming a highly doped second source/drain diffusion layer of an opposite conductivity type in the semiconductor substrate in alignment with the gate electrode and the first insulating film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a first embodiment of the present invention.

First, as shown in FIG.
A silicon nitride film 12 with a thickness of 0 to 150 nm is formed in layers, and after selectively removing the silicon nitride film 12 using photolithography technology, a silicon dioxide film (first An insulating film) 2 is formed in a region other than the element forming region, and at the same time a P-type diffusion layer 3 is formed directly under the silicon dioxide film 2. Formation of silicon dioxide films 11 and 2 is 900 to 10
The silicon nitride film 12 is formed by a known low pressure CVD technique.

The P-type diffusion layer 3 provides electrical isolation between elements, and is realized by implanting boron ions with an energy of 70 to 100 keV and a dose of I x 1013 to 2×1013/cm2. Next, of the silicon nitride film 12 used for selective oxidation, a portion located outside the channel formation region is selectively removed using a photoresist layer 13.

Next, as shown in FIG. 1(b), by performing oxidation treatment again, a silicon dioxide film (150 to 300 nm thick) is formed in the element formation region at a position other than the channel formation region.
A second insulating film) 14 is formed.

Next, as shown in FIG. 1(c), a silicon nitride film 1 is formed.
2. By removing the silicon dioxide film 11 and further performing oxidation treatment, a gate insulating film 4 with a thickness of 10 to 25 nm is formed in the channel formation region. This gate insulating film 4
The formation is carried out in an N2-0□ atmosphere at 700-950°C. The silicon dioxide film 14 is the silicon dioxide film 11
The thickness of the gate insulating film 4 can be reduced at the same time as the gate insulating film 4 is removed.
At the time of formation, the film thickness is 50 to 200 nm. Further, a polycrystalline silicon layer doped with phosphorus is deposited on the main surface of the P-type silicon substrate 1, and selectively etched using photolithography to form the gate electrode 15. The polycrystalline silicon layer has a thickness of 300 to 450 nm using low pressure CVD technology.
The layer resistance is further formed by diffusing and introducing phosphorus at a temperature of 820° C. to 950° C. to have a layer resistance of 10 to 40 Ω/hole. Here, the width J of the gate electrode 15 is set to be larger than the width ρ2 of the channel forming region, and the gate electrode 15 is formed to extend from the gate insulating film 4 to the silicon dioxide film 14. In this embodiment, It j12 = 600 to match the junction depth of the N- type diffusion layer 6 as a source/drain to be formed in a later process.
Set to nm.

Next, as shown in FIG. 1(d), a silicon dioxide film 14 is formed using the gate electrode 15 and the silicon dioxide film 2 as a mask.
After removing the
The silicon dioxide film 2 and the electrodes 1 to 15 are aligned in the sixth order to form a 0 nm silicon dioxide film 14A to form a source/drain diffusion layer consisting of an N- type diffusion layer 6 and an N1 type diffusion layer 8. The N-type diffusion layer 6 contains 50 to 80K of phosphorus.
Energy in eV, 2 x 1013 to I x 101
Ion implantation with a dose of 4/cm2 and an energy of 50 to 100 keV of N+ type scattered layer 8 arsenic 3×10
It is formed by ion implantation at a dose of 15 to 1 x 1016/cm2 and heat treatment at 950°C in a nitrogen atmosphere, and due to the difference in diffusion coefficient between phosphorus and arsenic, the N- layer has a low impurity concentration of phosphorus and a deep junction depth. It is formed into a double diffusion layer of a type diffusion layer 6 and an N+ type scattering layer 8 having a high impurity concentration of arsenic and a shallow junction depth.

In this embodiment, the N-type diffusion layer 6 made of phosphorus has a junction depth of 500 nm so that its junction end reaches the channel forming region.
The dose, heat treatment temperature, and time are set so that.

Next, regarding the second embodiment of the present invention, FIGS. 2(a) to (d)
).

First, as shown in FIG. 2(a), a silicon dioxide film 1 is deposited on a P-type silicon substrate 1 by the same means as in the first embodiment.
1. Silicon nitride film 12. P-type diffusion layer 3. After forming the silicon dioxide film 2, the silicon nitride film 12 is selectively removed using a photoresist layer 3 so that it remains only in the channel formation region. Furthermore, using this photoresist layer 13, phosphorus is selectively ion-implanted into the device region other than the channel forming region. This phosphorus ion implantation is performed under conditions of an energy of 50 to 80 keV and a dose of 1.times.10.sup.13 to 5.times.10.sup.13/cm.sup.2.

Next, as shown in FIG. 2(b), a silicon dioxide film 14 is formed by a selective oxidation technique, and at the same time, an N-type diffusion layer 16 is formed by implanting phosphorus ions directly under the silicon dioxide film 14 as a channel formation region. It is formed in alignment with the silicon dioxide film 14.

Next, as shown in FIG. 2C, a gate insulating film 4 and a gate electrode 15 are formed in the channel forming region by the same means as in the first embodiment.

Further, as shown in FIG. 2(d), after removing the silicon dioxide film 14 using the gate electrode 15 as a mask, a silicon dioxide film 14A having a thickness of 15 to 30 nm is formed on the surface by thermal oxidation again.

Next, the gate electrode 15. Arsenic ions are introduced into the P-type silicon substrate 1 in alignment with the silicon dioxide film 2 to form an N+ type dispersed layer 18 with a high impurity concentration.

1 In the second embodiment, compared to the first embodiment, the N-type diffusion layer 1
Since the gate electrode 6 can be formed in alignment with the channel forming region, there is an advantage that there is no need to strictly control the accuracy of alignment between the channel forming region and the gate electrode 15.

Although the present invention has been described above by taking an N-type MOS transistor as an example, it is clear that the same effect can be obtained with a P-type MOS transistor.

〔Effect of the invention〕

As explained above, according to the present invention, the gate electrode has a shape extending from above the gate insulating film to the silicon dioxide film, which is thicker than the gate insulating film. The concentration of electric field in this area is alleviated by making the gate insulating film thicker in that area. Therefore, there is an effect that deterioration of the transistor over time is reduced and reliability can be improved.

Further, the parasitic capacitance formed between the gate electrode and the source/drain diffusion layer is reduced, and the circuit operation speed can be increased.

Furthermore, the channel length, which was conventionally determined by the width of the gate electrode, can be determined by the width of the silicon nitride film used to form the second insulating film in the present invention, eliminating manufacturing variations caused by the gate electrode material. In addition, by using the lateral aperture of the second insulating film, even if an exposure device with the same resolution is used, the channel length can be made narrower by twice the lateral aperture of the second insulating film. It also has the effect of being achievable.

[Brief explanation of drawings]

1(a)-(d) and FIG. 2(a)-(d) are cross-sectional views of a semiconductor chip for explaining the second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor chip. FIG. 2 is a cross-sectional view of a semiconductor chip for explaining an MO5 type transistor. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Silicon dioxide film (first insulating film), 3... P-type diffusion layer, 4... Gate insulating film, 5.15... Gate electrode, 6,16...
N type diffusion layer, 7... side wall, 8, 18... N+ type diffused layer 11... silicon dioxide film, 12... silicon nitride film, 13... photoresist layer, 14...・Silicon dioxide film (second insulating film).

Claims (1)

[Claims] 1. A step of selectively forming a first insulating film in a region other than an element formation region of a semiconductor substrate of one conductivity type; selectively forming a second insulating film thinner than the first insulating film; forming a gate insulating film thinner than the second insulating film in the channel formation region; a step of forming a gate electrode extending on the second insulating film; and a step of forming a source/drain diffusion layer of opposite conductivity type in alignment with the first insulating film and the gate electrode. A method for manufacturing a semiconductor device. 2. Selectively forming a first insulating film in a region other than the element formation region of a semiconductor substrate of one conductivity type, and forming a first insulating film thinner than the first insulating film in a region other than the channel formation region in the element formation region. a step of selectively forming a second insulating film, and forming a low concentration first source/drain diffusion layer of an opposite conductivity type on the semiconductor substrate in alignment with the second insulating film, and then forming the channel. forming a gate insulating film thinner than the second insulating film in the region; forming a gate electrode extending from above the gate insulating film onto the second insulating film; forming a highly doped second source/drain diffusion layer of an opposite conductivity type on the semiconductor substrate in alignment with the insulating film of the semiconductor device.