JP2010147325A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a gate breakdown voltage comparing to the conventional identically sized semiconductor device, reducing an area of element isolation region by making an element isolation layer the structure including no bird's beak to miniaturize the element, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device forms a LOCOS (local oxidation of silicon) film extended from the element forming region to the element isolation region on the surface of the semiconductor substrate. A gate oxide film connected to the LOCOS film is formed on the semiconductor substrate in the element forming region. A conductive film is formed so as to cover the LOCOS film and the gate oxide film. A gate electrode covering part of the gate oxide film and the LOCOS film is formed by partially etching the conductive film. The LOCOS film is divided into the element isolation layer and a highly thickened part for composing the end of the gate oxide film by partially etching the LOCOS film exposed by the etching of the conductive film. A drain region and a source region are formed at the position sandwiching the gate electrode by conducting the ion implantation to the surface of the semiconductor substrate exposed by the etching of the LOCOS film. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device including a MOS type semiconductor element provided with an element isolation layer for isolating adjacent elements.

A semiconductor device having a MOS (Metal-Oxide-Semiconductor) structure is known. FIG. 1 shows the structure of a MOS type semiconductor device described in Patent Document 1, and a manufacturing method thereof will be described. First, a mask for selectively performing ion implantation is formed on the p-type semiconductor substrate 1, phosphorus ions (31P +) are implanted therein to form a low concentration impurity diffusion region 2, and then arsenic ions (75As +). Is implanted to form a high concentration impurity diffusion region 3. Next, an element isolation layer 4 is formed by an LOCOS method in an element isolation region provided outside the low concentration impurity diffusion region 2 and the high concentration impurity diffusion region 3. Next, a wet oxide film 5 is formed on the surface of the p-type semiconductor substrate 1. At this time, since the high concentration impurity diffusion region 3 has a higher impurity concentration than the channel region and the low concentration impurity diffusion region 2, the growth of the wet oxide film 5 on the high concentration impurity diffusion region 3 is promoted. The thickness is thicker than other areas. A polycrystalline silicon film is deposited on the surface of the wet oxide film 5 thus formed, and this is dry-etched to form the gate electrode 6. Thereafter, the portion of the wet oxide film where the gate electrode 6 is not formed is removed, the gate oxide film 5 is left, and the source / drain electrodes are formed on the high-concentration impurity diffusion region 3 to complete.
As described above, in the MOS type semiconductor device described in Patent Document 1, the wet oxide films having different thicknesses are formed on the high-concentration impurity diffusion region and the low-concentration impurity diffusion region, whereby the gate oxide film having the lowest breakdown voltage is formed. The gate breakdown voltage is increased by increasing the thickness at both ends, and the gate oxide film is shortened as compared with the prior art by removing the wet oxide film where the gate electrode is not formed, thereby miniaturizing the device.
JP 7-66400 A

However, the element isolation layer provided in the MOS type semiconductor device described in Patent Document 1 is formed using a conventional LOCOS method, and has a structure including a so-called bird's beak at the end. . As a result, there is a problem that the width of the element isolation region is increased and it is difficult to miniaturize the element. Although the gate oxide film is formed to have a large thickness at both ends for the purpose of improving the gate breakdown voltage, the end of the high concentration impurity diffusion region is directly below the thin part of the wet oxide film. Therefore, when a voltage is applied between the gate and the drain and between the gate and the source, an electric field is applied to the thin portion of the gate oxide film, and it is difficult to obtain a desired gate breakdown voltage.
The present invention has been made in view of the above points, and improves the gate breakdown voltage as compared with a conventional semiconductor device of the same size, and has an element isolation region that does not include a bird's beak. An object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of reducing the area of the semiconductor device and miniaturizing elements.

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an element formation region provided with semiconductor elements and an element isolation region provided with element isolation layers that insulate and isolate adjacent semiconductor elements. A step of forming a LOCOS film extending from the element formation region to the element division region on the surface of the semiconductor substrate, and a gate oxidation connected to the LOCOS film on the semiconductor substrate in the element formation region Forming a film; forming a conductive film so as to cover the LOCOS film and the gate oxide film; and partially etching the conductive film to cover a part of the gate oxide film and the LOCOS film. Forming a gate electrode; and partially etching the LOCOS film exposed by etching the conductive film to form the LOCOS film in the element A step of dividing into a delamination layer and a high-thickness portion constituting an end portion of the gate oxide film, and ion implantation is performed on the surface of the semiconductor substrate exposed by etching of the LOCOS film to sandwich the gate electrode And a step of forming a drain region and a source region.
According to another aspect of the present invention, there is provided a semiconductor device including: an element formation region provided with a semiconductor element; and an element isolation region provided with an element isolation layer that insulates and isolates adjacent semiconductor elements. A semiconductor element includes a gate electrode formed on a semiconductor substrate in the element formation region via a gate oxide film, a drain region provided at a position sandwiching a channel region below the gate oxide film on the surface of the semiconductor substrate, and The gate oxide film has a high-thickness portion thicker than other portions at both ends in the gate length direction, and the element isolation layer and the high-thickness portion are common. Each LOCOS film is formed by dividing the LOCOS film.

According to the MOS type semiconductor device of the present invention, an element isolation layer that does not contain a bird's beak can be formed, and the gate breakdown voltage can be improved as compared with a conventional MOS type semiconductor device of the same size.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.
(First embodiment)
FIG. 2 is a sectional view of the semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the present embodiment includes an element formation region 100 and an element isolation region 200. A MOSFET is formed in the element isolation region 100, and the MOSFET and other adjacent ones are disposed in the element isolation region 200. An element isolation layer 14b made of SiO2 that electrically isolates the semiconductor element is formed.
In the element formation region 100, a gate electrode 16 is formed on a p-type silicon substrate 10 via a gate oxide film 15 made of SiO2. The gate electrode 15 is made of, for example, polysilicon. On the surface of the silicon substrate 10, n-type low-concentration impurity diffusion regions 18 are formed on both sides of the channel region immediately below the gate oxide film 15. An n-type high concentration impurity diffusion region 19 having an impurity concentration higher than this is formed in the low concentration impurity diffusion region 18. That is, the high concentration impurity diffusion region 19 is formed at a position farther from the channel region in the gate length direction than the low concentration impurity diffusion region 18 and shallower than the low concentration impurity diffusion region 18. The low concentration impurity diffusion region 18 and the high concentration impurity diffusion region 19 function as the source or drain of the MOSFET. By interposing the low-concentration impurity diffusion region 18 between the high-concentration impurity diffusion region 19 and the channel region, the electric field in the vicinity of the end of the high-concentration impurity diffusion region is relaxed, and the breakdown voltage between the drain and the source is improved. Can do.
The gate oxide film 15 is formed such that both end portions in the gate length direction are thicker than the central portion, and the edge of the high-concentration impurity diffusion region 19 is directly below the thick portion (hereinafter referred to as the high-thickness portion 14a). The part is located. Thus, by interposing the high-thickness portion 14a between the gate electrode 16 and the end portion of the high-concentration impurity diffusion region 19, the gate when a voltage is applied between the gate and the drain or between the gate and the source. The electric field applied to the oxide film can be relaxed, and the gate breakdown voltage can be improved as compared with the conventional MOSFET.
In the element isolation region 200 located at both ends of the MOSFET having such a structure, an element isolation layer 14b made of SiO 2 is provided to electrically isolate the MOSFET from other adjacent semiconductor elements. Yes. The element isolation layer 14b is formed by using the LOCOS method as will be described later, but has a structure not including a bird's beak, and the area of the element isolation region 200 is reduced as compared with the conventional structure.
A method for manufacturing a semiconductor device according to the present embodiment will be described below. 3 and 4 are cross-sectional views for each manufacturing process of the semiconductor device according to the first embodiment of the present invention.
First, a p-type silicon wafer is washed with an acid solution, rinsed with ultrapure water, and then dried with a centrifugal dryer. Next, the cleaned wafer is carried into a furnace set at an atmospheric temperature of 900 ° C., for example, and oxygen and silicon are reacted to grow a pad oxide film (SiO 2) 11 on the silicon substrate 10. Thereafter, a silicon nitride film (Si3N4) 12 is deposited on the pad oxide film (SiO2) 11 by a thermochemical reaction between silane (SiH4) and ammonia (NH3) gas (FIG. 3A).
Next, a resist mask (not shown) is formed on the silicon nitride film 12, and the silicon nitride film 12 is patterned by dry etching. At this time, in the next step, the pad oxide film 11 where the LOCOS film 14 is to be formed is exposed (FIG. 3B).
Next, after removing and cleaning the resist mask, a LOCOS film 14 made of SiO2 is selectively grown by thermal oxidation using the acid-resistant silicon nitride film 12 as a mask. Thereafter, the silicon nitride film 12 is removed with hot phosphoric acid (H3PO4), and then the pad oxide film 11 remaining under the silicon nitride film 12 is removed with hydrofluoric acid (HF). Thereafter, a gate oxide film 15 is formed on the channel region of the silicon substrate 10 sandwiched between the LOCOS films 14 by thermal oxidation (FIG. 3C).

Next, a polysilicon film 16a is deposited so as to cover the gate oxide film 15 and the LOCOS film 14 by LP-CVD or the like using silane (SiH4) as a reaction gas (FIG. 3D). Thereafter, an appropriate amount of phosphorus (P) may be added into the polysilicon film 16a in order to lower the electrical resistance of the polysilicon film 16a.
Next, a resist mask (not shown) is formed on the polysilicon film 16a, and the polysilicon film 16a is patterned by dry etching to form the gate electrode 16. At this time, patterning is performed so that the end of the gate electrode 16 is positioned on a relatively thick part of the end of the LOCOS film 14 (FIG. 3E).

Next, a resist mask 17 is formed on the patterned gate electrode 16 and the portion where the element isolation layer 14b is formed on the LOCOS film 14 (FIG. 4F). Subsequently, the LOCOS film 14 exposed from the opening of the resist mask 17 is selectively etched by dry etching. Thereby, the LOCOS film 14 is divided into a high-thickness portion 14 a thicker than the thickness of the gate oxide film 15 constituting the end of the gate oxide film 15 and an element isolation layer 14 b extending in the element isolation region 200. Is done. As described above, the element isolation layer 14b is formed by selectively etching the LOCOS film 14, and the end portion processing is performed by such etching, so that the structure does not include a bird's beak. The silicon substrate 10 is exposed at the portion where the LOCOS film 14 has been removed by this etching (FIG. 4G).
Next, phosphorus ions (31P +) are implanted into the exposed surface of the silicon substrate 10 using the element isolation layer 14b and the gate electrode 16 as a mask, and an n-type low level is formed in a self-aligned manner with respect to the gate electrode 16 and the element isolation layer 14b. A concentration impurity diffusion region 18 is formed. The ion implantation energy at this time is, for example, 180 KeV, the dose amount is 5.0 × 10 12 to 1.0 × 10 13 cm −2, and the tilt angle is set to 45 °, for example. The tilt angle is an angle at which the normal and the ion beam intersect when the normal of the wafer surface is set at the center of the wafer (FIG. 4 (h)).
Subsequently, arsenic ions (75As +) are implanted using the element isolation region 14b and the gate electrode 16 as a mask to form an n-type high concentration impurity diffusion region 19 in a self-aligned manner with respect to the gate electrode 16 and the element isolation layer 14b. . The ion implantation energy at this time is, for example, 40 KeV, the dose amount is 6.0 × 10 15 cm −2, and the tilt angle is set to, for example, 0 ° (FIG. 4 (i)). By thus forming the high concentration impurity diffusion region 19 in a self-aligning manner using the gate electrode 16 and the element isolation layer 14b as a mask, the overlap amount between the gate region and the high concentration impurity diffusion region 19 is reduced, and the gate oxide film It is possible to position the end portion of the high-concentration impurity diffusion region 19 below the high-thickness portion formed at both end portions. After the ion implantation, the wafer is annealed at 800 to 900 ° C. to recover the crystal damage caused by the ion implantation and to activate the implanted ions.
After that, an interlayer insulating film is formed on the wafer, contact holes for extracting electrodes are formed in the gate, source, and drain regions, and an AL for wiring is formed thereon by a vapor deposition method, a sputtering method, etc. Patterning is performed. Then, sintering is performed in a forming gas atmosphere of hydrogen (H 2) and nitrogen (N 2) to complete a MOS type semiconductor device.
As described above, according to the MOS type semiconductor device of the present embodiment, thick portions (high film thickness portions) are formed at both ends of the gate oxide film, and a high concentration is formed immediately below the high film thickness portion. Since the edge of the impurity diffusion region is positioned, the distance between the gate electrode and the high concentration impurity diffusion region is widened, and the electric field is reduced when a voltage is applied between the gate electrode and the high concentration impurity diffusion region. As a result, the gate can have a higher breakdown voltage than a conventional device having the same size.
In addition, according to the method for manufacturing a MOS semiconductor device according to the present embodiment, the high-thickness portion and the element isolation layer can be formed by a batch process using a common LOCOS film, so that the manufacturing process is complicated. There is no harmful effect of becoming. Further, since the element isolation layer is formed through the etching process of the LOCOS film, and the edge process is performed by this etching, a structure including no bird's beak can be obtained. Therefore, the area of the element isolation region can be reduced as compared with the conventional structure using the conventional LOCOS film as the element isolation layer as it is, and the element can be miniaturized.

(Second embodiment)
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. The semiconductor device according to the second example is different from the configuration of the first example in that a polysilicon wiring 20 is formed on the element isolation layer 14b. The process from the formation of the LOCOS film 14 and the gate oxide film 15 on the silicon substrate 10 to the step of covering the entire surface with the polysilicon film 16a is the same as in the first embodiment. FIGS. 5A to 5D are cross-sectional views for each manufacturing process of the MOS type semiconductor device according to the second embodiment, and show processes after the formation process of the polysilicon film 16a.
After the polysilicon film 16a is formed on the entire surface of the silicon substrate 10, a resist mask 30 is formed on the gate electrode formation portion in the element formation region 100 and the polysilicon film 16a in the wiring formation portion in the element isolation region 200. (FIG. 5 (a)).
Next, the polysilicon film 16 a is etched and patterned through the resist mask 30 to form the gate electrode 16 in the element formation region 100 and the polysilicon wiring 20 in the element isolation region 200. At this time, patterning is performed so that the end portion of the gate electrode 16 is positioned on the relatively thick portion of the end portion of the LOCOS film 14 (FIG. 5B).
Subsequently, the LOCOS film 14 exposed in the opening of the resist mask 30 is selectively etched. As a result, the LOCOS film 14 is divided into a high-thickness portion 14 a of a relatively thick gate oxide film constituting the end portion of the gate oxide film 15 and an element isolation layer 14 b extending in the element isolation region 200. The As described above, the element isolation layer 14b is formed by selectively etching the LOCOS film 14, and the end portion processing is performed by such etching, so that the structure does not include a bird's beak. The silicon substrate 10 is exposed in the portion where the LOCOS film 14 has been removed by this etching (FIG. 5C).
Next, after removing the resist mask 30, phosphorus ions (31P +) are implanted into the exposed surface of the silicon substrate 10 using the polysilicon wiring 20 and the gate electrode 16 as a mask, so that the gate electrode 16 and the element isolation layer 14b are implanted. An n-type low concentration impurity diffusion region 18 is formed in a self-aligning manner. The ion implantation energy at this time is, for example, 180 KeV, the dose amount is 5.0 × 10 12 to 1.0 × 10 13 cm −2, and the tilt angle is set to 45 °, for example. Subsequently, arsenic ions (75As +) are implanted using the polysilicon wiring 20 and the gate electrode 16 as a mask to form an n-type high concentration impurity diffusion region 19 in a self-aligned manner with respect to the gate electrode 16 and the element isolation layer 14b. . The ion implantation energy at this time is, for example, 40 KeV, the dose amount is 6.0 × 10 15 cm −2, and the tilt angle is set to, for example, 0 ° (FIG. 5D). Thus, by forming the high-concentration impurity diffusion region 19 in a self-aligning manner using the gate electrode 16 and the polysilicon wiring 20 as a mask, the overlap amount between the gate region and the high-concentration impurity diffusion region 19 is reduced, and gate oxidation is performed. It becomes possible to position the end portion of the high concentration impurity diffusion region 19 below the high film thickness portion formed at both ends of the film. After the ion implantation, the wafer is annealed at 800 to 900 ° C. to recover the crystal damage caused by the ion implantation and to activate the implanted ions.
After that, an interlayer insulating film is formed on the wafer, contact holes for extracting electrodes are formed in the gate, source, and drain regions, and an AL for wiring is formed thereon by a vapor deposition method, a sputtering method, etc. Patterning is performed. Then, sintering is performed in a forming gas atmosphere of hydrogen (H 2) and nitrogen (N 2) to complete a MOS type semiconductor device.
Thus, according to the manufacturing method of the MOS type semiconductor device of the second embodiment, the structure including the wiring on the element isolation layer can be obtained. Since such wiring is made of polysilicon, which is the same material as the gate electrode material, the patterning of the gate electrode and the patterning of the wiring on the element isolation layer can be performed in a batch process. In addition, as in this embodiment, the patterning of the wiring on the element isolation layer and the patterning of the element isolation layer are performed using a common mask, so that it is possible to reduce the processing time and the problem of mask misalignment. In addition, the alignment between the element isolation layer and the wiring can be performed with high accuracy.
In each of the above embodiments, the case where an n-channel MOSFET is formed in the element formation region has been described as an example. However, a p-channel MOSFET can also be formed in the element formation region.

It is sectional drawing which shows the structure of the conventional MOS type semiconductor device. 1 is a cross-sectional view showing a structure of a MOS type semiconductor device according to a first embodiment of the present invention. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention. 4 (f) to 4 (i) are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention. 5A to 5D are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 Pad oxide film 12 Silicon nitride film 14 LOCOS film 14a High film thickness part 14b Element isolation layer 15 Gate oxide film 16a Gate electrode 18 Low concentration impurity diffusion region 19 High concentration impurity diffusion region 20 Polysilicon wiring

Claims (7)

A method for manufacturing a semiconductor device, comprising: an element formation region provided with a semiconductor element; and an element isolation region provided with an element isolation layer that insulates and isolates adjacent semiconductor elements.
Forming a LOCOS film extending from the element formation region to the element division region on the surface of the semiconductor substrate;
Forming a gate oxide film connected to the LOCOS film on the semiconductor substrate in the element formation region;
Forming a conductive film so as to cover the LOCOS film and the gate oxide film;
Partially etching the conductive film to form a gate electrode that covers part of the gate oxide film and the LOCOS film;
Partially etching the LOCOS film exposed by etching of the conductive film to divide the LOCOS film into the element isolation layer and a high-thickness portion constituting the end of the gate oxide film;
Forming a drain region and a source region at positions sandwiching the gate electrode by performing ion implantation on the surface of the semiconductor substrate exposed by etching the LOCOS film. The step of forming the drain region and the source region includes
A first implantation step of forming a low-concentration impurity diffusion region by implanting ions of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask;
Impurities having the same conductivity type as the low-concentration impurity diffusion region are ion-implanted into the semiconductor substrate using the gate electrode as a mask, and the high-concentration impurity diffusion region having a higher impurity concentration than the low-concentration impurity region is used as the low-concentration impurity region. The method for manufacturing a semiconductor device according to claim 1, further comprising a second implantation step formed in the semiconductor device.   The method of manufacturing a semiconductor device according to claim 2, wherein the first implantation step and the second implantation step are performed by ion implantation at different irradiation angles. A method for manufacturing a semiconductor device, comprising: an element formation region provided with a semiconductor element; and an element isolation region provided with an element isolation layer that insulates and isolates adjacent semiconductor elements.
Forming a LOCOS film extending from the element formation region to the element division region on the surface of the semiconductor substrate;
Forming a gate oxide film connected to the LOCOS film on the semiconductor substrate in the element formation region;
Forming a conductive film so as to cover the LOCOS film and the gate oxide film;
Partially etching the conductive film to form a gate electrode that covers part of the gate oxide film and the LOCOS film and a wiring part that covers the LOCOS film in the element isolation region;
Partially etching the LOCOS film exposed by etching the conductive film to divide the LOCOS film into the element isolation layer and a high-thickness portion constituting the end of the gate oxide film;
And a step of ion-implanting the surface of the semiconductor substrate exposed by etching the LOCOS film to form a drain region and a source region on both sides of the gate electrode. The step of forming the drain region and the source region includes
A first implantation step of forming a low-concentration impurity diffusion region by ion-implanting impurities of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode and the wiring portion as a mask;
Using the gate electrode and the wiring portion as a mask, an impurity having the same conductivity type as that of the low concentration impurity diffusion region is ion-implanted into the semiconductor substrate to form a high concentration impurity diffusion region having a higher impurity concentration than the low concentration impurity region. The method of manufacturing a semiconductor device according to claim 4, further comprising a second implantation step formed in the low concentration impurity region. A semiconductor device including an element formation region provided with a semiconductor element and an element isolation region provided with an element isolation layer that insulates and isolates adjacent semiconductor elements.
The semiconductor element is
A gate electrode formed on a semiconductor substrate in the element formation region via a gate oxide film;
A drain region and a source region provided at a position sandwiching a channel region below the gate oxide film on the semiconductor substrate surface,
The gate oxide film has a high-thickness portion thicker than other portions at both ends in the gate length direction,
The element isolation layer and the high-thickness portion are formed by dividing a common LOCOS film, respectively. The drain region and the source region are
A pair of low-concentration impurity diffusion regions containing impurities of a conductivity type different from the conductivity type of the semiconductor substrate provided at a position sandwiching a channel region below the gate oxide film on the surface of the semiconductor substrate;
Each of the low-concentration impurity diffusion regions is provided at a position separated from the channel region in the gate length direction, has the same conductivity type as the low-concentration impurity diffusion region, and is lower than the low-concentration impurity diffusion region A pair of high-concentration impurity diffusion regions containing high-concentration impurities,
6. The semiconductor device according to claim 5, wherein each of the end portions of the high-concentration impurity diffusion region facing each other across the channel region is located below the high-thickness portion.

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