JP2009004554A - Mos semiconductor device and manufacturing process of mos semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS semiconductor device that can improve gate voltage resistance and source-to-drain voltage resistance in comparison with the MOS semiconductor device of the same size in the related art and also provide manufacturing process of the MOS semiconductor device. <P>SOLUTION: The MOS semiconductor device includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, a pair of low concentration impurity diffusing regions provided, within inclusion of an impurity in the conductivity type different from that of the semiconductor substrate, at the locations sandwiching a channel region at the lower side of the gate oxide film within the semiconductor substrate, and a pair of high concentration impurity diffusing region separated, with inclusion of an impurity in the conductivity type same as that the low concentration impurity diffusion region and having concentration higher than that of the low concentration impurity diffusing region, from a channel region in the gate length direction of the gate electrode within each low concentration impurity diffusing region. In this MOS semiconductor device, the gate oxide film includes a thick film part thicker than the other portions in both end portions in the gate length direction of the gate electrode and each of the end portions facing with each other in both sides of the channel region of the high concentration impurity diffusion region is located just under the thick film part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a MOS type semiconductor device and a manufacturing method thereof.

  A MOS type semiconductor device having a MOS (Metal-Oxide-Semiconductor) structure is known. FIG. 1 shows the structure of a MOS type semiconductor device described in Patent Document 1, and a manufacturing method thereof will be described. First, a photomask is formed on the P-type semiconductor substrate 1, 31P + is implanted therein to form a low concentration impurity diffusion region 2, and then 75As + is implanted to form a high concentration impurity diffusion region 3, 31P + and 75As + are activated by heat treatment. Next, a wet oxide film 4 is formed on the surface of the P-type semiconductor substrate 1. At this time, since the high concentration impurity diffusion region 3 has a higher impurity concentration than the channel region and the low concentration impurity diffusion region 2, the growth of the wet oxide film 4 on the high concentration impurity diffusion region 3 is promoted. The thickness is thicker than other areas. A polycrystalline silicon film is deposited on the surface of the wet oxide film 4 formed in this way, and this is dry etched to form the gate electrode 5. Thereafter, the portion of the wet oxide film where the gate electrode 5 is not formed is removed, the gate oxide film is left, and the source / drain electrodes are formed on the high-concentration impurity diffusion region 3 to complete.

As described above, in the MOS type semiconductor device described in Patent Document 1, the wet oxide films having different thicknesses are formed on the high-concentration impurity diffusion region and the low-concentration impurity diffusion region, whereby the gate oxide film having the lowest breakdown voltage is formed. The gate breakdown voltage is increased by increasing the thickness at both ends, and the gate oxide film is shortened as compared with the prior art by removing the wet oxide film where the gate electrode is not formed, thereby miniaturizing the device.
JP 7-66400 A

  However, although the MOS type semiconductor device described in Patent Document 1 is configured to increase the thickness of both ends of the gate oxide film for the purpose of improving the gate breakdown voltage, the end of the high concentration impurity diffusion region is formed. Is located immediately below the thin part of the wet oxide film, so that when a voltage is applied between the gate and drain and between the gate and source, an electric field is applied to the thin part of the gate oxide film, It was difficult to obtain a desired gate breakdown voltage.

  Conventionally, the low concentration impurity diffusion region is introduced for the purpose of improving the drain-source breakdown voltage by relaxing the electric field in the vicinity of the end portion of the high concentration impurity diffusion region. In the method of manufacturing the MOS type semiconductor device, since the high concentration impurity diffusion region and the low concentration impurity diffusion region are formed by ion implantation using the same photomask, the low concentration is formed from the end of the high concentration impurity diffusion region. The distance L to the end of the impurity diffusion region, that is, the length of the portion where the low-concentration impurity diffusion region bears the electric field relaxation effect is determined by the difference between the diffusion coefficients of the two types of implanted impurities and the heat treatment after ion implantation. Therefore, it is difficult to control the distance L, and therefore there is a limit to increasing the breakdown voltage between the drain and the source.

  The present invention has been made in view of the above points, and a MOS semiconductor device capable of improving a gate breakdown voltage and a source-drain breakdown voltage as compared with a conventional MOS semiconductor device of the same size, and its manufacture. It aims to provide a method.

  A first aspect of a MOS type semiconductor device according to the present invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and a channel region below the gate oxide film inside the semiconductor substrate. A pair of low-concentration impurity diffusion regions including impurities having a conductivity type different from the conductivity type of the semiconductor substrate, and a gate of the gate electrode in each of the low-concentration impurity diffusion regions A pair of high-concentration impurity diffusion regions that are spaced apart from the channel region in the longitudinal direction and have the same conductivity type as the low-concentration impurity diffusion region and that contain a higher concentration of impurities than the low-concentration impurity diffusion region; In the MOS type semiconductor device, the gate oxide film has a high-thickness portion thicker than other portions at both ends of the gate electrode in the gate length direction. Each of opposite ends across the channel region of the high concentration impurity diffusion region is characterized by being located directly below the high thickness portion.

  According to a second aspect of the MOS semiconductor device of the present invention, there is provided a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and a portion below the gate oxide film inside the semiconductor substrate. A pair of low-concentration impurity diffusion regions including impurities of a conductivity type different from the conductivity type of the semiconductor substrate provided at a position sandwiching the channel region; and the gate electrode in each of the low-concentration impurity diffusion regions A pair of high-concentration impurity diffusion regions that are spaced apart from the channel region in the gate length direction, have the same conductivity type as the low-concentration impurity diffusion region, and contain a higher concentration of impurities than the low-concentration impurity diffusion region; A pair of spacers provided on the side wall of the gate electrode and facing each other in the gate length direction of the gate electrode. Thus, the gate oxide film has a high-thickness portion thicker than other portions at both ends in the gate length direction of the gate electrode, and sandwiches the channel region of the high-concentration impurity diffusion region. Each of the facing end portions is located immediately below each end portion of the spacer.

  A third aspect of the MOS type semiconductor device according to the present invention is a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and an interior of the semiconductor substrate below the gate oxide film. A pair of low-concentration impurity diffusion regions including impurities of a conductivity type different from the conductivity type of the semiconductor substrate provided at a position sandwiching the channel region; and the gate electrode in each of the low-concentration impurity diffusion regions A pair of high-concentration impurity diffusion regions that are spaced apart from the channel region in the gate length direction, have the same conductivity type as the low-concentration impurity diffusion region, and contain a higher concentration of impurities than the low-concentration impurity diffusion region; A pair of spacers provided on the side wall of the gate electrode and facing each other in the gate length direction of the gate electrode. Thus, the gate oxide film has a high-thickness portion thicker than other portions at both ends in the gate length direction of the gate electrode, and sandwiches the channel region of the high-concentration impurity diffusion region. Each of the facing end portions is located immediately below each end portion of the spacer.

  The manufacturing method of the MOS type semiconductor device according to the present invention is the manufacturing method of the MOS type semiconductor device according to the first aspect, wherein a first oxide film forming step of forming an oxide film on the semiconductor substrate by thermal oxidation, A second oxide film forming step of forming an oxide film thicker than the oxide film at both ends of the oxide film; and a gate electrode material on the oxide film formed in the first and second oxide film forming steps. A step of patterning the oxide film and the gate electrode material formed in the first and second oxide film forming steps to form the gate electrode and the gate oxide film, and using the gate electrode as a mask Implanting impurities of a conductivity type different from the conductivity type of the semiconductor substrate into the semiconductor substrate to form the low-concentration impurity diffusion region; and using the gate electrode as a mask A step of forming the high concentration impurity diffusion region by injecting an impurity of the same conductivity type as the impurity diffusion region and having a higher concentration than the low concentration impurity diffusion region into the semiconductor substrate. Yes.

  The method for manufacturing a MOS type semiconductor device according to the present invention is the method for manufacturing the MOS type semiconductor device according to the second aspect, wherein the oxide film is formed on the semiconductor substrate by thermal oxidation. A second oxide film forming step of forming an oxide film thicker than the oxide film at both ends in the gate length direction of the oxide film, and an oxide film formed in the first and second oxide film forming steps Depositing a gate electrode material thereon, patterning the oxide film formed in the first and second oxide film forming steps and the gate electrode material to form the gate electrode and the gate oxide film, Forming a low-concentration impurity diffusion region by implanting an impurity of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask; and Forming the spacer on the wall; and using the gate electrode and the spacer as a mask, the semiconductor substrate has the same conductivity type as the low-concentration impurity diffusion region and has a higher concentration than the low-concentration impurity diffusion region And forming the high-concentration impurity diffusion region.

  The method for manufacturing a MOS semiconductor device according to the present invention is the method for manufacturing the MOS semiconductor device according to the third aspect, wherein the oxide film is formed on the semiconductor substrate by thermal oxidation. A second oxide film forming step of forming an oxide film having a thickness larger than that of the oxide film at one end in the gate length direction of the oxide film, and the first and second oxide film forming steps. Depositing a gate electrode material on the oxide film, and patterning the oxide film and the gate electrode material formed in the first and second oxide film forming processes to form the gate electrode and the gate oxide film And forming a low-concentration impurity diffusion region by implanting an impurity having a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask, and the gate Forming the spacer on the side wall of the pole, and using the gate electrode and the spacer as a mask, the impurity having the same conductivity type as the low-concentration impurity diffusion region and having a higher concentration than the low-concentration impurity diffusion region And a step of forming the high-concentration impurity diffusion region by implanting the semiconductor substrate.

  According to the MOS type semiconductor device of the present invention, the gate breakdown voltage and the source-drain breakdown voltage can be improved as compared with a conventional MOS type semiconductor device of the same size.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.
(First embodiment)
FIG. 2 is a sectional view of a MOS type semiconductor device according to the first embodiment of the present invention. The MOS type semiconductor device according to this embodiment is, for example, an N channel type MOSFET, and a gate electrode 14 is formed on a P type silicon substrate 10 via a gate oxide film 13 made of SiO ₂ . The gate electrode 14 is made of, for example, polysilicon. N-type low-concentration impurity diffusion regions 12 are formed on the surface of the silicon substrate 10 on both sides of the channel region formed immediately below the gate oxide film 13. A high-concentration N-type high-concentration impurity diffusion region 11 is formed. That is, the high concentration impurity diffusion region 11 is formed at a position farther from the channel region in the gate length direction than the low concentration impurity diffusion region 12 and shallower than the low concentration impurity diffusion region 12. The high-concentration impurity diffusion region 11 functions as a source / drain region. By interposing the low-concentration impurity diffusion region 12 between the high-concentration impurity diffusion region 11 and the channel region, the electric field in the vicinity of the end of the high-concentration impurity diffusion region is relaxed, and the breakdown voltage between the drain and the source is improved. Can do.

  The gate oxide film 13 is formed such that the gate length direction both end portions 13a having the lowest breakdown voltage are thicker than the center portion, and the end portions of the high-concentration impurity diffusion regions 11 are located immediately below the thick end portions 13a. is doing. Thus, a voltage is applied between the gate and the drain or between the gate and the source by interposing the thick part of the gate oxide film between the gate electrode 14 and the end of the high concentration impurity diffusion region. The electric field applied to the gate oxide film can be relaxed, and the gate breakdown voltage can be improved as compared with the conventional MOS type semiconductor device.

FIG. 3 shows a manufacturing process diagram of the MOS semiconductor device according to the first embodiment of the present invention. Hereinafter, a method for manufacturing a MOS semiconductor device according to the present embodiment will be described with reference to FIG. First, a P-type silicon wafer is washed with an acid solution, rinsed with ultrapure water, and then dried with a centrifugal dryer. Next, the cleaned wafer is carried into a furnace set at an atmospheric temperature of 900 ° C., for example, and oxygen and silicon are reacted to grow an oxide film (SiO ₂ ) 13 on the silicon substrate 10. Thereafter, a silicon nitride film (Si ₃ N ₄ ) 20 is deposited on the oxide film (SiO ₂ ) 13 by a thermochemical reaction between silane (SiH ₄ ) and ammonia (NH ₃ ) gas (FIG. 3A).

Next, a photomask is formed on the silicon nitride film 20, and the silicon nitride film (Si ₃ N ₄ ) 20 is patterned by dry etching. At this time, the oxide film (SiO ₂ ) 13 where the field oxide film is to be formed in the next process is exposed (FIG. 3B).

Next, after removing the photomask and washing, a field oxide film (SiO ₂ ) 13a is partially formed by thermal oxidation using the acid-resistant silicon nitride film (Si ₃ N ₄ ) 20 as a mask, and the remaining The silicon nitride film (Si ₃ N ₄ ) 20 is removed with hot phosphoric acid (H ₃ PO ₄ ) (FIG. 3C).

Next, a polysilicon film 14 is deposited on the SiO 2 films 13 and 13a by the LP-CVD method using silane (SiH ₄ ) as a reaction gas (FIG. 3D). Thereafter, phosphorus (P) may be added by a diffusion method or the like in order to lower the electrical resistance of the polysilicon film 14.

Next, a photomask is formed on the polysilicon film 14, and the gate electrode is patterned by dry etching. Thereafter, the field oxide film (SiO ₂ ) 13a is etched using the patterned gate electrode as a mask. At this time, patterning is performed so that the field oxide film (SiO ₂ ) 13a formed in the previous step forms both end portions of the gate oxide film (FIG. 3E).

  Next, phosphorus (P) is ion-implanted using the patterned gate electrode 14 as a mask to form an N-type low-concentration impurity diffusion region 12 in a self-aligned manner with respect to the gate electrode 14. The implantation energy at this time is, for example, 180 KeV, the dose is 5.0E12 to 1.0E13 cm−2, and the tilt angle is set to 45 °, for example. The tilt angle is an angle at which the normal and the ion beam intersect when the normal of the wafer surface is set at the center of the wafer (FIG. 3 (f)).

  Further, arsenic (As) is ion-implanted using the gate electrode 14 as a mask to form an N-type high concentration impurity diffusion region 11 in a self-aligned manner with respect to the gate electrode 14. The implantation energy at this time is, for example, 40 KeV, the dose amount is 6.0E15 cm −2, and the tilt angle is set to, for example, 0 ° (FIG. 3G). By thus forming the high concentration impurity diffusion region 11 in a self-aligning manner using the gate electrode 14 as a mask, the amount of overlap between the gate region and the high concentration impurity diffusion region 11 is reduced, and the gate oxide film has both ends 13a. The end portion of the high-concentration impurity diffusion region 11 is located below the formed thick portion. After the ion implantation, the wafer is annealed at 800 to 900 ° C. to recover the crystal damage caused by the ion implantation and to activate the implanted ions.

After that, an interlayer insulating film is formed on the wafer, contact holes for extracting electrodes are formed in the gate, source, and drain regions, and an AL for wiring is formed thereon by a vapor deposition method, a sputtering method, etc. Patterning is performed. Then, sintering is performed in a forming gas atmosphere of hydrogen (H ₂ ) and nitrogen (N ₂ ) to complete a MOS type semiconductor device.

  As is apparent from the above description, according to the MOS type semiconductor device of the first embodiment of the present invention, thick portions are formed at both ends of the gate oxide film using the conventional LOCOS forming method. Since the end portion of the high concentration impurity diffusion region is located immediately below the thick portion of the gate oxide film, the distance between the gate electrode and the high concentration impurity diffusion region is widened, The electric field when a voltage is applied to the impurity diffusion region is alleviated, and the gate can have a higher breakdown voltage than a conventional device having the same size.

(Second embodiment)
FIG. 4 is a sectional view of a MOS type semiconductor device according to the second embodiment of the present invention. The MOS type semiconductor device according to this embodiment is, for example, an N channel type MOSFET, and a gate electrode 14 is formed on a P type silicon substrate 10 via a gate oxide film 13 made of SiO2. The gate electrode 14 is made of, for example, polysilicon. A pair of sidewall spacers 15 facing each other in the gate length direction are formed on the side wall portion of the gate electrode 14. The sidewall spacer 15 is formed of an insulator such as SiO ₂ . N-type low-concentration impurity diffusion regions 12 are formed on the surface of the silicon substrate 10 on both sides of the channel region formed immediately below the gate oxide film 13. A high-concentration N-type high-concentration impurity diffusion region 11 is formed. That is, the high-concentration impurity diffusion region 11 is formed at a position farther from the channel region in the gate length direction than the low-concentration impurity diffusion region 12, is formed shallower than the low-concentration impurity diffusion region 12, and has an end portion thereof. It is located directly below the end of the sidewall spacer 15. A source / drain region is formed by the high concentration impurity diffusion region 11. By interposing the low-concentration impurity diffusion region 12 between the high-concentration impurity diffusion region 11 and the channel region, the electric field in the vicinity of the end portion of the high-concentration impurity diffusion region is relaxed, and the breakdown voltage between the drain and the source is improved. It becomes possible.

  The gate oxide film 13 is formed such that the gate length direction both end portions 13a having the lowest breakdown voltage are formed thicker than the central portion, thereby ensuring the gate breakdown voltage. In this embodiment, the side wall spacer 15 is formed on the side wall portion of the gate electrode 14 as described above, and the end portion of the high concentration impurity diffusion region 11 is located immediately below the end portion of the side wall spacer 15. Therefore, the distance L1 from the end of the high concentration diffusion region 11 to the end of the low concentration diffusion region 12 is longer than that described in the first embodiment. Thereby, the electric field relaxation effect by the low concentration impurity diffusion region 12 is increased, and the drain-source breakdown voltage can be improved. Furthermore, inclined portions 50 are formed on the surface of the silicon substrate 10 on the source side and the drain side from the end portion of the high concentration impurity diffusion region 11 to the end portion of the low concentration diffusion region 12, respectively. This can be a factor for increasing the distance between the impurity diffusion region 11 and the low-concentration impurity diffusion region 12.

FIG. 5 shows a manufacturing process diagram of the MOS type semiconductor device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing a MOS semiconductor device according to this embodiment will be described with reference to FIG. First, a P-type silicon wafer is washed with an acid solution, rinsed with ultrapure water, and then dried with a centrifugal dryer. Next, the cleaned wafer is carried into a furnace set at an atmospheric temperature of 900 ° C., for example, and oxygen and silicon are reacted to grow an oxide film (SiO ₂ ) 13 on the silicon substrate 10. Thereafter, a silicon nitride film (Si ₃ N ₄ ) 20 is deposited on the oxide film (SiO ₂ ) 13 by a thermochemical reaction between silane (SiH ₄ ) and ammonia (NH ₃ ) gas (FIG. 5A).

Next, a photomask is formed on the silicon nitride film 20, and the silicon nitride film (Si ₃ N ₄ ) 20 is patterned by dry etching. At this time, the oxide film (SiO ₂ ) 13 where the field oxide film is to be formed in the next process is exposed (FIG. 5B).
Next, after removing the photomask and washing, a field oxide film (SiO ₂ ) 13a is partially formed by thermal oxidation using the acid-resistant silicon nitride film (Si ₃ N ₄ ) 20 as a mask, and the remaining The silicon nitride film (Si ₃ N ₄ ) 20 is removed with hot phosphoric acid (H ₃ PO ₄ ) (FIG. 5C).

Next, a polysilicon film 14 is deposited on the SiO ₂ films 13 and 13a by an LP-CVD method using silane (SiH ₄ ) as a reaction gas (FIG. 5D). Thereafter, phosphorus (P) may be added by a diffusion method or the like in order to lower the electrical resistance of the polysilicon film 14.

Next, a photomask is formed on the polysilicon film 14, and the gate electrode is patterned by dry etching. Thereafter, the field oxide film (SiO ₂ ) 13a is etched using the patterned gate electrode as a mask. At this time, patterning is performed so that the field oxide film (SiO ₂ ) 13a formed in the previous step forms both end portions of the gate oxide film (FIG. 5E).

  Next, phosphorus (P) is ion-implanted using the patterned gate electrode 14 as a mask to form an N-type low-concentration impurity diffusion region 12 in a self-aligned manner with respect to the gate electrode 14. The implantation energy at this time is, for example, 180 KeV, the dose is 5.0E12 to 1.0E13 cm−2, and the tilt angle is set to 45 °, for example (FIG. 5F).

  Next, a SiO 2 film having conformal, that is, isotropic step coverage is deposited on the wafer, and anisotropic etching mainly composed of a vertical component is performed by RIE (reactive ion etching), whereby the side wall of the gate electrode 14 is formed. Sidewall spacers 15 are formed on the portions. Here, the width dimension of the sidewall spacer 15 is controlled by its height. The MOS type semiconductor device according to the present embodiment has these steps by the level difference d1 formed on the silicon substrate 10 when the field oxide film 13a is formed and the level difference d2 at both ends of the gate oxide film. Compared to a conventional device that is not, the overall height d3 of the sidewall spacer 15 can be increased, and accordingly, the width dimension L0 of the sidewall spacer 15 can be increased (FIG. 5G).

  Next, arsenic (As) is ion-implanted using the gate electrode 14 and the sidewall spacer 15 as a mask to form the N-type high concentration impurity diffusion region 11 in a self-aligning manner. The implantation energy at this time is, for example, 40 KeV, the dose amount is 6.0E15 cm−2, and the tilt angle is set to, for example, 0 ° (FIG. 5 (h)). After the ion implantation, the wafer is annealed at 800 to 900 ° C. to recover the crystal damage caused by the ion implantation and to activate the implanted ions.

After that, an interlayer insulating film is formed on the wafer, contact holes for extracting electrodes are formed in the gate, source, and drain regions, and an AL for wiring is formed thereon by a vapor deposition method, a sputtering method, etc. Patterning is performed. Then, sintering is performed in a forming gas atmosphere of hydrogen (H ₂ ) and nitrogen (N ₂ ) to complete a MOS type semiconductor device.

  As is apparent from the above description, according to the MOS type semiconductor device of the second embodiment of the present invention, thick portions are formed at both ends of the gate oxide film using the conventional LOCOS formation method. Therefore, the gate breakdown voltage is secured. In addition, after forming the low concentration impurity diffusion region, a sidewall spacer is formed on the side wall of the gate electrode, and this is used as a mask to form the high concentration impurity diffusion region. Therefore, the low concentration impurity diffusion region is formed from the end of the high concentration impurity diffusion region. The distance L1 to the end of the region can be increased, the electric field relaxation effect by the low-concentration impurity diffusion region 12 can be increased, and the drain-source breakdown voltage can be improved. Further, as described above, in the MOS type semiconductor device of the present invention, the width L0 of the sidewall spacer can be increased, and a more remarkable breakdown voltage improvement effect can be expected as compared with the conventional structure.

(Example 3)
FIG. 6 is a sectional view of a MOS type semiconductor device according to the third embodiment of the present invention. The MOS type semiconductor device according to this embodiment is, for example, an N channel type MOSFET, and a gate electrode 14 is formed on a P type silicon substrate 10 via a gate oxide film 13 made of SiO2. The gate electrode 14 is made of, for example, polysilicon. A pair of sidewall spacers 15 facing each other in the gate length direction are formed on the side wall portion of the gate electrode 14. The sidewall spacer 15 is formed of an insulator such as SiO 2. On the surface of the silicon substrate 10, N-type low-concentration impurity diffusion regions 12 are formed on both sides of the gate electrode 14, and an N-type high-concentration having a higher impurity concentration is formed in the low-concentration impurity diffusion region 12. An impurity diffusion region 11 is formed. That is, the high-concentration impurity diffusion region 11 is formed at a position farther from the channel region than the low-concentration impurity diffusion region 12, is formed shallower than the low-concentration impurity diffusion region 12, and an end thereof is the sidewall spacer 15. It is located directly under the edge of the. The high concentration impurity diffusion region 11 forms a source / drain region. By interposing the low-concentration impurity diffusion region 12 between the source / drain region and the channel region, the electric field in the vicinity of the end of the high-concentration impurity diffusion region can be relaxed and the breakdown voltage between the source and drain can be improved. It becomes possible.

  The MOS type semiconductor device according to the present embodiment has an asymmetric structure, and an inclined portion 50 is provided on the surface of the silicon substrate from the drain region on the right side to the channel region in the drawing, while the source region on the left side in the drawing is shown. A flat surface is formed from the channel region to the channel region. Further, the gate oxide film 13 is formed with a thick portion 13a only at the end on the drain side in the gate length direction. Such an asymmetric structure is brought about by forming a field oxide film only on the drain side in the manufacturing process described later. Accordingly, the height and width dimensions of the sidewall spacer 15 are higher on the source side than on the drain side. Is also getting smaller. Since the sidewall 15 functions as a mask when performing ion implantation for forming a high concentration impurity diffusion region in a manufacturing process described later, the side wall 15 starts from the end portion of the high concentration impurity diffusion region 11 on the source side. The distance L2 to the end of the drain is shortened compared to the corresponding distance L1 on the drain side. As described above, in the MOS type semiconductor device according to this embodiment, the device size is reduced by reducing the size of the source-side sidewall spacer 15 which does not contribute to the high breakdown voltage, and the high concentration from the channel region. Since the distance L2 to the impurity diffusion region 11 is shortened, the source resistance can be reduced.

FIG. 7 shows a manufacturing process diagram of the MOS type semiconductor device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing a MOS semiconductor device according to this embodiment will be described with reference to FIG. First, a P-type silicon wafer is washed with an acid solution, rinsed with ultrapure water, and then dried with a centrifugal dryer. Next, the cleaned wafer is carried into a furnace set at an atmospheric temperature of 900 ° C., for example, and oxygen and silicon are reacted to grow an oxide film (SiO ₂ ) 13 on the silicon substrate 10. Thereafter, a silicon nitride film (Si ₃ N ₄ ) 20 is deposited on the oxide film (SiO ₂ ) 13 by a thermochemical reaction between silane (SiH ₄ ) and ammonia (NH ₃ ) gas (FIG. 7A).

Next, a photomask is formed on the silicon nitride film 20, and the silicon nitride film (Si ₃ N ₄ ) 20 is patterned by dry etching. At this time, the source region is covered with a silicon nitride film (Si ₃ N ₄ ) 20 so that a field oxide film is not formed in the source region in the next step (FIG. 7B).

Next, after removing the photomask and washing, a field oxide film (SiO ₂ ) 13a is partially formed by thermal oxidation using the acid-resistant silicon nitride film (Si ₃ N ₄ ) 20 as a mask, and the remaining The silicon nitride film (Si ₃ N ₄ ) 20 is removed with hot phosphoric acid (H ₃ PO ₄ ) (FIG. 7C).

Next, a polysilicon film 14 is deposited on the SiO 2 films 13 and 13a by LP-CVD using silane (SiH ₄ ) as a reaction gas (FIG. 7D). Thereafter, phosphorus (P) may be added by a diffusion method or the like in order to lower the electrical resistance of the polysilicon film 14.

Next, a photomask is formed on the polysilicon film 14, and the gate electrode is patterned by dry etching. Thereafter, the field oxide film (SiO ₂ ) 13a is etched using the patterned gate electrode as a mask. At this time, patterning is performed so that the field oxide film (SiO ₂ ) 13a formed in the previous step forms an end portion on the drain side of the gate oxide film (FIG. 7E).

  Next, phosphorus (P) is ion-implanted using the patterned gate electrode 14 as a mask to form an N-type low-concentration impurity diffusion region 12 in a self-aligned manner with respect to the gate electrode 14. The implantation energy at this time is, for example, 180 KeV, the dose amount is 5.0E12 to 1.0E13 cm−2, and the tilt angle is set to 45 °, for example (FIG. 7F).

Next, a conformal, ie, isotropic step coverage SiO ₂ film is deposited on the wafer, and anisotropic etching mainly including a vertical component is performed by RIE (reactive ion etching). Sidewall spacers 15 are formed on the side wall portions. In the MOS type semiconductor device according to the present embodiment, the height and width dimension of the drain side sidewall spacer are larger than those on the source side due to the field oxide film 13a formed only on the drain side (FIG. 7G )).

  Next, arsenic (As) is ion-implanted using the gate electrode 14 and the sidewall spacer 15 as a mask to form the N-type high concentration impurity diffusion region 11 in a self-aligning manner. The implantation energy at this time is 40 KeV, the dose is 6.0E15 cm−2, and the tilt angle is set to 0 °, for example (FIG. 7 (h)). After the ion implantation, the wafer is annealed at 800 to 900 ° C. to recover the crystal damage caused by the ion implantation and to activate the implanted ions.

After that, an interlayer insulating film is formed on the wafer, contact holes for extracting electrodes are formed in the gate, source, and drain regions, and an AL for wiring is formed thereon by a vapor deposition method, a sputtering method, etc. Patterning is performed. Then, sintering is performed in a forming gas atmosphere of hydrogen (H ₂ ) and nitrogen (N ₂ ) to complete a MOS type semiconductor device.

  As is apparent from the above description, according to the MOS type semiconductor device of the third embodiment of the present invention, as in the second embodiment, after the low concentration impurity diffusion region is formed, the sidewall is formed on the sidewall of the gate electrode. Since the spacer is formed and the high concentration impurity diffusion region is formed using this as a mask, the drain-source breakdown voltage is improved by increasing the distance from the end of the high concentration impurity diffusion region to the end of the low concentration impurity diffusion region. At the same time, on the source side that does not contribute to high breakdown voltage, it is possible to reduce the device size and the source resistance by shortening this distance from the drain side.

  In each of the above embodiments, the case where the present invention is applied to an N-channel MOSFET has been described as an example. However, the present invention can also be applied to a P-channel MOSFET. In this case, using an N-type silicon substrate, the low concentration impurity diffusion region and the high concentration impurity diffusion region are formed by ion implantation of boron (B) or the like.

It is sectional drawing which shows the structure of the conventional MOS type semiconductor device. 1 is a cross-sectional view showing a structure of a MOS type semiconductor device according to a first embodiment of the present invention. It is a manufacturing process figure which shows the manufacturing method of the MOS type semiconductor device which concerns on 1st Example of this invention. It is sectional drawing which shows the structure of the MOS type semiconductor device which concerns on 2nd Example of this invention. It is a manufacturing process figure which shows the manufacturing method of the MOS type semiconductor device which concerns on 2nd Example of this invention. It is sectional drawing which shows the structure of the MOS type semiconductor device which concerns on 3rd Example of this invention. It is a manufacturing process figure which shows the manufacturing method of the MOS type semiconductor device which concerns on 3rd Example of this invention.

Explanation of symbols

10 Silicon substrate 11 High concentration impurity diffusion region 12 Low concentration impurity diffusion region 13 Gate oxide film 13a Gate oxide film 14 Gate electrode 15 Side wall spacer

Claims (9)

A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and a conductivity type of the semiconductor substrate provided in a position sandwiching a channel region below the gate oxide film inside the semiconductor substrate. A pair of low-concentration impurity diffusion regions containing impurities of different conductivity types; and each of the low-concentration impurity diffusion regions within the low-concentration impurity diffusion region and spaced apart from the channel region in the gate length direction of the gate electrode A MOS type semiconductor device having a pair of high-concentration impurity diffusion regions having the same conductivity type as the impurity diffusion region and containing a higher concentration of impurities than the low-concentration impurity diffusion region,
The gate oxide film has a high-thickness portion having a thickness greater than other portions at both ends of the gate electrode in the gate length direction,
A MOS type semiconductor device, wherein each of the end portions of the high concentration impurity diffusion region facing each other across the channel region is located immediately below the high film thickness portion.   2. The MOS type semiconductor device according to claim 1, wherein the high concentration impurity diffusion region is formed by impurity implantation using the gate electrode as a mask. A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and a conductivity type of the semiconductor substrate provided in a position sandwiching a channel region below the gate oxide film inside the semiconductor substrate. A pair of low-concentration impurity diffusion regions containing impurities of different conductivity types; and each of the low-concentration impurity diffusion regions within the low-concentration impurity diffusion region and spaced apart from the channel region in the gate length direction of the gate electrode A pair of high-concentration impurity diffusion regions having the same conductivity type as the impurity diffusion region and containing a higher concentration of impurities than the low-concentration impurity diffusion region; and a gate length of the gate electrode provided on a side wall of the gate electrode A MOS type semiconductor device having a pair of spacers facing each other in a direction,
The gate oxide film has a high-thickness portion that is thicker than other portions at both ends in the gate length direction of the gate electrode,
A MOS type semiconductor device, wherein each of the end portions of the high-concentration impurity diffusion region facing each other across the channel region is located immediately below each end portion of the spacer. A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, and a conductivity type of the semiconductor substrate provided in a position sandwiching a channel region below the gate oxide film inside the semiconductor substrate. A pair of low-concentration impurity diffusion regions containing impurities of different conductivity types; and each of the low-concentration impurity diffusion regions within the low-concentration impurity diffusion region and spaced apart from the channel region in the gate length direction of the gate electrode A pair of high-concentration impurity diffusion regions having the same conductivity type as the impurity diffusion region and containing a higher concentration of impurities than the low-concentration impurity diffusion region; and a gate length of the gate electrode provided on a side wall of the gate electrode And a pair of spacers facing each other in a direction, wherein the gate oxide film has a gate length of the gate electrode. It has a high-thickness part that is thicker than the other part at one end in the direction,
The spacer formed on the gate electrode side wall on the side where the high-thickness portion is formed has a wider width in the gate length direction than the spacer facing the spacer.
A MOS type semiconductor device, wherein each of the end portions of the high-concentration impurity diffusion region facing each other across the channel region is located immediately below each end portion of the spacer.   5. The MOS semiconductor device according to claim 3, wherein the high concentration impurity diffusion region is formed by impurity implantation using the gate electrode and the spacer as a mask. A method for manufacturing a MOS semiconductor device according to claim 1,
A first oxide film forming step of forming an oxide film on the semiconductor substrate by thermal oxidation;
A second oxide film forming step of forming an oxide film having a thickness greater than that of the oxide film at both ends of the oxide film;
Depositing a gate electrode material on the oxide film formed in the first and second oxide film forming steps;
Patterning the oxide film and the gate electrode material formed in the first and second oxide film forming steps to form the gate electrode and the gate oxide film;
A first impurity implantation step of implanting impurities of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask to form the low-concentration impurity diffusion region;
A high-concentration impurity diffusion region is formed by implanting an impurity having the same conductivity type as the low-concentration impurity diffusion region and using a higher concentration than the low-concentration impurity diffusion region into the semiconductor substrate using the gate electrode as a mask. A method of manufacturing a MOS semiconductor device, comprising: a step of implanting two impurities. A method for manufacturing a MOS semiconductor device according to claim 2,
A first oxide film forming step of forming an oxide film on the semiconductor substrate by thermal oxidation;
A second oxide film forming step of forming an oxide film having a thickness larger than that of the oxide film at both ends in the gate length direction of the oxide film;
Depositing a gate electrode material on the oxide film formed in the first and second oxide film forming steps;
Patterning the oxide film and the gate electrode material formed in the first and second oxide film forming steps to form the gate electrode and the gate oxide film;
A first impurity implantation step of implanting impurities of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask to form the low-concentration impurity diffusion region;
Forming the spacer on the side wall of the gate electrode;
Using the gate electrode and the spacer as a mask, the semiconductor substrate is implanted with an impurity having the same conductivity type as the low-concentration impurity diffusion region and having a higher concentration than the low-concentration impurity diffusion region. A method of manufacturing a MOS semiconductor device, comprising: a second impurity implantation step to be formed. It is a manufacturing method of the MOS type semiconductor device according to claim 3,
A first oxide film forming step of forming an oxide film on the semiconductor substrate by thermal oxidation;
A second oxide film forming step of forming an oxide film having a thickness larger than that of the oxide film at one end in the gate length direction of the oxide film;
Depositing a gate electrode material on the oxide film formed in the first and second oxide film forming steps;
Patterning the oxide film and the gate electrode material formed in the first and second oxide film forming steps to form the gate electrode and the gate oxide film;
A first impurity implantation step of implanting impurities of a conductivity type different from that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask to form the low-concentration impurity diffusion region;
Forming the spacer on the side wall of the gate electrode;
Using the gate electrode and the spacer as a mask, the semiconductor substrate is implanted with an impurity having the same conductivity type as the low-concentration impurity diffusion region and having a higher concentration than the low-concentration impurity diffusion region. A method of manufacturing a MOS semiconductor device, comprising: a second impurity implantation step to be formed.   9. The MOS semiconductor device according to claim 6, wherein the first impurity implantation step and the second impurity implantation step are ion implantation steps performed at different irradiation angles. 10. Production method.

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