JP5457902B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor substrate for a lateral insulated gate field effect transistor and a manufacturing method thereof.

Conventionally, in the field of high withstand voltage and low on-resistance lateral field effect transistors, various efforts have been made to improve the trade-off relationship between withstand voltage and on-resistance per unit area.
For example, Patent Document 1 proposes a method in which a P offset region for forming a drain drift region is formed by projecting to the source side in order to increase the breakdown voltage.
FIG. 11 shows the configuration, and reference numeral 106 in the drawing denotes a p offset region having a low impurity concentration. As shown in FIG. 11, since the p offset region 106 having a low impurity concentration is provided under the gate oxide film 107 so as to protrude toward the source side, a depletion layer easily spreads in this region. The breakdown voltage is improved by being relaxed.
In FIG. 11, 103 is a p source region, 104 is a p drain region, 108 is a gate electrode, 109 is a LOCOS for electric field relaxation, and 110 is a second p offset region having a higher impurity concentration than the p offset region 106. .

JP-A-9-260651

However, as described above, when the p offset region 106 is formed so as to protrude toward the source side, the resistance in the low concentration region having a low impurity concentration exists in the channel region, and the on-resistance increases.
In addition, since the p offset region 106 protruding to the source side exists, a certain gate length Lga (distance between the gate electrode 108 and the LOCOS 109) is required, and the cell pitch is increased. That is, when the gate length is shortened, the p offset region 106 overlaps with the n-type region forming the channel, and the effective n-type impurity concentration is lowered. For this reason, the depletion layer in the n-type region is likely to spread, and the punch-through breakdown voltage between the source region 103 and the drain region 104 is reduced. As a result, it is necessary to secure the gate length Lga to some extent.

Also, an n-well layer 102 is formed on the surface layer of the p-type substrate 101, boron ions are implanted into the n-well layer 102 to form a p-offset region 106, and then heat treatment is performed in an oxidizing atmosphere to increase the thickness. An oxide film LOCOS (SiO ₂ ) 109 is formed.
When the LOCOS 109 is formed, the ion-implanted boron is sucked into the LOCOS 109, and the boron concentration in the vicinity of the LOCOS 109, that is, the p-type offset concentration is lowered. That is, boron segregation occurs. Therefore, the boron concentration in the vicinity of the LOCOS 106 varies, and as a result, the on-resistance increases and the on-resistance varies.
Therefore, the present invention has been made paying attention to the above-mentioned conventional unsolved problems, and aims to improve the trade-off relationship between breakdown voltage and on-resistance.

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a first conductivity type semiconductor substrate, a second conductivity type well region formed in a surface layer of the semiconductor substrate, and the second conductivity type. A source region and a drain region of the first conductivity type formed separately from each other in the conductivity type well region, an offset region provided in contact with the drain region, and between the source region and the drain region A gate electrode provided on the surface of the semiconductor substrate via a gate insulating film; a LOCOS oxide film formed on the surface layer of the offset region and having one end in contact with the drain region and the other end overlapping the gate electrode; A source electrode provided in contact with the surface of the source region; and a drain electrode provided in contact with the surface of the drain region. An upper offset region formed on the surface layer of the set region so as to protrude from the end portion on the source region side of the LOCOS oxide film to the source region side, and the LOCOS oxide film formed under the upper offset region and the LOCOS oxide film, An intermediate offset region in contact with the drain region, and a lower offset region formed below the intermediate offset region, and the upper offset region and the intermediate offset region at an end of the offset region on the source region side has a three-layer structure in which the and the lower offset region overlapping with the intermediate offset region, the upper offset region and the impurity concentration than the lower offset region rather high, the upper offset region, than the lower offset region impurity concentration is characterized by a high Ikoto.

Further, the semiconductor device according to claim 2, the depth direction of the width before Symbol intermediate offset region, along with the depletion of the upper offset region and the lower offset region, the intermediate offset region, and the upper offset region The depletion progresses in the depth direction of the overlapping equivalent region, and the equivalent region overlapping the upper offset region is set to a value that is completely depleted.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the source of the first conductivity type is formed separately from each other in a second conductivity type well region formed in a semiconductor substrate of the first conductivity type. A region and a drain region; an offset region provided in contact with the drain region; a LOCOS oxide film formed on a surface layer of the offset region and having one end in contact with the drain region and the other end extending toward the source region; The offset region is formed on the surface layer of the offset region so as to protrude from the end of the LOCOS oxide film on the source region side to the source region side, and below the upper offset region. And an intermediate offset region in contact with the LOCOS oxide film and the drain region, and formed below the intermediate offset region. A method of manufacturing a semiconductor device having a three-layer structure, wherein the upper offset region, the intermediate offset region, and the lower offset region overlap each other at an end of the offset region on the source region side. A first ion implantation step for implanting ions in the formation region of the lower offset region; and after the first ion implantation step, a thermal oxidation process is performed to form the LOCOS oxide film, and the lower offset Forming an oxide film over the entire surface including the LOCOS oxide film, and then forming a resist in a portion excluding the formation area of the intermediate offset region; As a mask for ion implantation, the intermediate offset region is formed in the intermediate offset region forming region. A second ion implantation step for performing ion implantation; and after the second ion implantation step, using the resist as a mask for ion implantation, ion implantation for forming the upper offset region in a region where the mask is not formed A third ion implantation step that performs ion implantation using an ion species having a heavier mass than that of the ion species in the second ion implantation step and with a lower acceleration energy. It is characterized by performing.
Furthermore, in the method of manufacturing a semiconductor device according to claim 4 of the present invention, in the third ion implantation step, ions are implanted into a formation region of the upper offset region, and a peak of impurity concentration is formed in the LOCOS oxide film. The ion implantation is performed so that the position is located.

  According to the semiconductor device of the present invention, the end of the offset region on the source region side is configured such that the intermediate offset region having a high impurity concentration is sandwiched between the upper offset region and the lower offset region having a lower impurity concentration than the intermediate offset region. In addition, the depletion of the upper offset region and the lower offset region promotes depletion in the depth direction of the intermediate offset region, thereby enabling depletion of the entire offset region in the depth direction, thereby reducing the electric field and resulting in withstand voltage Can be improved. Further, by forming an intermediate offset region having a high impurity concentration under the LOCOS oxide film, the resistance under the LOCOS oxide film can be reduced, and the on-resistance can be reduced by effectively reducing the drift resistance. Therefore, the breakdown voltage can be improved and the on-resistance can be reduced.

  In addition, according to the method of manufacturing a semiconductor device of the present invention, after ion implantation into the lower offset region, a LOCOS oxide film is formed, and after forming the LOCOS oxide film, ions for forming the intermediate offset region and the upper offset region Since the implantation is performed, when the LOCOS oxide film is formed, ions in the intermediate offset region formed in contact with the LOCOS film under the LOCOS oxide film are not absorbed into the LOCOS oxide film, that is, the LOCOS oxide film is formed. It is possible to avoid the occurrence of variations in the impurity concentration in the vicinity of the film, thereby causing variations in the on-resistance.

It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the mode of the depletion layer of a drain drift area | region at the time of applying a voltage to a P + type drain region. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. FIG. 5 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 4. FIG. 6 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 5. FIG. 7 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 6. FIG. 8 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 7. FIG. 9 is a cross-sectional view showing a continuation of the manufacturing process in FIG. 8. FIG. 10 is a cross-sectional view showing a continuation of the manufacturing process of FIG. 9. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the structure of the conventional semiconductor device.

Embodiments of the present invention will be described below.
As a result of intensive studies, the present inventor has found a method of increasing the breakdown voltage without overhanging a low impurity concentration region as an offset region on the source side and suppressing variations in boron concentration.
(Configuration of Semiconductor Device in the Present Invention)
FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to the present invention. The semiconductor device of FIG. 1 is a lateral field effect P-type MOS transistor.
As shown in FIG. 1, in this semiconductor device, an N-type well 2 is formed in a surface layer of a P-type substrate 1 made of a silicon substrate, and a P + type source region 3 and a P + type are formed in the N type well 2 region. Drain regions 4 are formed separately from each other.

A gate oxide film 5 is formed on the substrate surface between the P + type source region 3 and the P + type drain region 4, and a LOCOS 6 made of a thick oxide film is formed between the gate oxide film 5 and the P + type drain region 4. Is formed.
A conductive polysilicon layer 7 as a gate electrode is formed on the gate oxide film 5. At this time, the end portion on the source side of the conductive polysilicon layer 7 is formed so as to overlap the end portion on the source side of the gate oxide film 5, and the end portion on the drain side is formed on the LOCOS 6. Yes.

Further, a drain drift region 10 is formed in a part of the gate oxide film 5, under the LOCOS 6 and the P + type drain region 4.
An interlayer insulating film 15 is formed on the P + type source region 3 and the P + type drain region 4, and contact holes that lead to the P + type source region 3 and the P + type drain region 4 are provided in the interlayer insulating film 15. A source electrode 16 and a drain electrode 17 are formed.

(Description of drain drift region of horizontal electric field MOD transistor)
Next, the drain drift region 10 in FIG. 1 will be described.
The drain drift region 10 includes a first P offset region 11, a second P offset region 12 and a third P offset region 13 having different impurity concentrations. The third P offset region 13 is formed below the gate oxide film 5 so as to protrude from the end of the LOCOS 6 toward the P + type source region 3, and below the third P offset region 13, the LOCOS 6 and the P + type drain region 4. In this region, a second P offset region 12 is formed so as to surround the P + type drain region 4, and the first P offset region 11 is formed in the region equivalent to the second P offset region below the second P offset region 12. Is formed. At this time, the end portions on the source side of the first P offset region 11, the second P offset region 12, and the third P offset region 13 are formed so as to be substantially at the same position.

Specifically, for example, the first P offset region 11 is formed in a depth range of 0.4 to 1 [μm] with a peak concentration of about 6E16 [cm ⁻³ ]. Is formed in a range of depth: 0.2 to 0.4 [μm] with a peak concentration of about 2E17 [cm ⁻³ ], and the third P offset region 13 has a depth of 0 to 0.2 [μm]. [mu] m] and a peak concentration of about 8E16 [cm < ^-3 >].
The depth represents the distance in the y direction (vertical direction in FIG. 1) from the interface between the P-type substrate 1 and the insulating interlayer film.

As a result, as shown in FIG. 2, these offset regions 11 to 13 are formed in a region having a depth of 1 μm from the interface between the P-type substrate 1 and the insulating interlayer film, and in the depth direction, One P offset region 11 is formed with a width of 0.6 [μm], the second P offset region 12 is formed with a width of 0.2 [μm], and the third P offset region 13 is formed with a width of 0.2 [μm].
Further, as shown in FIG. 2, the first P offset region 11, the second P offset region 12, and the third P offset region 13 are about 0.4 [μm] from the LOCOS 6 and closer to the P + type source region 3 side. It is formed at the overhanging position. The gate length (distance between the gate electrode 7 and LOCOS 6) Lga is about 1.3 [μm].

(Reason why the on-resistance can be reduced in the semiconductor device of the present invention)
As shown in FIG. 1, in the semiconductor device according to the present invention, the source-side ends of the first P offset region 11, the second P offset region 12, and the third P offset region 13 constituting the drain drift region 10 are A sandwich structure in which the second P offset region 12 having the maximum impurity concentration is sandwiched between the first P offset region 11 and the third P offset region 13 having a lower impurity concentration than the second P offset region 12 formed so as to be substantially at the same position. It is said.
By the offset region of this sandwich structure, the electric field in the vicinity of the source side end of the LOCOS 6 under the gate electrode 7 is relaxed.

FIG. 3 shows a state of the depletion layer 14 generated in the drain drift region 10 when a voltage is applied to the P + type drain region 4 in FIG. 1, and the drain drift region 10 portion of FIG. 1 is enlarged. Is.
As shown in FIG. 3, the depletion layer extending from the first P offset region 11 and the third P offset region 13 which are low concentration regions sandwiches the second P offset region 12 which is a high concentration region, and the second P offset The depletion is promoted from the upper part and the lower part of the region 12 in the y direction, and the depletion layer expands, so that the first P offset region 11, the second P offset region 12, and the third P offset region 13 of the drain drift region 10 are formed. The entire stacked region is completely depleted in the depth direction. Therefore, the electric field is relaxed and does not become an electric field concentration portion.

Therefore, since the electric field can be relaxed by using the sandwich structure, it is not necessary to provide a low-concentration P offset region protruding to the source side. For this reason, it is possible to reduce the on-resistance generated by providing the low-concentration P offset region so as to protrude toward the source side. Further, since it is not necessary to project the P offset region, the gate electrode can be shortened accordingly, that is, the cell pitch can be reduced.
Also, the distance from the channel to the P + drain region 4 is the shortest path that passes directly under the LOCOS 6.
Here, if the resistance immediately below the LOCOS 6 is reduced, the drift resistance can be effectively reduced, that is, the on-resistance can be reduced.
Therefore, in the present invention, as shown in FIG. 1, the second P offset region 12 having a high impurity concentration is formed in the region immediately below the LOCOS 6.

Further, the end region of the LOCOS 6 under the gate electrode 7, that is, the region where the third P offset region 13 is formed, enters the drain drift region 10 for holes moving from the channel to the P + -type drain region 4. Hit the entrance. If the drain drift region 10 has a low impurity concentration, the depletion layer tends to extend, and the entrance is narrowed and the on-resistance is increased by the JFET (junction field effect transistor) effect.
Therefore, in the present invention, the impurity concentration of the third P offset region 13 is made higher than the impurity concentration of the first P offset region 11, and the depletion layer is more difficult to extend to suppress the JFET effect. The increase is prevented.

  In this specification, the depletion layer extending from the first P offset region 11 and the third P offset region 13 promotes depletion from the upper and lower portions in the y direction of the second P offset region 12 which is a high concentration region. As a result, the depletion layer spreads from the upper part and the lower part in the y direction in the second P offset region 12, and the region equivalent to the region overlapping the third P offset region 13 in the second P offset region 12 is depleted. , “The depletion in the depth direction occurs in the second P offset region 12 as the first P offset region 11 and the third P offset region 13 are depleted”.

(Reason why the breakdown voltage is improved in the semiconductor device of the present invention)
When a voltage is applied to the P + type drain region 4, the depletion layer tends to spread in the first P offset region 11 and the third P offset region 13 having a low impurity concentration.
On the other hand, since the second P offset region 12 has the highest impurity concentration, the depletion layer hardly spreads in the x direction (horizontal direction in FIG. 1), but the y direction distance is as thin as about 0.2 [μm]. Fully depleted from the y direction.

  Here, the depletion layer extending from the PN junction formed by the first P offset region 11 and the N-type well 2 reaches the second P offset region 12 relatively easily, and with respect to the second P offset region 12, y Promotes depletion from the direction. As a result, depletion of the second P offset region 12 proceeds, and as a result, as shown in FIG. 3, the end of the drain drift region 10 on the P + type source region 3 side is depleted over the entire depth direction. It becomes possible. Therefore, the withstand voltage can be improved by relaxing the electric field.

(Method for Manufacturing Semiconductor Device of the Present Invention)
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
First, as shown in FIG. 4, the surface of the P-type substrate 21 made of a silicon substrate having a resistivity of about 5 to 10 [Ω · cm] is subjected to steam oxidation in a temperature environment of about 900 to 1000 [° C.] An oxide film (SiO ₂ film) 22 having a thickness of 100 to 200 [nm] is formed. Further, an Si ₃ N ₄ film 23 having a film thickness of about 110 to 120 [nm] is formed on the entire surface of the oxide film 22 by a low pressure CVD method. As a result, the oxide film 22 and the Si ₃ N ₄ film 23 are laminated on the P-type substrate 21 in this order.

Next, as shown in FIG. 5, a photoresist 24 having an opening in an element isolation layer (LOCOS) formation region is formed by a known photolithography technique. Thereafter, the Si ₃ N ₄ film 23 is removed by a known etching method using the photoresist 24 as a mask, for example, reactive ion etching (RIE) so as to leave the Si ₃ N ₄ film 23 only on the active region. To do. Then, the photoresist 24 is removed.

Next, a photoresist for ion implantation having an opening in the N-type well formation region is newly formed, and ion implantation is performed using this photoresist as a mask, and phosphorus (P) is 5 × 10 ¹² to 1 × 10 ^13. / Cm ^{2 is} introduced.
Subsequently, after removing the photoresist for ion implantation, heat treatment is performed in a temperature environment of about 1100 to 1300 [° C.] to form an N-type well 25 (FIG. 6).

Next, as shown in FIG. 7, a photoresist 26 having an opening is formed in the formation region of the P offset region (drain drift region), ion implantation is performed using the photoresist 26 as a mask, and boron (B) is accelerated. Ions are implanted under the conditions of energy 350 [keV] and a dose of 5 × 10 ¹² cm ² to form a P offset impurity implantation region 27. The peak position of the impurity concentration of boron immediately after ion implantation is a position where the depth from the surface of the P-type substrate 21 is 800 [nm]. The introduced impurities are distributed in a range of about 700 to 900 [nm] from the surface of the P-type substrate 21.

Next, after removing the photoresist 26, steam oxidation is performed in a temperature environment of about 950 to 1000 [° C.] to form a LOCOS 28 made of an oxide film having a thickness of about 400 to 500 [nm].
The boron ion-implanted into the P offset impurity implantation region 27 is diffused by the heat of this oxidation process, and a P offset region 29 is formed. At this time, since boron is implanted sufficiently deep by ion implantation, boron does not diffuse to the interface between the LOCOS 28 made of an oxide film and the P-type substrate 21. That is, boron segregation to LOCOS 28 made of SiO ₂ does not occur during LOCOS formation.

Therefore, it is possible to suppress a decrease in boron concentration and variations in the vicinity of the LOCOS 28 in the drain drift region, and as a result, it is possible to suppress an increase in ON resistance and variations.
Thereafter, the Si ₃ N ₄ film 23 is removed by hot phosphoric acid, and then the oxide film (SiO ₂ film) 22 is removed using a hydrofluoric acid (HF) chemical solution. As a result, the structure shown in FIG. 8 is obtained.

Subsequently, as shown in FIG. 9, steam oxidation is performed in a temperature environment of 900 to 1000 [° C.], and an oxide film (SiO ₂ film) having a thickness of 200 to 300 [nm] is formed on the surface of the N-type well layer 25. 30 is formed.
Next, as shown in FIG. 9, a photoresist 31 having an opening in the second P offset formation region is formed, and boron (B) is used as an acceleration energy of 100 to 150 using the photoresist 31 as a mask for ion implantation. Ion implantation is performed under conditions of [keV] and a dose of about 1 × 10 ¹² to 1 × 10 ¹³ / cm ² .

Thereby, boron (B) is implanted into the formation region of the second P offset region via the oxide film 30 and the LOCOS 28, and the second P offset region 32 is formed.
Furthermore, using the same photoresist 31 as a mask for ion implantation, boron difluoride (BF ₂ ) is accelerated energy 50 to 100 [keV] and dose amount 1 × 10 ¹² to 1 × 10 ¹³ / cm ² . Under the conditions, ion implantation for forming the third P offset region 33 is performed.

Thereby, boron (B) is implanted through the oxide film 30 and the LOCOS 28. Here, the ion implantation for forming the third P offset region 33 is performed at an acceleration energy of 50 to 100 [keV], which is lower in energy than the ion implantation for forming the second P offset region 32. This is because the peak position of the impurity concentration immediately after ion implantation in the third P offset region 33 is positioned in the LOCOS 28, and “BF ₂ +” having a heavy mass is used as the ion species for ion implantation. Ion implantation is performed with low acceleration energy.

  As a result, boron (B) is implanted through the oxide film 30 and the LOCOS 28 and is ion-implanted with a relatively low acceleration energy, so that boron (B) is formed between the P-type substrate 1 and the oxide film 30. Only a relatively shallow region can be reached from the interface. As a result, ion implantation is performed in the formation region of the third P offset region 33 and the peak position of the impurity concentration is located in the LOCOS 28. Therefore, it is possible to selectively introduce impurities into only the surface of the P-type substrate 21 in the opening, that is, the formation region of the third P offset region 33 without affecting the boron concentration profile of the second P offset region 32. it can. By this method, it is possible to form the second P offset region 32 and the third P offset region 33 having different impurity concentrations with the same photoresist 31.

Further, ion implantation is performed after the LOCOS 28 formation step. Here, when LOCOS is formed in this ion-implanted region after ion implantation as in the prior art, there is a possibility that the boron concentration in the vicinity of LOCOS may be lowered or varied. However, in the present invention, as described above, when ion implantation is performed, since the LOCOS 28 has already been formed, it is possible to suppress the decrease in boron concentration and the occurrence of variations. Variations can be suppressed.
Subsequently, the photoresist 31 is removed, and the oxide film (SiO ₂ film) 30 is removed using a hydrofluoric acid (HF) chemical solution.

Further, thermal oxidation is performed in a temperature environment of 800 to 900 [° C.] to form a gate oxide film 34 on the surface of the N-type well layer 25 as shown in FIG.
Next, a conductive polysilicon layer 35 having a thickness of about 350 to 400 [nm] is formed on the entire surface by CVD. Thereafter, a photoresist is formed in the gate formation region by a known photolithography technique, the conductive polysilicon layer 35 other than the gate formation region is removed by a known etching method using the photoresist as a mask, and the photoresist is removed.

Then, a photoresist for forming an impurity implantation region having openings in the P + type source and P + type drain formation regions is formed by a known photolithography technique, and a dose amount of 1 × 10 is formed in the P + type source and P + type drain formation regions. Boron (B) of about ¹⁵ to 1 × 10 ¹⁶ / cm ² is ion-implanted. Thereby, a P + type source impurity implantation region and a P + type drain impurity implantation region are formed.
Subsequently, after removing the photoresist for forming the impurity implantation region, heat treatment is performed in a temperature environment of about 800 to 900 [deg.] C. to diffuse boron in the P + type source impurity implantation region and the P + type drain impurity implantation region. Thus, a P + type source region and a P + type drain region are formed. Further, an interlayer insulating film (SiO ₂ film) of about 600 to 700 [nm] is deposited on the entire surface by CVD.

Thereafter, a photoresist for electrode formation having openings in the source, gate and drain electrode formation regions of the interlayer insulating film (SiO ₂ film) is formed by a known photolithography technique, and known etching is performed using the photoresist as a mask. The interlayer insulating film is etched by a method such as RIE. Then, after removing the photoresist for electrode formation, a wiring metal layer including a barrier metal layer such as Ti / TiN or AL is deposited in each electrode formation opening formed in the interlayer insulating film.

Further, the wiring metal layer is patterned by a known photolithography technique and RIE to form a source electrode and a drain electrode. Thereby, the semiconductor device of the present invention having a structure as shown in FIG. 1 is obtained.
When the breakdown voltage and on-resistance were measured for the semiconductor device thus fabricated, it was confirmed that the breakdown voltage was 40 [V] and the on-resistance (RonA) was 0.10 [Ω · mm ² ]. At this time, the gate length Lga is about 1.3 [μm].

In contrast, in the case of the conventional lateral field effect transistor shown in FIG. 11, the breakdown voltage is 30 [V] and the on-resistance (RonA) is 0.25 [Ω · mm ² ]. Also, as shown in FIG. 12, a p-offset region 306 having a low impurity concentration is formed on the entire surface of the device, and a second p-offset region 310 is formed only below the LOCOS 309, thereby increasing the drain drift resistance due to the junction FET effect. When this is prevented, the breakdown voltage is 34 [V] and the on-resistance (RonA) is 0.17 [Ω · mm ² ]. The gate length Lga at this time is about 2 [μm].

Accordingly, it was confirmed that the trade-off between the breakdown voltage and the on-resistance can be improved by adopting the configuration of the semiconductor device of the present invention described above.
It was also confirmed that the gate length Lga can be shortened along with the improvement of the trade-off.
Further, by manufacturing a semiconductor device according to the procedure described in the above embodiment, in principle, segregation of boron does not occur when the LOCOS 6 is manufactured. Therefore, there is no variation in on-resistance due to boron segregation.

In the above embodiment, the case where the lateral electric field MOS transistor is formed on the P-type substrate 1 has been described. However, the present invention is not limited to this, and the present invention can also be applied to the case where it is formed on an N-type substrate.
Here, in the above embodiment, the P-type substrate 1 corresponds to the semiconductor substrate, the N-type well 2 corresponds to the second conductivity type well region, and the P + type source region 3 and the P + type drain region 4 correspond to the first conductivity type. The offset region 10 corresponds to the offset region, the LOCOS 6 corresponds to the LOCOS oxide film, the first P offset region 11 corresponds to the lower offset region, and the second P offset region 12 corresponds to the source and drain regions of the mold. Corresponds to the intermediate offset region, and the third P offset region 13 corresponds to the upper offset region.

1 P-type substrate 2 N-type well 3 P + type source region 4 P + type drain region 5 Gate oxide film 6 LOCOS
7 Conductive polysilicon layer (gate electrode)
10 drain drift region 11 first P offset region 12 second P offset region 13 third P offset region 14 depletion layer 15 interlayer insulating film 16 source electrode 17 drain electrode

Claims (4)

A first conductivity type semiconductor substrate;
A second conductivity type well region formed in the surface layer of the semiconductor substrate;
A source region and a drain region of the first conductivity type formed separately from each other in the second conductivity type well region;
An offset region provided in contact with the drain region;
A gate electrode provided on the semiconductor substrate surface between the source region and the drain region via a gate insulating film;
A LOCOS oxide film formed on the surface layer of the offset region and having one end in contact with the drain region and the other end overlapping the gate electrode;
A source electrode provided in contact with the surface of the source region;
A drain electrode provided in contact with the surface of the drain region,
The offset region is
An upper offset region formed on the surface layer of the offset region so as to protrude from the end of the LOCOS oxide film on the source region side to the source region side;
An intermediate offset region formed under the upper offset region and in contact with the LOCOS oxide film and the drain region;
A lower offset region formed below the intermediate offset region,
And the upper offset region, the intermediate offset region, and the lower offset region overlap each other at the end of the offset region on the source region side,
The intermediate offset region, the upper offset region and the impurity concentration than the lower offset region rather high, the upper offset region, a semiconductor device wherein the impurity concentration than the lower offset region characterized by high Ikoto. The width in the depth direction of the intermediate offset region is depleted in the depth direction of an equivalent region of the intermediate offset region that overlaps the upper offset region as the upper offset region and the lower offset region are depleted. in semiconductor device according to claim 1 Symbol mounting, characterized in that the equivalent region overlapping with the upper offset region is set to a value which completely depleted. A source region and a drain region of the first conductivity type formed separately from each other in a second conductivity type well region formed in the semiconductor substrate of the first conductivity type;
An offset region provided in contact with the drain region;
A LOCOS oxide film formed on the surface layer of the offset region and having one end in contact with the drain region and the other end extending toward the source region;
The offset region is
An upper offset region formed on the surface layer of the offset region so as to protrude from the end of the LOCOS oxide film on the source region side to the source region side;
An intermediate offset region formed under the upper offset region and in contact with the LOCOS oxide film and the drain region;
A lower offset region formed below the intermediate offset region,
And a manufacturing method of a semiconductor device having a three-layer structure in which the upper offset region, the intermediate offset region, and the lower offset region overlap with an end portion of the offset region on the source region side,
A first ion implantation step of implanting ions into the formation region of the lower offset region;
After the first ion implantation step, a thermal oxidation process is performed to form the LOCOS oxide film, and an oxidation step of diffusing ions implanted into the formation region of the lower offset region;
After forming an oxide film on the entire surface including the LOCOS oxide film, a resist is formed in a portion excluding the formation region of the intermediate offset region, and the resist is used as a mask for ion implantation in the formation region of the intermediate offset region. A second ion implantation step for performing ion implantation for forming an intermediate offset region;
After the second ion implantation step, there is provided a third ion implantation step in which the resist is used as an ion implantation mask and ion implantation for forming the upper offset region is performed in a region where the mask is not formed. And
In the third ion implantation step, a method of manufacturing a semiconductor device is characterized in that ion implantation is performed using ion species having a heavier mass than the ion species in the second ion implantation step and with lower acceleration energy. The third ion implantation step includes
4. The method of manufacturing a semiconductor device according to claim 3, wherein ions are implanted into a formation region of the upper offset region and the ion implantation is performed so that a peak position of impurity concentration is located in the LOCOS oxide film. .

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