CN113394102A - NMOS device manufacturing method and NMOS device - Google Patents
NMOS device manufacturing method and NMOS device Download PDFInfo
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- CN113394102A CN113394102A CN202110568331.5A CN202110568331A CN113394102A CN 113394102 A CN113394102 A CN 113394102A CN 202110568331 A CN202110568331 A CN 202110568331A CN 113394102 A CN113394102 A CN 113394102A
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- nmos device
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- nmos
- well region
- ion implantation
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 36
- 230000008569 process Effects 0.000 abstract description 23
- 230000006872 improvement Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 230000008859 change Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 4
- 238000002474 experimental method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing an NMOS (N-channel metal oxide semiconductor) device, which comprises the step of performing P-type ion implantation to form a well region before performing thermal growth of an oxide layer on a silicon wafer. Compared with the prior art, the method effectively improves the electron mobility of the metal oxide semiconductor NMOS device, obtains higher saturation current, and realizes the improvement of the device speed under the same driving voltage. The method is compatible with the traditional process, only needs to change the sequence of the process flow without increasing or decreasing any process flow, is easy to realize and has low cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an NMOS device and an NMOS device.
Background
Since the advent of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, device sizes have been reduced following moore's law, and higher performance and lower cost have been achieved only by ever decreasing device sizes and increasing the integration density of integrated circuits. However, as the demand of integrated circuits is more and more diversified and the device size is smaller, the electron mobility in the device needs to be continuously improved, so as to reduce the power consumption and improve the current carrying capability of the device, and therefore how to improve the electron mobility of the device is a constant concern.
The electron mobility and the carrier concentration together determine the conductivity of the semiconductor material, and the larger the mobility is, the smaller the resistivity is, and the smaller the power consumption is and the larger the current carrying capacity is when the same current is passed. In addition, electron mobility can affect the operating frequency of the device, and the most significant limitation of the frequency response characteristic of a bipolar transistor is the time for minority carriers to transit the base region. The higher the mobility is, the shorter the required transit time is, and the cut-off frequency of the transistor is in direct proportion to the carrier mobility of the base region material, so that the carrier mobility is improved, the power consumption can be reduced, the current carrying capacity of the device is improved, and the switching conversion speed of the transistor is improved.
In the conventional CMOS process technology, theoretically, the electrical parameters of the device should be substantially the same on the premise that the well region ion implantation, the gate oxide thickness, the isolation sidewall, the shallow doped ion implantation, and the source/drain ion implantation are the same. However, experiments show that the threshold voltage of the NMOS device is too high and the saturation current (Idsat) is lower than the predicted target value, and as shown in the following graph, it can be clearly seen that Idsat of the NMOS device is lower than the target value. Therefore, it is an urgent problem to find a reason why the device driving current becomes low, that is, the electron mobility becomes low, and to improve the device performance.
Disclosure of Invention
The invention aims to solve the technical problem of how to improve the electron mobility of an NMOS device and achieve the purpose of increasing the saturation current.
The invention provides a method for manufacturing an NMOS (N-channel metal oxide semiconductor) device, which comprises the steps of carrying out P-type ion implantation to form a well region before carrying out thermal growth of an oxide layer on a silicon wafer. The thermal growth of the oxide layer changes the ion concentration of the well region.
Preferably, the P-type ions contain boron.
Preferably, the temperature of the thermal growth of the oxide layer is 800 ℃.
Preferably, the well region is plural.
The invention also provides an NMOS device manufactured by any one of the manufacturing methods.
Preferably, the channel length of the NMOS device is not less than 27 nanometers.
Compared with the prior art, the method effectively improves the electron mobility of the metal oxide semiconductor NMOS device, obtains higher saturation current, and realizes the improvement of the device speed under the same driving voltage. The method is compatible with the traditional process, only needs to change the sequence of the process flow without increasing or decreasing any process flow, is easy to realize and has low cost.
Drawings
FIG. 1 is a schematic diagram of a saturation current experiment in a prior art process.
FIG. 2 is a schematic diagram of a method of differentiating embodiments from the prior art.
Detailed Description
In the conventional CMOS process technology, theoretically, the electrical parameters of the device should be substantially the same on the premise that the well region ion implantation, the gate oxide thickness, the isolation sidewall, the shallow doped ion implantation, and the source/drain ion implantation are the same. However, experiments show that the threshold voltage of the NMOS device is too high and the saturation current (Idsat) is lower than the predicted target value, and as shown in fig. 1, it can be clearly seen that the saturation current Idsat of the NMOS device is lower than the target value. Therefore, it is an urgent problem to find a reason why the device driving current becomes low, that is, the electron mobility becomes low, and to improve the device performance.
The mobility (μ) and the speed (v) of the carriers are directly related to the external electric field (E) acting on it: v ═ μ · E, it follows that increasing the mobility of a carrier can increase its velocity, directly increasing the drive current of the device.
The conventional manufacturing method of the prior art CMOS process has the following flow:
step 1, ion implantation of a high voltage N well region (HVNW);
step 2, thermally growing an Oxide layer (Pad Oxide);
step 3, injecting P-type ions to form a well region;
step 4, forming a device oxide layer;
step 5, grid formation, shallow doped source and drain ion implantation and source and drain region ion implantation;
step 6, manufacturing metal silicide to form effective ohmic contact;
step 7, manufacturing a back-end metal interconnection process;
step 8, Wafer Acceptance Test (Wafer Acceptance Test WAT).
The present invention is described in the following with reference to the above-mentioned CMOS process, but it should be noted that the present invention is not limited to the above-mentioned CMOS process improvement. And in the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the practice of the invention may not necessarily be limited to these specific details. On the other hand, in order to avoid obscuring the present invention, the following examples will only describe the details of the manufacturing process flow which is different from the above.
Example 1:
in the manufacturing method of the NMOS device of this embodiment, the order of the step 2 and the step 3 is replaced. Because the process only needs to change the sequence of the process flow without increasing or decreasing any process flow, the overall electrical property of the device is not greatly influenced, and the improvement of the electron mobility enables the device to realize higher saturation current without influencing the overall performance of the device under the same working voltage.
In this embodiment, as shown in fig. 2, the left side is the steps 2 and 3 in the prior art, and the process steps in this embodiment are adjusted to the right side. The process flow sequence of thermal growth of the oxide layer (Pad oxide) and P-type ion implantation of the well region is adjusted, the P-type ion implantation of the well region is firstly carried out, and then the oxide layer (Pad oxide) is grown, wherein the P-type ions contain boron. The oxide layer (Pad oxide) grows in the thermal oxidation (800 ℃) process to absorb boron to change the ion concentration of the well region, so that the electron mobility of the device is improved, and the electron mobility of the narrow-width device is improved greatly.
The method is completed before shallow doping and source-drain ion implantation of the device, so that the saturation current of the device is improved on the premise of not causing great influence on the overall electrical property of the device.
The conventional process and the improved process flow obtain saturation current results, and saturation currents of different channel widths under the channel lengths of 0.0315um and 0.027um are measured respectively, and for a device with the channel length L of 0.0315um, the improved process saturation currents are respectively increased by 22.4%, 13.9%, 16% and 12.9% (for the channel width W of 0.09um,0.27um,0.54um and 2.7um) compared with those before the improvement. For the device with the channel length L being 0.027um, the process saturation current after improvement is respectively improved by 14.7%, 16.2%, 11.5% and 10.3% compared with that before improvement (for the channel width W being 0.09um,0.27um,0.54um and 2.7um), so that the saturation current is obviously improved no matter which channel length device is used, and the saturation current is improved more particularly for the narrow width device. Therefore, the electron mobility of the device can be improved by adjusting the sequence of the Pad oxide thermal growth and well region ion implantation process flow, so that the saturation current of the device is improved, and better device performance is realized.
Example 2:
this embodiment provides an NMOS device fabricated by the fabrication method of embodiment 1. The method is particularly suitable for the NMOS device with the channel length not less than 27 nanometers.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (7)
1. A manufacturing method of an NMOS device is characterized in that:
before the thermal growth of the oxide layer on the silicon chip, P-type ion implantation is carried out to form a well region.
2. The device manufacturing method of claim 1, wherein:
the P-type ions contain boron.
3. The device manufacturing method of claim 1, wherein:
the temperature of the thermal growth of the oxide layer is 800 ℃.
4. The device manufacturing method of claim 1, wherein:
the well region is a plurality of.
5. The device manufacturing method of claim 1, wherein:
the thermal growth of the oxide layer changes the ion concentration of the well region.
6. An NMOS device, characterized in that:
manufactured by the manufacturing method according to claims 1 to 4.
7. The NMOS device of claim 6, wherein:
the channel length of the NMOS device is not less than 27 nanometers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110568331.5A CN113394102A (en) | 2021-05-25 | 2021-05-25 | NMOS device manufacturing method and NMOS device |
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| CN202110568331.5A CN113394102A (en) | 2021-05-25 | 2021-05-25 | NMOS device manufacturing method and NMOS device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62162360A (en) * | 1986-01-13 | 1987-07-18 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| CN1198250A (en) * | 1996-06-24 | 1998-11-04 | 松下电器产业株式会社 | Method for manufacturing semiconductor device |
| JP2004119616A (en) * | 2002-09-25 | 2004-04-15 | Fuji Electric Device Technology Co Ltd | Method for manufacturing semiconductor device |
| CN101336473A (en) * | 2006-01-30 | 2008-12-31 | 住友电气工业株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP2011204998A (en) * | 2010-03-26 | 2011-10-13 | Asahi Kasei Electronics Co Ltd | Semiconductor device and method for manufacturing the same |
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
| CN112002755A (en) * | 2020-08-20 | 2020-11-27 | 合肥工业大学 | Novel LDMOS device structure and preparation method and performance thereof |
-
2021
- 2021-05-25 CN CN202110568331.5A patent/CN113394102A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62162360A (en) * | 1986-01-13 | 1987-07-18 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| CN1198250A (en) * | 1996-06-24 | 1998-11-04 | 松下电器产业株式会社 | Method for manufacturing semiconductor device |
| JP2004119616A (en) * | 2002-09-25 | 2004-04-15 | Fuji Electric Device Technology Co Ltd | Method for manufacturing semiconductor device |
| CN101336473A (en) * | 2006-01-30 | 2008-12-31 | 住友电气工业株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP2011204998A (en) * | 2010-03-26 | 2011-10-13 | Asahi Kasei Electronics Co Ltd | Semiconductor device and method for manufacturing the same |
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
| CN112002755A (en) * | 2020-08-20 | 2020-11-27 | 合肥工业大学 | Novel LDMOS device structure and preparation method and performance thereof |
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